Revision 39d51eb8 hw/mips_timer.c
| b/hw/mips_timer.c | ||
|---|---|---|
| 28 | 28 |
uint64_t now, next; |
| 29 | 29 |
uint32_t tmp; |
| 30 | 30 |
|
| 31 |
if (env->CP0_Cause & (1 << CP0Ca_DC)) |
|
| 32 |
return; |
|
| 33 |
|
|
| 31 | 34 |
tmp = count; |
| 32 | 35 |
if (count == compare) |
| 33 | 36 |
tmp++; |
| ... | ... | |
| 57 | 60 |
void cpu_mips_store_compare (CPUState *env, uint32_t value) |
| 58 | 61 |
{
|
| 59 | 62 |
cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
| 63 |
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
|
| 64 |
env->CP0_Cause &= ~(1 << CP0Ca_TI); |
|
| 60 | 65 |
cpu_mips_irq_request(env, 7, 0); |
| 61 | 66 |
} |
| 62 | 67 |
|
| ... | ... | |
| 71 | 76 |
} |
| 72 | 77 |
#endif |
| 73 | 78 |
cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
| 79 |
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
|
| 80 |
env->CP0_Cause |= 1 << CP0Ca_TI; |
|
| 74 | 81 |
cpu_mips_irq_request(env, 7, 1); |
| 75 | 82 |
} |
| 76 | 83 |
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