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1 | e8af50a3 | bellard | /*
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2 | e8af50a3 | bellard | * sparc helpers
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3 | 5fafdf24 | ths | *
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4 | 83469015 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | e8af50a3 | bellard | *
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6 | e8af50a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | e8af50a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | e8af50a3 | bellard | * License as published by the Free Software Foundation; either
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9 | e8af50a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | e8af50a3 | bellard | *
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11 | e8af50a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | e8af50a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | e8af50a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | e8af50a3 | bellard | * Lesser General Public License for more details.
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15 | e8af50a3 | bellard | *
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16 | e8af50a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | e8af50a3 | bellard | * License along with this library; if not, write to the Free Software
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18 | e8af50a3 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | e8af50a3 | bellard | */
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20 | ee5bbe38 | bellard | #include <stdarg.h> |
21 | ee5bbe38 | bellard | #include <stdlib.h> |
22 | ee5bbe38 | bellard | #include <stdio.h> |
23 | ee5bbe38 | bellard | #include <string.h> |
24 | ee5bbe38 | bellard | #include <inttypes.h> |
25 | ee5bbe38 | bellard | #include <signal.h> |
26 | ee5bbe38 | bellard | #include <assert.h> |
27 | ee5bbe38 | bellard | |
28 | ee5bbe38 | bellard | #include "cpu.h" |
29 | ee5bbe38 | bellard | #include "exec-all.h" |
30 | ca10f867 | aurel32 | #include "qemu-common.h" |
31 | e8af50a3 | bellard | |
32 | e80cfcfc | bellard | //#define DEBUG_MMU
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33 | 64a88d5d | blueswir1 | //#define DEBUG_FEATURES
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34 | f2bc7e7f | blueswir1 | //#define DEBUG_PCALL
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35 | e8af50a3 | bellard | |
36 | 22548760 | blueswir1 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
37 | c48fcb47 | blueswir1 | |
38 | e8af50a3 | bellard | /* Sparc MMU emulation */
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39 | e8af50a3 | bellard | |
40 | e8af50a3 | bellard | /* thread support */
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41 | e8af50a3 | bellard | |
42 | e8af50a3 | bellard | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
43 | e8af50a3 | bellard | |
44 | e8af50a3 | bellard | void cpu_lock(void) |
45 | e8af50a3 | bellard | { |
46 | e8af50a3 | bellard | spin_lock(&global_cpu_lock); |
47 | e8af50a3 | bellard | } |
48 | e8af50a3 | bellard | |
49 | e8af50a3 | bellard | void cpu_unlock(void) |
50 | e8af50a3 | bellard | { |
51 | e8af50a3 | bellard | spin_unlock(&global_cpu_lock); |
52 | e8af50a3 | bellard | } |
53 | e8af50a3 | bellard | |
54 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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55 | 9d893301 | bellard | |
56 | 22548760 | blueswir1 | int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, |
57 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
58 | 9d893301 | bellard | { |
59 | 878d3096 | bellard | if (rw & 2) |
60 | 22548760 | blueswir1 | env1->exception_index = TT_TFAULT; |
61 | 878d3096 | bellard | else
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62 | 22548760 | blueswir1 | env1->exception_index = TT_DFAULT; |
63 | 9d893301 | bellard | return 1; |
64 | 9d893301 | bellard | } |
65 | 9d893301 | bellard | |
66 | 9d893301 | bellard | #else
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67 | e8af50a3 | bellard | |
68 | 3475187d | bellard | #ifndef TARGET_SPARC64
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69 | 83469015 | bellard | /*
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70 | 83469015 | bellard | * Sparc V8 Reference MMU (SRMMU)
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71 | 83469015 | bellard | */
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72 | e8af50a3 | bellard | static const int access_table[8][8] = { |
73 | a764a566 | blueswir1 | { 0, 0, 0, 0, 8, 0, 12, 12 }, |
74 | a764a566 | blueswir1 | { 0, 0, 0, 0, 8, 0, 0, 0 }, |
75 | a764a566 | blueswir1 | { 8, 8, 0, 0, 0, 8, 12, 12 }, |
76 | a764a566 | blueswir1 | { 8, 8, 0, 0, 0, 8, 0, 0 }, |
77 | a764a566 | blueswir1 | { 8, 0, 8, 0, 8, 8, 12, 12 }, |
78 | a764a566 | blueswir1 | { 8, 0, 8, 0, 8, 0, 8, 0 }, |
79 | a764a566 | blueswir1 | { 8, 8, 8, 0, 8, 8, 12, 12 }, |
80 | a764a566 | blueswir1 | { 8, 8, 8, 0, 8, 8, 8, 0 } |
81 | e8af50a3 | bellard | }; |
82 | e8af50a3 | bellard | |
83 | 227671c9 | bellard | static const int perm_table[2][8] = { |
84 | 227671c9 | bellard | { |
85 | 227671c9 | bellard | PAGE_READ, |
86 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
87 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
88 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
89 | 227671c9 | bellard | PAGE_EXEC, |
90 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
91 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
92 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC |
93 | 227671c9 | bellard | }, |
94 | 227671c9 | bellard | { |
95 | 227671c9 | bellard | PAGE_READ, |
96 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
97 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
98 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
99 | 227671c9 | bellard | PAGE_EXEC, |
100 | 227671c9 | bellard | PAGE_READ, |
101 | 227671c9 | bellard | 0,
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102 | 227671c9 | bellard | 0,
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103 | 227671c9 | bellard | } |
104 | e8af50a3 | bellard | }; |
105 | e8af50a3 | bellard | |
106 | c48fcb47 | blueswir1 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
107 | c48fcb47 | blueswir1 | int *prot, int *access_index, |
108 | c48fcb47 | blueswir1 | target_ulong address, int rw, int mmu_idx) |
109 | e8af50a3 | bellard | { |
110 | e80cfcfc | bellard | int access_perms = 0; |
111 | e80cfcfc | bellard | target_phys_addr_t pde_ptr; |
112 | af7bf89b | bellard | uint32_t pde; |
113 | af7bf89b | bellard | target_ulong virt_addr; |
114 | 6ebbf390 | j_mayer | int error_code = 0, is_dirty, is_user; |
115 | e80cfcfc | bellard | unsigned long page_offset; |
116 | e8af50a3 | bellard | |
117 | 6ebbf390 | j_mayer | is_user = mmu_idx == MMU_USER_IDX; |
118 | e8af50a3 | bellard | virt_addr = address & TARGET_PAGE_MASK; |
119 | 40ce0a9a | blueswir1 | |
120 | e8af50a3 | bellard | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
121 | 40ce0a9a | blueswir1 | // Boot mode: instruction fetches are taken from PROM
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122 | 5578ceab | blueswir1 | if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) { |
123 | 58a770f3 | blueswir1 | *physical = env->prom_addr | (address & 0x7ffffULL);
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124 | 40ce0a9a | blueswir1 | *prot = PAGE_READ | PAGE_EXEC; |
125 | 40ce0a9a | blueswir1 | return 0; |
126 | 40ce0a9a | blueswir1 | } |
127 | 0f8a249a | blueswir1 | *physical = address; |
128 | 227671c9 | bellard | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
129 | e80cfcfc | bellard | return 0; |
130 | e8af50a3 | bellard | } |
131 | e8af50a3 | bellard | |
132 | 7483750d | bellard | *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
133 | 5dcb6b91 | blueswir1 | *physical = 0xffffffffffff0000ULL;
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134 | 7483750d | bellard | |
135 | e8af50a3 | bellard | /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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136 | e8af50a3 | bellard | /* Context base + context number */
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137 | 3deaeab7 | blueswir1 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
138 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
139 | e8af50a3 | bellard | |
140 | e8af50a3 | bellard | /* Ctx pde */
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141 | e8af50a3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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142 | e80cfcfc | bellard | default:
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143 | e8af50a3 | bellard | case 0: /* Invalid */ |
144 | 0f8a249a | blueswir1 | return 1 << 2; |
145 | e80cfcfc | bellard | case 2: /* L0 PTE, maybe should not happen? */ |
146 | e8af50a3 | bellard | case 3: /* Reserved */ |
147 | 7483750d | bellard | return 4 << 2; |
148 | e80cfcfc | bellard | case 1: /* L0 PDE */ |
149 | 0f8a249a | blueswir1 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
150 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
151 | e8af50a3 | bellard | |
152 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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153 | 0f8a249a | blueswir1 | default:
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154 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
155 | 0f8a249a | blueswir1 | return (1 << 8) | (1 << 2); |
156 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
157 | 0f8a249a | blueswir1 | return (1 << 8) | (4 << 2); |
158 | 0f8a249a | blueswir1 | case 1: /* L1 PDE */ |
159 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
160 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
161 | e8af50a3 | bellard | |
162 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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163 | 0f8a249a | blueswir1 | default:
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164 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
165 | 0f8a249a | blueswir1 | return (2 << 8) | (1 << 2); |
166 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
167 | 0f8a249a | blueswir1 | return (2 << 8) | (4 << 2); |
168 | 0f8a249a | blueswir1 | case 1: /* L2 PDE */ |
169 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
170 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
171 | e8af50a3 | bellard | |
172 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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173 | 0f8a249a | blueswir1 | default:
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174 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
175 | 0f8a249a | blueswir1 | return (3 << 8) | (1 << 2); |
176 | 0f8a249a | blueswir1 | case 1: /* PDE, should not happen */ |
177 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
178 | 0f8a249a | blueswir1 | return (3 << 8) | (4 << 2); |
179 | 0f8a249a | blueswir1 | case 2: /* L3 PTE */ |
180 | 0f8a249a | blueswir1 | virt_addr = address & TARGET_PAGE_MASK; |
181 | 77f193da | blueswir1 | page_offset = (address & TARGET_PAGE_MASK) & |
182 | 77f193da | blueswir1 | (TARGET_PAGE_SIZE - 1);
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183 | 0f8a249a | blueswir1 | } |
184 | 0f8a249a | blueswir1 | break;
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185 | 0f8a249a | blueswir1 | case 2: /* L2 PTE */ |
186 | 0f8a249a | blueswir1 | virt_addr = address & ~0x3ffff;
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187 | 0f8a249a | blueswir1 | page_offset = address & 0x3ffff;
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188 | 0f8a249a | blueswir1 | } |
189 | 0f8a249a | blueswir1 | break;
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190 | 0f8a249a | blueswir1 | case 2: /* L1 PTE */ |
191 | 0f8a249a | blueswir1 | virt_addr = address & ~0xffffff;
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192 | 0f8a249a | blueswir1 | page_offset = address & 0xffffff;
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193 | 0f8a249a | blueswir1 | } |
194 | e8af50a3 | bellard | } |
195 | e8af50a3 | bellard | |
196 | e8af50a3 | bellard | /* update page modified and dirty bits */
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197 | b769d8fe | bellard | is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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198 | e8af50a3 | bellard | if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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199 | 0f8a249a | blueswir1 | pde |= PG_ACCESSED_MASK; |
200 | 0f8a249a | blueswir1 | if (is_dirty)
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201 | 0f8a249a | blueswir1 | pde |= PG_MODIFIED_MASK; |
202 | 49be8030 | bellard | stl_phys_notdirty(pde_ptr, pde); |
203 | e8af50a3 | bellard | } |
204 | e8af50a3 | bellard | /* check access */
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205 | e8af50a3 | bellard | access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
206 | e80cfcfc | bellard | error_code = access_table[*access_index][access_perms]; |
207 | d8e3326c | bellard | if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
208 | 0f8a249a | blueswir1 | return error_code;
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209 | e8af50a3 | bellard | |
210 | e8af50a3 | bellard | /* the page can be put in the TLB */
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211 | 227671c9 | bellard | *prot = perm_table[is_user][access_perms]; |
212 | 227671c9 | bellard | if (!(pde & PG_MODIFIED_MASK)) {
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213 | e8af50a3 | bellard | /* only set write access if already dirty... otherwise wait
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214 | e8af50a3 | bellard | for dirty access */
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215 | 227671c9 | bellard | *prot &= ~PAGE_WRITE; |
216 | e8af50a3 | bellard | } |
217 | e8af50a3 | bellard | |
218 | e8af50a3 | bellard | /* Even if large ptes, we map only one 4KB page in the cache to
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219 | e8af50a3 | bellard | avoid filling it too fast */
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220 | 5dcb6b91 | blueswir1 | *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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221 | 6f7e9aec | bellard | return error_code;
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222 | e80cfcfc | bellard | } |
223 | e80cfcfc | bellard | |
224 | e80cfcfc | bellard | /* Perform address translation */
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225 | af7bf89b | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
226 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
227 | e80cfcfc | bellard | { |
228 | af7bf89b | bellard | target_phys_addr_t paddr; |
229 | 5dcb6b91 | blueswir1 | target_ulong vaddr; |
230 | e80cfcfc | bellard | int error_code = 0, prot, ret = 0, access_index; |
231 | e8af50a3 | bellard | |
232 | 77f193da | blueswir1 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
233 | 77f193da | blueswir1 | address, rw, mmu_idx); |
234 | e80cfcfc | bellard | if (error_code == 0) { |
235 | 0f8a249a | blueswir1 | vaddr = address & TARGET_PAGE_MASK; |
236 | 0f8a249a | blueswir1 | paddr &= TARGET_PAGE_MASK; |
237 | 9e61bde5 | bellard | #ifdef DEBUG_MMU
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238 | 0f8a249a | blueswir1 | printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
239 | 5dcb6b91 | blueswir1 | TARGET_FMT_lx "\n", address, paddr, vaddr);
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240 | 9e61bde5 | bellard | #endif
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241 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
242 | 0f8a249a | blueswir1 | return ret;
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243 | e80cfcfc | bellard | } |
244 | e8af50a3 | bellard | |
245 | e8af50a3 | bellard | if (env->mmuregs[3]) /* Fault status register */ |
246 | 0f8a249a | blueswir1 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
247 | 7483750d | bellard | env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
248 | e8af50a3 | bellard | env->mmuregs[4] = address; /* Fault address register */ |
249 | e8af50a3 | bellard | |
250 | 878d3096 | bellard | if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
251 | 6f7e9aec | bellard | // No fault mode: if a mapping is available, just override
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252 | 6f7e9aec | bellard | // permissions. If no mapping is available, redirect accesses to
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253 | 6f7e9aec | bellard | // neverland. Fake/overridden mappings will be flushed when
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254 | 6f7e9aec | bellard | // switching to normal mode.
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255 | 0f8a249a | blueswir1 | vaddr = address & TARGET_PAGE_MASK; |
256 | 227671c9 | bellard | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
257 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
258 | 0f8a249a | blueswir1 | return ret;
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259 | 7483750d | bellard | } else {
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260 | 7483750d | bellard | if (rw & 2) |
261 | 7483750d | bellard | env->exception_index = TT_TFAULT; |
262 | 7483750d | bellard | else
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263 | 7483750d | bellard | env->exception_index = TT_DFAULT; |
264 | 7483750d | bellard | return 1; |
265 | 878d3096 | bellard | } |
266 | e8af50a3 | bellard | } |
267 | 24741ef3 | bellard | |
268 | 24741ef3 | bellard | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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269 | 24741ef3 | bellard | { |
270 | 24741ef3 | bellard | target_phys_addr_t pde_ptr; |
271 | 24741ef3 | bellard | uint32_t pde; |
272 | 24741ef3 | bellard | |
273 | 24741ef3 | bellard | /* Context base + context number */
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274 | 5dcb6b91 | blueswir1 | pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
275 | 5dcb6b91 | blueswir1 | (env->mmuregs[2] << 2); |
276 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
277 | 24741ef3 | bellard | |
278 | 24741ef3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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279 | 24741ef3 | bellard | default:
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280 | 24741ef3 | bellard | case 0: /* Invalid */ |
281 | 24741ef3 | bellard | case 2: /* PTE, maybe should not happen? */ |
282 | 24741ef3 | bellard | case 3: /* Reserved */ |
283 | 0f8a249a | blueswir1 | return 0; |
284 | 24741ef3 | bellard | case 1: /* L1 PDE */ |
285 | 0f8a249a | blueswir1 | if (mmulev == 3) |
286 | 0f8a249a | blueswir1 | return pde;
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287 | 0f8a249a | blueswir1 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
288 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
289 | 24741ef3 | bellard | |
290 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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291 | 0f8a249a | blueswir1 | default:
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292 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
293 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
294 | 0f8a249a | blueswir1 | return 0; |
295 | 0f8a249a | blueswir1 | case 2: /* L1 PTE */ |
296 | 0f8a249a | blueswir1 | return pde;
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297 | 0f8a249a | blueswir1 | case 1: /* L2 PDE */ |
298 | 0f8a249a | blueswir1 | if (mmulev == 2) |
299 | 0f8a249a | blueswir1 | return pde;
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300 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
301 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
302 | 24741ef3 | bellard | |
303 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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304 | 0f8a249a | blueswir1 | default:
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305 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
306 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
307 | 0f8a249a | blueswir1 | return 0; |
308 | 0f8a249a | blueswir1 | case 2: /* L2 PTE */ |
309 | 0f8a249a | blueswir1 | return pde;
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310 | 0f8a249a | blueswir1 | case 1: /* L3 PDE */ |
311 | 0f8a249a | blueswir1 | if (mmulev == 1) |
312 | 0f8a249a | blueswir1 | return pde;
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313 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
314 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
315 | 24741ef3 | bellard | |
316 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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317 | 0f8a249a | blueswir1 | default:
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318 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
319 | 0f8a249a | blueswir1 | case 1: /* PDE, should not happen */ |
320 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
321 | 0f8a249a | blueswir1 | return 0; |
322 | 0f8a249a | blueswir1 | case 2: /* L3 PTE */ |
323 | 0f8a249a | blueswir1 | return pde;
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324 | 0f8a249a | blueswir1 | } |
325 | 0f8a249a | blueswir1 | } |
326 | 0f8a249a | blueswir1 | } |
327 | 24741ef3 | bellard | } |
328 | 24741ef3 | bellard | return 0; |
329 | 24741ef3 | bellard | } |
330 | 24741ef3 | bellard | |
331 | 24741ef3 | bellard | #ifdef DEBUG_MMU
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332 | 24741ef3 | bellard | void dump_mmu(CPUState *env)
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333 | 24741ef3 | bellard | { |
334 | 5dcb6b91 | blueswir1 | target_ulong va, va1, va2; |
335 | 5dcb6b91 | blueswir1 | unsigned int n, m, o; |
336 | 5dcb6b91 | blueswir1 | target_phys_addr_t pde_ptr, pa; |
337 | 24741ef3 | bellard | uint32_t pde; |
338 | 24741ef3 | bellard | |
339 | 24741ef3 | bellard | printf("MMU dump:\n");
|
340 | 24741ef3 | bellard | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
341 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
342 | 5dcb6b91 | blueswir1 | printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
343 | 5dcb6b91 | blueswir1 | (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
344 | 24741ef3 | bellard | for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
345 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va, 2);
|
346 | 0f8a249a | blueswir1 | if (pde) {
|
347 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va); |
348 | 0f8a249a | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
349 | 5dcb6b91 | blueswir1 | " PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
350 | 0f8a249a | blueswir1 | for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
351 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va1, 1);
|
352 | 0f8a249a | blueswir1 | if (pde) {
|
353 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va1); |
354 | 0f8a249a | blueswir1 | printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
355 | 5dcb6b91 | blueswir1 | " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
356 | 0f8a249a | blueswir1 | for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
357 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va2, 0);
|
358 | 0f8a249a | blueswir1 | if (pde) {
|
359 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va2); |
360 | 0f8a249a | blueswir1 | printf(" VA: " TARGET_FMT_lx ", PA: " |
361 | 5dcb6b91 | blueswir1 | TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
362 | 5dcb6b91 | blueswir1 | va2, pa, pde); |
363 | 0f8a249a | blueswir1 | } |
364 | 0f8a249a | blueswir1 | } |
365 | 0f8a249a | blueswir1 | } |
366 | 0f8a249a | blueswir1 | } |
367 | 0f8a249a | blueswir1 | } |
368 | 24741ef3 | bellard | } |
369 | 24741ef3 | bellard | printf("MMU dump ends\n");
|
370 | 24741ef3 | bellard | } |
371 | 24741ef3 | bellard | #endif /* DEBUG_MMU */ |
372 | 24741ef3 | bellard | |
373 | 24741ef3 | bellard | #else /* !TARGET_SPARC64 */ |
374 | 83469015 | bellard | /*
|
375 | 83469015 | bellard | * UltraSparc IIi I/DMMUs
|
376 | 83469015 | bellard | */
|
377 | 77f193da | blueswir1 | static int get_physical_address_data(CPUState *env, |
378 | 77f193da | blueswir1 | target_phys_addr_t *physical, int *prot,
|
379 | 22548760 | blueswir1 | target_ulong address, int rw, int is_user) |
380 | 3475187d | bellard | { |
381 | 3475187d | bellard | target_ulong mask; |
382 | 3475187d | bellard | unsigned int i; |
383 | 3475187d | bellard | |
384 | 3475187d | bellard | if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
385 | 0f8a249a | blueswir1 | *physical = address; |
386 | 0f8a249a | blueswir1 | *prot = PAGE_READ | PAGE_WRITE; |
387 | 3475187d | bellard | return 0; |
388 | 3475187d | bellard | } |
389 | 3475187d | bellard | |
390 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
391 | 0f8a249a | blueswir1 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
392 | 0f8a249a | blueswir1 | default:
|
393 | 0f8a249a | blueswir1 | case 0x0: // 8k |
394 | 0f8a249a | blueswir1 | mask = 0xffffffffffffe000ULL;
|
395 | 0f8a249a | blueswir1 | break;
|
396 | 0f8a249a | blueswir1 | case 0x1: // 64k |
397 | 0f8a249a | blueswir1 | mask = 0xffffffffffff0000ULL;
|
398 | 0f8a249a | blueswir1 | break;
|
399 | 0f8a249a | blueswir1 | case 0x2: // 512k |
400 | 0f8a249a | blueswir1 | mask = 0xfffffffffff80000ULL;
|
401 | 0f8a249a | blueswir1 | break;
|
402 | 0f8a249a | blueswir1 | case 0x3: // 4M |
403 | 0f8a249a | blueswir1 | mask = 0xffffffffffc00000ULL;
|
404 | 0f8a249a | blueswir1 | break;
|
405 | 0f8a249a | blueswir1 | } |
406 | 0f8a249a | blueswir1 | // ctx match, vaddr match?
|
407 | 0f8a249a | blueswir1 | if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
408 | 0f8a249a | blueswir1 | (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
409 | 0f8a249a | blueswir1 | // valid, access ok?
|
410 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || |
411 | 0f8a249a | blueswir1 | ((env->dtlb_tte[i] & 0x4) && is_user) ||
|
412 | 0f8a249a | blueswir1 | (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
413 | 0f8a249a | blueswir1 | if (env->dmmuregs[3]) /* Fault status register */ |
414 | 77f193da | blueswir1 | env->dmmuregs[3] = 2; /* overflow (not read before |
415 | 77f193da | blueswir1 | another fault) */
|
416 | 0f8a249a | blueswir1 | env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
417 | 0f8a249a | blueswir1 | env->dmmuregs[4] = address; /* Fault address register */ |
418 | 0f8a249a | blueswir1 | env->exception_index = TT_DFAULT; |
419 | 83469015 | bellard | #ifdef DEBUG_MMU
|
420 | 0f8a249a | blueswir1 | printf("DFAULT at 0x%" PRIx64 "\n", address); |
421 | 83469015 | bellard | #endif
|
422 | 0f8a249a | blueswir1 | return 1; |
423 | 0f8a249a | blueswir1 | } |
424 | 77f193da | blueswir1 | *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
|
425 | 77f193da | blueswir1 | (address & ~mask & 0x1fffffff000ULL);
|
426 | 0f8a249a | blueswir1 | *prot = PAGE_READ; |
427 | 0f8a249a | blueswir1 | if (env->dtlb_tte[i] & 0x2) |
428 | 0f8a249a | blueswir1 | *prot |= PAGE_WRITE; |
429 | 0f8a249a | blueswir1 | return 0; |
430 | 0f8a249a | blueswir1 | } |
431 | 3475187d | bellard | } |
432 | 83469015 | bellard | #ifdef DEBUG_MMU
|
433 | 26a76461 | bellard | printf("DMISS at 0x%" PRIx64 "\n", address); |
434 | 83469015 | bellard | #endif
|
435 | f617a9a6 | blueswir1 | env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff); |
436 | 83469015 | bellard | env->exception_index = TT_DMISS; |
437 | 3475187d | bellard | return 1; |
438 | 3475187d | bellard | } |
439 | 3475187d | bellard | |
440 | 77f193da | blueswir1 | static int get_physical_address_code(CPUState *env, |
441 | 77f193da | blueswir1 | target_phys_addr_t *physical, int *prot,
|
442 | 22548760 | blueswir1 | target_ulong address, int is_user)
|
443 | 3475187d | bellard | { |
444 | 3475187d | bellard | target_ulong mask; |
445 | 3475187d | bellard | unsigned int i; |
446 | 3475187d | bellard | |
447 | 3475187d | bellard | if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
448 | 0f8a249a | blueswir1 | *physical = address; |
449 | 0f8a249a | blueswir1 | *prot = PAGE_EXEC; |
450 | 3475187d | bellard | return 0; |
451 | 3475187d | bellard | } |
452 | 83469015 | bellard | |
453 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
454 | 0f8a249a | blueswir1 | switch ((env->itlb_tte[i] >> 61) & 3) { |
455 | 0f8a249a | blueswir1 | default:
|
456 | 0f8a249a | blueswir1 | case 0x0: // 8k |
457 | 0f8a249a | blueswir1 | mask = 0xffffffffffffe000ULL;
|
458 | 0f8a249a | blueswir1 | break;
|
459 | 0f8a249a | blueswir1 | case 0x1: // 64k |
460 | 0f8a249a | blueswir1 | mask = 0xffffffffffff0000ULL;
|
461 | 0f8a249a | blueswir1 | break;
|
462 | 0f8a249a | blueswir1 | case 0x2: // 512k |
463 | 0f8a249a | blueswir1 | mask = 0xfffffffffff80000ULL;
|
464 | 0f8a249a | blueswir1 | break;
|
465 | 0f8a249a | blueswir1 | case 0x3: // 4M |
466 | 0f8a249a | blueswir1 | mask = 0xffffffffffc00000ULL;
|
467 | 0f8a249a | blueswir1 | break;
|
468 | 0f8a249a | blueswir1 | } |
469 | 0f8a249a | blueswir1 | // ctx match, vaddr match?
|
470 | 0f8a249a | blueswir1 | if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
471 | 0f8a249a | blueswir1 | (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
472 | 0f8a249a | blueswir1 | // valid, access ok?
|
473 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
474 | 0f8a249a | blueswir1 | ((env->itlb_tte[i] & 0x4) && is_user)) {
|
475 | 0f8a249a | blueswir1 | if (env->immuregs[3]) /* Fault status register */ |
476 | 77f193da | blueswir1 | env->immuregs[3] = 2; /* overflow (not read before |
477 | 77f193da | blueswir1 | another fault) */
|
478 | 0f8a249a | blueswir1 | env->immuregs[3] |= (is_user << 3) | 1; |
479 | 0f8a249a | blueswir1 | env->exception_index = TT_TFAULT; |
480 | 83469015 | bellard | #ifdef DEBUG_MMU
|
481 | 0f8a249a | blueswir1 | printf("TFAULT at 0x%" PRIx64 "\n", address); |
482 | 83469015 | bellard | #endif
|
483 | 0f8a249a | blueswir1 | return 1; |
484 | 0f8a249a | blueswir1 | } |
485 | 77f193da | blueswir1 | *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
|
486 | 77f193da | blueswir1 | (address & ~mask & 0x1fffffff000ULL);
|
487 | 0f8a249a | blueswir1 | *prot = PAGE_EXEC; |
488 | 0f8a249a | blueswir1 | return 0; |
489 | 0f8a249a | blueswir1 | } |
490 | 3475187d | bellard | } |
491 | 83469015 | bellard | #ifdef DEBUG_MMU
|
492 | 26a76461 | bellard | printf("TMISS at 0x%" PRIx64 "\n", address); |
493 | 83469015 | bellard | #endif
|
494 | f617a9a6 | blueswir1 | env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff); |
495 | 83469015 | bellard | env->exception_index = TT_TMISS; |
496 | 3475187d | bellard | return 1; |
497 | 3475187d | bellard | } |
498 | 3475187d | bellard | |
499 | c48fcb47 | blueswir1 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
500 | c48fcb47 | blueswir1 | int *prot, int *access_index, |
501 | c48fcb47 | blueswir1 | target_ulong address, int rw, int mmu_idx) |
502 | 3475187d | bellard | { |
503 | 6ebbf390 | j_mayer | int is_user = mmu_idx == MMU_USER_IDX;
|
504 | 6ebbf390 | j_mayer | |
505 | 3475187d | bellard | if (rw == 2) |
506 | 22548760 | blueswir1 | return get_physical_address_code(env, physical, prot, address,
|
507 | 22548760 | blueswir1 | is_user); |
508 | 3475187d | bellard | else
|
509 | 22548760 | blueswir1 | return get_physical_address_data(env, physical, prot, address, rw,
|
510 | 22548760 | blueswir1 | is_user); |
511 | 3475187d | bellard | } |
512 | 3475187d | bellard | |
513 | 3475187d | bellard | /* Perform address translation */
|
514 | 3475187d | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
515 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
516 | 3475187d | bellard | { |
517 | 83469015 | bellard | target_ulong virt_addr, vaddr; |
518 | 3475187d | bellard | target_phys_addr_t paddr; |
519 | 3475187d | bellard | int error_code = 0, prot, ret = 0, access_index; |
520 | 3475187d | bellard | |
521 | 77f193da | blueswir1 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
522 | 77f193da | blueswir1 | address, rw, mmu_idx); |
523 | 3475187d | bellard | if (error_code == 0) { |
524 | 0f8a249a | blueswir1 | virt_addr = address & TARGET_PAGE_MASK; |
525 | 77f193da | blueswir1 | vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & |
526 | 77f193da | blueswir1 | (TARGET_PAGE_SIZE - 1));
|
527 | 83469015 | bellard | #ifdef DEBUG_MMU
|
528 | 77f193da | blueswir1 | printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 |
529 | 77f193da | blueswir1 | "\n", address, paddr, vaddr);
|
530 | 83469015 | bellard | #endif
|
531 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
532 | 0f8a249a | blueswir1 | return ret;
|
533 | 3475187d | bellard | } |
534 | 3475187d | bellard | // XXX
|
535 | 3475187d | bellard | return 1; |
536 | 3475187d | bellard | } |
537 | 3475187d | bellard | |
538 | 83469015 | bellard | #ifdef DEBUG_MMU
|
539 | 83469015 | bellard | void dump_mmu(CPUState *env)
|
540 | 83469015 | bellard | { |
541 | 83469015 | bellard | unsigned int i; |
542 | 83469015 | bellard | const char *mask; |
543 | 83469015 | bellard | |
544 | 77f193da | blueswir1 | printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", |
545 | 77f193da | blueswir1 | env->dmmuregs[1], env->dmmuregs[2]); |
546 | 83469015 | bellard | if ((env->lsu & DMMU_E) == 0) { |
547 | 0f8a249a | blueswir1 | printf("DMMU disabled\n");
|
548 | 83469015 | bellard | } else {
|
549 | 0f8a249a | blueswir1 | printf("DMMU dump:\n");
|
550 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
551 | 0f8a249a | blueswir1 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
552 | 0f8a249a | blueswir1 | default:
|
553 | 0f8a249a | blueswir1 | case 0x0: |
554 | 0f8a249a | blueswir1 | mask = " 8k";
|
555 | 0f8a249a | blueswir1 | break;
|
556 | 0f8a249a | blueswir1 | case 0x1: |
557 | 0f8a249a | blueswir1 | mask = " 64k";
|
558 | 0f8a249a | blueswir1 | break;
|
559 | 0f8a249a | blueswir1 | case 0x2: |
560 | 0f8a249a | blueswir1 | mask = "512k";
|
561 | 0f8a249a | blueswir1 | break;
|
562 | 0f8a249a | blueswir1 | case 0x3: |
563 | 0f8a249a | blueswir1 | mask = " 4M";
|
564 | 0f8a249a | blueswir1 | break;
|
565 | 0f8a249a | blueswir1 | } |
566 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
567 | 77f193da | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
568 | 77f193da | blueswir1 | ", %s, %s, %s, %s, ctx %" PRId64 "\n", |
569 | 0f8a249a | blueswir1 | env->dtlb_tag[i] & ~0x1fffULL,
|
570 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
571 | 0f8a249a | blueswir1 | mask, |
572 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x4? "priv": "user", |
573 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x2? "RW": "RO", |
574 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
575 | 0f8a249a | blueswir1 | env->dtlb_tag[i] & 0x1fffULL);
|
576 | 0f8a249a | blueswir1 | } |
577 | 0f8a249a | blueswir1 | } |
578 | 83469015 | bellard | } |
579 | 83469015 | bellard | if ((env->lsu & IMMU_E) == 0) { |
580 | 0f8a249a | blueswir1 | printf("IMMU disabled\n");
|
581 | 83469015 | bellard | } else {
|
582 | 0f8a249a | blueswir1 | printf("IMMU dump:\n");
|
583 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
584 | 0f8a249a | blueswir1 | switch ((env->itlb_tte[i] >> 61) & 3) { |
585 | 0f8a249a | blueswir1 | default:
|
586 | 0f8a249a | blueswir1 | case 0x0: |
587 | 0f8a249a | blueswir1 | mask = " 8k";
|
588 | 0f8a249a | blueswir1 | break;
|
589 | 0f8a249a | blueswir1 | case 0x1: |
590 | 0f8a249a | blueswir1 | mask = " 64k";
|
591 | 0f8a249a | blueswir1 | break;
|
592 | 0f8a249a | blueswir1 | case 0x2: |
593 | 0f8a249a | blueswir1 | mask = "512k";
|
594 | 0f8a249a | blueswir1 | break;
|
595 | 0f8a249a | blueswir1 | case 0x3: |
596 | 0f8a249a | blueswir1 | mask = " 4M";
|
597 | 0f8a249a | blueswir1 | break;
|
598 | 0f8a249a | blueswir1 | } |
599 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
600 | 77f193da | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
601 | 77f193da | blueswir1 | ", %s, %s, %s, ctx %" PRId64 "\n", |
602 | 0f8a249a | blueswir1 | env->itlb_tag[i] & ~0x1fffULL,
|
603 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x1ffffffe000ULL,
|
604 | 0f8a249a | blueswir1 | mask, |
605 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x4? "priv": "user", |
606 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x40? "locked": "unlocked", |
607 | 0f8a249a | blueswir1 | env->itlb_tag[i] & 0x1fffULL);
|
608 | 0f8a249a | blueswir1 | } |
609 | 0f8a249a | blueswir1 | } |
610 | 83469015 | bellard | } |
611 | 83469015 | bellard | } |
612 | 24741ef3 | bellard | #endif /* DEBUG_MMU */ |
613 | 24741ef3 | bellard | |
614 | 24741ef3 | bellard | #endif /* TARGET_SPARC64 */ |
615 | 24741ef3 | bellard | #endif /* !CONFIG_USER_ONLY */ |
616 | 24741ef3 | bellard | |
617 | c48fcb47 | blueswir1 | |
618 | c48fcb47 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
619 | c48fcb47 | blueswir1 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
620 | c48fcb47 | blueswir1 | { |
621 | c48fcb47 | blueswir1 | return addr;
|
622 | c48fcb47 | blueswir1 | } |
623 | c48fcb47 | blueswir1 | |
624 | c48fcb47 | blueswir1 | #else
|
625 | c48fcb47 | blueswir1 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
626 | c48fcb47 | blueswir1 | { |
627 | c48fcb47 | blueswir1 | target_phys_addr_t phys_addr; |
628 | c48fcb47 | blueswir1 | int prot, access_index;
|
629 | c48fcb47 | blueswir1 | |
630 | c48fcb47 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
631 | c48fcb47 | blueswir1 | MMU_KERNEL_IDX) != 0)
|
632 | c48fcb47 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
633 | c48fcb47 | blueswir1 | 0, MMU_KERNEL_IDX) != 0) |
634 | c48fcb47 | blueswir1 | return -1; |
635 | c48fcb47 | blueswir1 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
636 | c48fcb47 | blueswir1 | return -1; |
637 | c48fcb47 | blueswir1 | return phys_addr;
|
638 | c48fcb47 | blueswir1 | } |
639 | c48fcb47 | blueswir1 | #endif
|
640 | c48fcb47 | blueswir1 | |
641 | c48fcb47 | blueswir1 | void cpu_reset(CPUSPARCState *env)
|
642 | c48fcb47 | blueswir1 | { |
643 | c48fcb47 | blueswir1 | tlb_flush(env, 1);
|
644 | c48fcb47 | blueswir1 | env->cwp = 0;
|
645 | c48fcb47 | blueswir1 | env->wim = 1;
|
646 | c48fcb47 | blueswir1 | env->regwptr = env->regbase + (env->cwp * 16);
|
647 | c48fcb47 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
648 | c48fcb47 | blueswir1 | env->user_mode_only = 1;
|
649 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
650 | 1a14026e | blueswir1 | env->cleanwin = env->nwindows - 2;
|
651 | 1a14026e | blueswir1 | env->cansave = env->nwindows - 2;
|
652 | c48fcb47 | blueswir1 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
653 | c48fcb47 | blueswir1 | env->asi = 0x82; // Primary no-fault |
654 | c48fcb47 | blueswir1 | #endif
|
655 | c48fcb47 | blueswir1 | #else
|
656 | c48fcb47 | blueswir1 | env->psret = 0;
|
657 | c48fcb47 | blueswir1 | env->psrs = 1;
|
658 | c48fcb47 | blueswir1 | env->psrps = 1;
|
659 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
660 | c48fcb47 | blueswir1 | env->pstate = PS_PRIV; |
661 | c48fcb47 | blueswir1 | env->hpstate = HS_PRIV; |
662 | 8eba209e | blueswir1 | env->pc = 0x1fff0000020ULL; // XXX should be different for system_reset |
663 | c19148bd | blueswir1 | env->tsptr = &env->ts[env->tl & MAXTL_MASK]; |
664 | c48fcb47 | blueswir1 | #else
|
665 | c48fcb47 | blueswir1 | env->pc = 0;
|
666 | c48fcb47 | blueswir1 | env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
667 | 5578ceab | blueswir1 | env->mmuregs[0] |= env->def->mmu_bm;
|
668 | c48fcb47 | blueswir1 | #endif
|
669 | c48fcb47 | blueswir1 | env->npc = env->pc + 4;
|
670 | c48fcb47 | blueswir1 | #endif
|
671 | c48fcb47 | blueswir1 | } |
672 | c48fcb47 | blueswir1 | |
673 | 64a88d5d | blueswir1 | static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
674 | c48fcb47 | blueswir1 | { |
675 | 64a88d5d | blueswir1 | sparc_def_t def1, *def = &def1; |
676 | c48fcb47 | blueswir1 | |
677 | 64a88d5d | blueswir1 | if (cpu_sparc_find_by_name(def, cpu_model) < 0) |
678 | 64a88d5d | blueswir1 | return -1; |
679 | c48fcb47 | blueswir1 | |
680 | 5578ceab | blueswir1 | env->def = qemu_mallocz(sizeof(*def));
|
681 | 5578ceab | blueswir1 | memcpy(env->def, def, sizeof(*def));
|
682 | 5578ceab | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
683 | 5578ceab | blueswir1 | if ((env->def->features & CPU_FEATURE_FLOAT))
|
684 | 5578ceab | blueswir1 | env->def->features |= CPU_FEATURE_FLOAT128; |
685 | 5578ceab | blueswir1 | #endif
|
686 | c48fcb47 | blueswir1 | env->cpu_model_str = cpu_model; |
687 | c48fcb47 | blueswir1 | env->version = def->iu_version; |
688 | c48fcb47 | blueswir1 | env->fsr = def->fpu_version; |
689 | 1a14026e | blueswir1 | env->nwindows = def->nwindows; |
690 | c48fcb47 | blueswir1 | #if !defined(TARGET_SPARC64)
|
691 | c48fcb47 | blueswir1 | env->mmuregs[0] |= def->mmu_version;
|
692 | c48fcb47 | blueswir1 | cpu_sparc_set_id(env, 0);
|
693 | 1a14026e | blueswir1 | #else
|
694 | fb79ceb9 | blueswir1 | env->mmu_version = def->mmu_version; |
695 | c19148bd | blueswir1 | env->maxtl = def->maxtl; |
696 | c19148bd | blueswir1 | env->version |= def->maxtl << 8;
|
697 | 1a14026e | blueswir1 | env->version |= def->nwindows - 1;
|
698 | c48fcb47 | blueswir1 | #endif
|
699 | 64a88d5d | blueswir1 | return 0; |
700 | 64a88d5d | blueswir1 | } |
701 | 64a88d5d | blueswir1 | |
702 | 64a88d5d | blueswir1 | static void cpu_sparc_close(CPUSPARCState *env) |
703 | 64a88d5d | blueswir1 | { |
704 | 5578ceab | blueswir1 | free(env->def); |
705 | 64a88d5d | blueswir1 | free(env); |
706 | 64a88d5d | blueswir1 | } |
707 | 64a88d5d | blueswir1 | |
708 | 64a88d5d | blueswir1 | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
709 | 64a88d5d | blueswir1 | { |
710 | 64a88d5d | blueswir1 | CPUSPARCState *env; |
711 | 64a88d5d | blueswir1 | |
712 | 64a88d5d | blueswir1 | env = qemu_mallocz(sizeof(CPUSPARCState));
|
713 | 64a88d5d | blueswir1 | if (!env)
|
714 | 64a88d5d | blueswir1 | return NULL; |
715 | 64a88d5d | blueswir1 | cpu_exec_init(env); |
716 | c48fcb47 | blueswir1 | |
717 | c48fcb47 | blueswir1 | gen_intermediate_code_init(env); |
718 | c48fcb47 | blueswir1 | |
719 | 64a88d5d | blueswir1 | if (cpu_sparc_register(env, cpu_model) < 0) { |
720 | 64a88d5d | blueswir1 | cpu_sparc_close(env); |
721 | 64a88d5d | blueswir1 | return NULL; |
722 | 64a88d5d | blueswir1 | } |
723 | c48fcb47 | blueswir1 | cpu_reset(env); |
724 | c48fcb47 | blueswir1 | |
725 | c48fcb47 | blueswir1 | return env;
|
726 | c48fcb47 | blueswir1 | } |
727 | c48fcb47 | blueswir1 | |
728 | c48fcb47 | blueswir1 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
729 | c48fcb47 | blueswir1 | { |
730 | c48fcb47 | blueswir1 | #if !defined(TARGET_SPARC64)
|
731 | c48fcb47 | blueswir1 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
732 | c48fcb47 | blueswir1 | #endif
|
733 | c48fcb47 | blueswir1 | } |
734 | c48fcb47 | blueswir1 | |
735 | c48fcb47 | blueswir1 | static const sparc_def_t sparc_defs[] = { |
736 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
737 | c48fcb47 | blueswir1 | { |
738 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64",
|
739 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
740 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
741 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
742 | 1a14026e | blueswir1 | .nwindows = 4,
|
743 | c19148bd | blueswir1 | .maxtl = 4,
|
744 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
745 | c48fcb47 | blueswir1 | }, |
746 | c48fcb47 | blueswir1 | { |
747 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 III",
|
748 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
749 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
750 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
751 | 1a14026e | blueswir1 | .nwindows = 5,
|
752 | c19148bd | blueswir1 | .maxtl = 4,
|
753 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
754 | c48fcb47 | blueswir1 | }, |
755 | c48fcb47 | blueswir1 | { |
756 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 IV",
|
757 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
758 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
759 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
760 | 1a14026e | blueswir1 | .nwindows = 8,
|
761 | c19148bd | blueswir1 | .maxtl = 5,
|
762 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
763 | c48fcb47 | blueswir1 | }, |
764 | c48fcb47 | blueswir1 | { |
765 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 V",
|
766 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
767 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
768 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
769 | 1a14026e | blueswir1 | .nwindows = 8,
|
770 | c19148bd | blueswir1 | .maxtl = 5,
|
771 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
772 | c48fcb47 | blueswir1 | }, |
773 | c48fcb47 | blueswir1 | { |
774 | c48fcb47 | blueswir1 | .name = "TI UltraSparc I",
|
775 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
776 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
777 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
778 | 1a14026e | blueswir1 | .nwindows = 8,
|
779 | c19148bd | blueswir1 | .maxtl = 5,
|
780 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
781 | c48fcb47 | blueswir1 | }, |
782 | c48fcb47 | blueswir1 | { |
783 | c48fcb47 | blueswir1 | .name = "TI UltraSparc II",
|
784 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
785 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
786 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
787 | 1a14026e | blueswir1 | .nwindows = 8,
|
788 | c19148bd | blueswir1 | .maxtl = 5,
|
789 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
790 | c48fcb47 | blueswir1 | }, |
791 | c48fcb47 | blueswir1 | { |
792 | c48fcb47 | blueswir1 | .name = "TI UltraSparc IIi",
|
793 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
794 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
795 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
796 | 1a14026e | blueswir1 | .nwindows = 8,
|
797 | c19148bd | blueswir1 | .maxtl = 5,
|
798 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
799 | c48fcb47 | blueswir1 | }, |
800 | c48fcb47 | blueswir1 | { |
801 | c48fcb47 | blueswir1 | .name = "TI UltraSparc IIe",
|
802 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
803 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
804 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
805 | 1a14026e | blueswir1 | .nwindows = 8,
|
806 | c19148bd | blueswir1 | .maxtl = 5,
|
807 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
808 | c48fcb47 | blueswir1 | }, |
809 | c48fcb47 | blueswir1 | { |
810 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc III",
|
811 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
812 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
813 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
814 | 1a14026e | blueswir1 | .nwindows = 8,
|
815 | c19148bd | blueswir1 | .maxtl = 5,
|
816 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
817 | c48fcb47 | blueswir1 | }, |
818 | c48fcb47 | blueswir1 | { |
819 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc III Cu",
|
820 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
821 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
822 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_3, |
823 | 1a14026e | blueswir1 | .nwindows = 8,
|
824 | c19148bd | blueswir1 | .maxtl = 5,
|
825 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
826 | c48fcb47 | blueswir1 | }, |
827 | c48fcb47 | blueswir1 | { |
828 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IIIi",
|
829 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
830 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
831 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
832 | 1a14026e | blueswir1 | .nwindows = 8,
|
833 | c19148bd | blueswir1 | .maxtl = 5,
|
834 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
835 | c48fcb47 | blueswir1 | }, |
836 | c48fcb47 | blueswir1 | { |
837 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IV",
|
838 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
839 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
840 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_4, |
841 | 1a14026e | blueswir1 | .nwindows = 8,
|
842 | c19148bd | blueswir1 | .maxtl = 5,
|
843 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
844 | c48fcb47 | blueswir1 | }, |
845 | c48fcb47 | blueswir1 | { |
846 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IV+",
|
847 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
848 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
849 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
850 | 1a14026e | blueswir1 | .nwindows = 8,
|
851 | c19148bd | blueswir1 | .maxtl = 5,
|
852 | fb79ceb9 | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
853 | c48fcb47 | blueswir1 | }, |
854 | c48fcb47 | blueswir1 | { |
855 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IIIi+",
|
856 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
857 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
858 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_3, |
859 | 1a14026e | blueswir1 | .nwindows = 8,
|
860 | c19148bd | blueswir1 | .maxtl = 5,
|
861 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
862 | c48fcb47 | blueswir1 | }, |
863 | c48fcb47 | blueswir1 | { |
864 | c7ba218d | blueswir1 | .name = "Sun UltraSparc T1",
|
865 | c7ba218d | blueswir1 | // defined in sparc_ifu_fdp.v and ctu.h
|
866 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
867 | c7ba218d | blueswir1 | .fpu_version = 0x00000000,
|
868 | c7ba218d | blueswir1 | .mmu_version = mmu_sun4v, |
869 | c7ba218d | blueswir1 | .nwindows = 8,
|
870 | c19148bd | blueswir1 | .maxtl = 6,
|
871 | c7ba218d | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
872 | c7ba218d | blueswir1 | | CPU_FEATURE_GL, |
873 | c7ba218d | blueswir1 | }, |
874 | c7ba218d | blueswir1 | { |
875 | c7ba218d | blueswir1 | .name = "Sun UltraSparc T2",
|
876 | c7ba218d | blueswir1 | // defined in tlu_asi_ctl.v and n2_revid_cust.v
|
877 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
878 | c7ba218d | blueswir1 | .fpu_version = 0x00000000,
|
879 | c7ba218d | blueswir1 | .mmu_version = mmu_sun4v, |
880 | c7ba218d | blueswir1 | .nwindows = 8,
|
881 | c19148bd | blueswir1 | .maxtl = 6,
|
882 | c7ba218d | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
883 | c7ba218d | blueswir1 | | CPU_FEATURE_GL, |
884 | c7ba218d | blueswir1 | }, |
885 | c7ba218d | blueswir1 | { |
886 | c48fcb47 | blueswir1 | .name = "NEC UltraSparc I",
|
887 | c19148bd | blueswir1 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
888 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
889 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
890 | 1a14026e | blueswir1 | .nwindows = 8,
|
891 | c19148bd | blueswir1 | .maxtl = 5,
|
892 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
893 | c48fcb47 | blueswir1 | }, |
894 | c48fcb47 | blueswir1 | #else
|
895 | c48fcb47 | blueswir1 | { |
896 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86900",
|
897 | c48fcb47 | blueswir1 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
898 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
899 | c48fcb47 | blueswir1 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
900 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
901 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
902 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
903 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
904 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
905 | 1a14026e | blueswir1 | .nwindows = 7,
|
906 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD, |
907 | c48fcb47 | blueswir1 | }, |
908 | c48fcb47 | blueswir1 | { |
909 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86904",
|
910 | c48fcb47 | blueswir1 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
911 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
912 | c48fcb47 | blueswir1 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
913 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
914 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
915 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
916 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
917 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
918 | 1a14026e | blueswir1 | .nwindows = 8,
|
919 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
920 | c48fcb47 | blueswir1 | }, |
921 | c48fcb47 | blueswir1 | { |
922 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86907",
|
923 | c48fcb47 | blueswir1 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
924 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
925 | c48fcb47 | blueswir1 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
926 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
927 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
928 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
929 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
930 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
931 | 1a14026e | blueswir1 | .nwindows = 8,
|
932 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
933 | c48fcb47 | blueswir1 | }, |
934 | c48fcb47 | blueswir1 | { |
935 | c48fcb47 | blueswir1 | .name = "LSI L64811",
|
936 | c48fcb47 | blueswir1 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
937 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
938 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
939 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
940 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
941 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
942 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
943 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
944 | 1a14026e | blueswir1 | .nwindows = 8,
|
945 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
946 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
947 | c48fcb47 | blueswir1 | }, |
948 | c48fcb47 | blueswir1 | { |
949 | c48fcb47 | blueswir1 | .name = "Cypress CY7C601",
|
950 | c48fcb47 | blueswir1 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
951 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
952 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
953 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
954 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
955 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
956 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
957 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
958 | 1a14026e | blueswir1 | .nwindows = 8,
|
959 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
960 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
961 | c48fcb47 | blueswir1 | }, |
962 | c48fcb47 | blueswir1 | { |
963 | c48fcb47 | blueswir1 | .name = "Cypress CY7C611",
|
964 | c48fcb47 | blueswir1 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
965 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
966 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
967 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
968 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
969 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
970 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
971 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
972 | 1a14026e | blueswir1 | .nwindows = 8,
|
973 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
974 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
975 | c48fcb47 | blueswir1 | }, |
976 | c48fcb47 | blueswir1 | { |
977 | c48fcb47 | blueswir1 | .name = "TI SuperSparc II",
|
978 | c48fcb47 | blueswir1 | .iu_version = 0x40000000,
|
979 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
980 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
981 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
982 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
983 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
984 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
985 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
986 | 1a14026e | blueswir1 | .nwindows = 8,
|
987 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
988 | c48fcb47 | blueswir1 | }, |
989 | c48fcb47 | blueswir1 | { |
990 | c48fcb47 | blueswir1 | .name = "TI MicroSparc I",
|
991 | c48fcb47 | blueswir1 | .iu_version = 0x41000000,
|
992 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
993 | c48fcb47 | blueswir1 | .mmu_version = 0x41000000,
|
994 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
995 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
996 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
997 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
998 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x0000003f,
|
999 | 1a14026e | blueswir1 | .nwindows = 7,
|
1000 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | |
1001 | e30b4678 | blueswir1 | CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | |
1002 | e30b4678 | blueswir1 | CPU_FEATURE_FMUL, |
1003 | c48fcb47 | blueswir1 | }, |
1004 | c48fcb47 | blueswir1 | { |
1005 | c48fcb47 | blueswir1 | .name = "TI MicroSparc II",
|
1006 | c48fcb47 | blueswir1 | .iu_version = 0x42000000,
|
1007 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
1008 | c48fcb47 | blueswir1 | .mmu_version = 0x02000000,
|
1009 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1010 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
1011 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
1012 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
1013 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
1014 | 1a14026e | blueswir1 | .nwindows = 8,
|
1015 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1016 | c48fcb47 | blueswir1 | }, |
1017 | c48fcb47 | blueswir1 | { |
1018 | c48fcb47 | blueswir1 | .name = "TI MicroSparc IIep",
|
1019 | c48fcb47 | blueswir1 | .iu_version = 0x42000000,
|
1020 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
1021 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
1022 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1023 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
1024 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
1025 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016bff,
|
1026 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
1027 | 1a14026e | blueswir1 | .nwindows = 8,
|
1028 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1029 | c48fcb47 | blueswir1 | }, |
1030 | c48fcb47 | blueswir1 | { |
1031 | b5154bde | blueswir1 | .name = "TI SuperSparc 40", // STP1020NPGA |
1032 | b5154bde | blueswir1 | .iu_version = 0x41000000,
|
1033 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1034 | b5154bde | blueswir1 | .mmu_version = 0x00000000,
|
1035 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1036 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1037 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1038 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1039 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1040 | 1a14026e | blueswir1 | .nwindows = 8,
|
1041 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1042 | b5154bde | blueswir1 | }, |
1043 | b5154bde | blueswir1 | { |
1044 | b5154bde | blueswir1 | .name = "TI SuperSparc 50", // STP1020PGA |
1045 | b5154bde | blueswir1 | .iu_version = 0x40000000,
|
1046 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1047 | b5154bde | blueswir1 | .mmu_version = 0x04000000,
|
1048 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1049 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1050 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1051 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1052 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1053 | 1a14026e | blueswir1 | .nwindows = 8,
|
1054 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1055 | b5154bde | blueswir1 | }, |
1056 | b5154bde | blueswir1 | { |
1057 | c48fcb47 | blueswir1 | .name = "TI SuperSparc 51",
|
1058 | c48fcb47 | blueswir1 | .iu_version = 0x43000000,
|
1059 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1060 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
1061 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
1062 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1063 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1064 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1065 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1066 | 1a14026e | blueswir1 | .nwindows = 8,
|
1067 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1068 | c48fcb47 | blueswir1 | }, |
1069 | c48fcb47 | blueswir1 | { |
1070 | b5154bde | blueswir1 | .name = "TI SuperSparc 60", // STP1020APGA |
1071 | b5154bde | blueswir1 | .iu_version = 0x40000000,
|
1072 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1073 | b5154bde | blueswir1 | .mmu_version = 0x03000000,
|
1074 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1075 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1076 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1077 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1078 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1079 | 1a14026e | blueswir1 | .nwindows = 8,
|
1080 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1081 | b5154bde | blueswir1 | }, |
1082 | b5154bde | blueswir1 | { |
1083 | c48fcb47 | blueswir1 | .name = "TI SuperSparc 61",
|
1084 | c48fcb47 | blueswir1 | .iu_version = 0x44000000,
|
1085 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1086 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
1087 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
1088 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1089 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1090 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1091 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1092 | 1a14026e | blueswir1 | .nwindows = 8,
|
1093 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1094 | c48fcb47 | blueswir1 | }, |
1095 | c48fcb47 | blueswir1 | { |
1096 | c48fcb47 | blueswir1 | .name = "Ross RT625",
|
1097 | c48fcb47 | blueswir1 | .iu_version = 0x1e000000,
|
1098 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, |
1099 | c48fcb47 | blueswir1 | .mmu_version = 0x1e000000,
|
1100 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1101 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1102 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1103 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1104 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1105 | 1a14026e | blueswir1 | .nwindows = 8,
|
1106 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1107 | c48fcb47 | blueswir1 | }, |
1108 | c48fcb47 | blueswir1 | { |
1109 | c48fcb47 | blueswir1 | .name = "Ross RT620",
|
1110 | c48fcb47 | blueswir1 | .iu_version = 0x1f000000,
|
1111 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, |
1112 | c48fcb47 | blueswir1 | .mmu_version = 0x1f000000,
|
1113 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1114 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1115 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1116 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1117 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1118 | 1a14026e | blueswir1 | .nwindows = 8,
|
1119 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1120 | c48fcb47 | blueswir1 | }, |
1121 | c48fcb47 | blueswir1 | { |
1122 | c48fcb47 | blueswir1 | .name = "BIT B5010",
|
1123 | c48fcb47 | blueswir1 | .iu_version = 0x20000000,
|
1124 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
1125 | c48fcb47 | blueswir1 | .mmu_version = 0x20000000,
|
1126 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1127 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1128 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1129 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1130 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1131 | 1a14026e | blueswir1 | .nwindows = 8,
|
1132 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1133 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
1134 | c48fcb47 | blueswir1 | }, |
1135 | c48fcb47 | blueswir1 | { |
1136 | c48fcb47 | blueswir1 | .name = "Matsushita MN10501",
|
1137 | c48fcb47 | blueswir1 | .iu_version = 0x50000000,
|
1138 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1139 | c48fcb47 | blueswir1 | .mmu_version = 0x50000000,
|
1140 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1141 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1142 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1143 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1144 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1145 | 1a14026e | blueswir1 | .nwindows = 8,
|
1146 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT | |
1147 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
1148 | c48fcb47 | blueswir1 | }, |
1149 | c48fcb47 | blueswir1 | { |
1150 | c48fcb47 | blueswir1 | .name = "Weitek W8601",
|
1151 | c48fcb47 | blueswir1 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
1152 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
1153 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
1154 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1155 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1156 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1157 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1158 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1159 | 1a14026e | blueswir1 | .nwindows = 8,
|
1160 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1161 | c48fcb47 | blueswir1 | }, |
1162 | c48fcb47 | blueswir1 | { |
1163 | c48fcb47 | blueswir1 | .name = "LEON2",
|
1164 | c48fcb47 | blueswir1 | .iu_version = 0xf2000000,
|
1165 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1166 | c48fcb47 | blueswir1 | .mmu_version = 0xf2000000,
|
1167 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1168 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1169 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1170 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1171 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1172 | 1a14026e | blueswir1 | .nwindows = 8,
|
1173 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1174 | c48fcb47 | blueswir1 | }, |
1175 | c48fcb47 | blueswir1 | { |
1176 | c48fcb47 | blueswir1 | .name = "LEON3",
|
1177 | c48fcb47 | blueswir1 | .iu_version = 0xf3000000,
|
1178 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1179 | c48fcb47 | blueswir1 | .mmu_version = 0xf3000000,
|
1180 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1181 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1182 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1183 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1184 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1185 | 1a14026e | blueswir1 | .nwindows = 8,
|
1186 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1187 | c48fcb47 | blueswir1 | }, |
1188 | c48fcb47 | blueswir1 | #endif
|
1189 | c48fcb47 | blueswir1 | }; |
1190 | c48fcb47 | blueswir1 | |
1191 | 64a88d5d | blueswir1 | static const char * const feature_name[] = { |
1192 | 64a88d5d | blueswir1 | "float",
|
1193 | 64a88d5d | blueswir1 | "float128",
|
1194 | 64a88d5d | blueswir1 | "swap",
|
1195 | 64a88d5d | blueswir1 | "mul",
|
1196 | 64a88d5d | blueswir1 | "div",
|
1197 | 64a88d5d | blueswir1 | "flush",
|
1198 | 64a88d5d | blueswir1 | "fsqrt",
|
1199 | 64a88d5d | blueswir1 | "fmul",
|
1200 | 64a88d5d | blueswir1 | "vis1",
|
1201 | 64a88d5d | blueswir1 | "vis2",
|
1202 | e30b4678 | blueswir1 | "fsmuld",
|
1203 | fb79ceb9 | blueswir1 | "hypv",
|
1204 | fb79ceb9 | blueswir1 | "cmt",
|
1205 | fb79ceb9 | blueswir1 | "gl",
|
1206 | 64a88d5d | blueswir1 | }; |
1207 | 64a88d5d | blueswir1 | |
1208 | 64a88d5d | blueswir1 | static void print_features(FILE *f, |
1209 | 64a88d5d | blueswir1 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1210 | 64a88d5d | blueswir1 | uint32_t features, const char *prefix) |
1211 | c48fcb47 | blueswir1 | { |
1212 | c48fcb47 | blueswir1 | unsigned int i; |
1213 | c48fcb47 | blueswir1 | |
1214 | 64a88d5d | blueswir1 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1215 | 64a88d5d | blueswir1 | if (feature_name[i] && (features & (1 << i))) { |
1216 | 64a88d5d | blueswir1 | if (prefix)
|
1217 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "%s", prefix);
|
1218 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "%s ", feature_name[i]);
|
1219 | 64a88d5d | blueswir1 | } |
1220 | 64a88d5d | blueswir1 | } |
1221 | 64a88d5d | blueswir1 | |
1222 | 64a88d5d | blueswir1 | static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) |
1223 | 64a88d5d | blueswir1 | { |
1224 | 64a88d5d | blueswir1 | unsigned int i; |
1225 | 64a88d5d | blueswir1 | |
1226 | 64a88d5d | blueswir1 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1227 | 64a88d5d | blueswir1 | if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
|
1228 | 64a88d5d | blueswir1 | *features |= 1 << i;
|
1229 | 64a88d5d | blueswir1 | return;
|
1230 | 64a88d5d | blueswir1 | } |
1231 | 64a88d5d | blueswir1 | fprintf(stderr, "CPU feature %s not found\n", flagname);
|
1232 | 64a88d5d | blueswir1 | } |
1233 | 64a88d5d | blueswir1 | |
1234 | 22548760 | blueswir1 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
1235 | 64a88d5d | blueswir1 | { |
1236 | 64a88d5d | blueswir1 | unsigned int i; |
1237 | 64a88d5d | blueswir1 | const sparc_def_t *def = NULL; |
1238 | 64a88d5d | blueswir1 | char *s = strdup(cpu_model);
|
1239 | 64a88d5d | blueswir1 | char *featurestr, *name = strtok(s, ","); |
1240 | 64a88d5d | blueswir1 | uint32_t plus_features = 0;
|
1241 | 64a88d5d | blueswir1 | uint32_t minus_features = 0;
|
1242 | 64a88d5d | blueswir1 | long long iu_version; |
1243 | 1a14026e | blueswir1 | uint32_t fpu_version, mmu_version, nwindows; |
1244 | 64a88d5d | blueswir1 | |
1245 | c48fcb47 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1246 | c48fcb47 | blueswir1 | if (strcasecmp(name, sparc_defs[i].name) == 0) { |
1247 | 64a88d5d | blueswir1 | def = &sparc_defs[i]; |
1248 | c48fcb47 | blueswir1 | } |
1249 | c48fcb47 | blueswir1 | } |
1250 | 64a88d5d | blueswir1 | if (!def)
|
1251 | 64a88d5d | blueswir1 | goto error;
|
1252 | 64a88d5d | blueswir1 | memcpy(cpu_def, def, sizeof(*def));
|
1253 | 64a88d5d | blueswir1 | |
1254 | 64a88d5d | blueswir1 | featurestr = strtok(NULL, ","); |
1255 | 64a88d5d | blueswir1 | while (featurestr) {
|
1256 | 64a88d5d | blueswir1 | char *val;
|
1257 | 64a88d5d | blueswir1 | |
1258 | 64a88d5d | blueswir1 | if (featurestr[0] == '+') { |
1259 | 64a88d5d | blueswir1 | add_flagname_to_bitmaps(featurestr + 1, &plus_features);
|
1260 | 64a88d5d | blueswir1 | } else if (featurestr[0] == '-') { |
1261 | 64a88d5d | blueswir1 | add_flagname_to_bitmaps(featurestr + 1, &minus_features);
|
1262 | 64a88d5d | blueswir1 | } else if ((val = strchr(featurestr, '='))) { |
1263 | 64a88d5d | blueswir1 | *val = 0; val++;
|
1264 | 64a88d5d | blueswir1 | if (!strcmp(featurestr, "iu_version")) { |
1265 | 64a88d5d | blueswir1 | char *err;
|
1266 | 64a88d5d | blueswir1 | |
1267 | 64a88d5d | blueswir1 | iu_version = strtoll(val, &err, 0);
|
1268 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1269 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1270 | 64a88d5d | blueswir1 | goto error;
|
1271 | 64a88d5d | blueswir1 | } |
1272 | 64a88d5d | blueswir1 | cpu_def->iu_version = iu_version; |
1273 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1274 | 64a88d5d | blueswir1 | fprintf(stderr, "iu_version %llx\n", iu_version);
|
1275 | 64a88d5d | blueswir1 | #endif
|
1276 | 64a88d5d | blueswir1 | } else if (!strcmp(featurestr, "fpu_version")) { |
1277 | 64a88d5d | blueswir1 | char *err;
|
1278 | 64a88d5d | blueswir1 | |
1279 | 64a88d5d | blueswir1 | fpu_version = strtol(val, &err, 0);
|
1280 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1281 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1282 | 64a88d5d | blueswir1 | goto error;
|
1283 | 64a88d5d | blueswir1 | } |
1284 | 64a88d5d | blueswir1 | cpu_def->fpu_version = fpu_version; |
1285 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1286 | 64a88d5d | blueswir1 | fprintf(stderr, "fpu_version %llx\n", fpu_version);
|
1287 | 64a88d5d | blueswir1 | #endif
|
1288 | 64a88d5d | blueswir1 | } else if (!strcmp(featurestr, "mmu_version")) { |
1289 | 64a88d5d | blueswir1 | char *err;
|
1290 | 64a88d5d | blueswir1 | |
1291 | 64a88d5d | blueswir1 | mmu_version = strtol(val, &err, 0);
|
1292 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1293 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1294 | 64a88d5d | blueswir1 | goto error;
|
1295 | 64a88d5d | blueswir1 | } |
1296 | 64a88d5d | blueswir1 | cpu_def->mmu_version = mmu_version; |
1297 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1298 | 64a88d5d | blueswir1 | fprintf(stderr, "mmu_version %llx\n", mmu_version);
|
1299 | 64a88d5d | blueswir1 | #endif
|
1300 | 1a14026e | blueswir1 | } else if (!strcmp(featurestr, "nwindows")) { |
1301 | 1a14026e | blueswir1 | char *err;
|
1302 | 1a14026e | blueswir1 | |
1303 | 1a14026e | blueswir1 | nwindows = strtol(val, &err, 0);
|
1304 | 1a14026e | blueswir1 | if (!*val || *err || nwindows > MAX_NWINDOWS ||
|
1305 | 1a14026e | blueswir1 | nwindows < MIN_NWINDOWS) { |
1306 | 1a14026e | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1307 | 1a14026e | blueswir1 | goto error;
|
1308 | 1a14026e | blueswir1 | } |
1309 | 1a14026e | blueswir1 | cpu_def->nwindows = nwindows; |
1310 | 1a14026e | blueswir1 | #ifdef DEBUG_FEATURES
|
1311 | 1a14026e | blueswir1 | fprintf(stderr, "nwindows %d\n", nwindows);
|
1312 | 1a14026e | blueswir1 | #endif
|
1313 | 64a88d5d | blueswir1 | } else {
|
1314 | 64a88d5d | blueswir1 | fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
1315 | 64a88d5d | blueswir1 | goto error;
|
1316 | 64a88d5d | blueswir1 | } |
1317 | 64a88d5d | blueswir1 | } else {
|
1318 | 77f193da | blueswir1 | fprintf(stderr, "feature string `%s' not in format "
|
1319 | 77f193da | blueswir1 | "(+feature|-feature|feature=xyz)\n", featurestr);
|
1320 | 64a88d5d | blueswir1 | goto error;
|
1321 | 64a88d5d | blueswir1 | } |
1322 | 64a88d5d | blueswir1 | featurestr = strtok(NULL, ","); |
1323 | 64a88d5d | blueswir1 | } |
1324 | 64a88d5d | blueswir1 | cpu_def->features |= plus_features; |
1325 | 64a88d5d | blueswir1 | cpu_def->features &= ~minus_features; |
1326 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1327 | 64a88d5d | blueswir1 | print_features(stderr, fprintf, cpu_def->features, NULL);
|
1328 | 64a88d5d | blueswir1 | #endif
|
1329 | 64a88d5d | blueswir1 | free(s); |
1330 | 64a88d5d | blueswir1 | return 0; |
1331 | 64a88d5d | blueswir1 | |
1332 | 64a88d5d | blueswir1 | error:
|
1333 | 64a88d5d | blueswir1 | free(s); |
1334 | 64a88d5d | blueswir1 | return -1; |
1335 | c48fcb47 | blueswir1 | } |
1336 | c48fcb47 | blueswir1 | |
1337 | 77f193da | blueswir1 | void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
1338 | c48fcb47 | blueswir1 | { |
1339 | c48fcb47 | blueswir1 | unsigned int i; |
1340 | c48fcb47 | blueswir1 | |
1341 | c48fcb47 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1342 | 1a14026e | blueswir1 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ", |
1343 | c48fcb47 | blueswir1 | sparc_defs[i].name, |
1344 | c48fcb47 | blueswir1 | sparc_defs[i].iu_version, |
1345 | c48fcb47 | blueswir1 | sparc_defs[i].fpu_version, |
1346 | 1a14026e | blueswir1 | sparc_defs[i].mmu_version, |
1347 | 1a14026e | blueswir1 | sparc_defs[i].nwindows); |
1348 | 77f193da | blueswir1 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
1349 | 77f193da | blueswir1 | ~sparc_defs[i].features, "-");
|
1350 | 77f193da | blueswir1 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & |
1351 | 77f193da | blueswir1 | sparc_defs[i].features, "+");
|
1352 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1353 | c48fcb47 | blueswir1 | } |
1354 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
|
1355 | f76981b1 | blueswir1 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
|
1356 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1357 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
|
1358 | f76981b1 | blueswir1 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
|
1359 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1360 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
|
1361 | f76981b1 | blueswir1 | "fpu_version mmu_version nwindows\n");
|
1362 | c48fcb47 | blueswir1 | } |
1363 | c48fcb47 | blueswir1 | |
1364 | c48fcb47 | blueswir1 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
1365 | c48fcb47 | blueswir1 | |
1366 | c48fcb47 | blueswir1 | void cpu_dump_state(CPUState *env, FILE *f,
|
1367 | c48fcb47 | blueswir1 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1368 | c48fcb47 | blueswir1 | int flags)
|
1369 | c48fcb47 | blueswir1 | { |
1370 | c48fcb47 | blueswir1 | int i, x;
|
1371 | c48fcb47 | blueswir1 | |
1372 | 77f193da | blueswir1 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
1373 | 77f193da | blueswir1 | env->npc); |
1374 | c48fcb47 | blueswir1 | cpu_fprintf(f, "General Registers:\n");
|
1375 | c48fcb47 | blueswir1 | for (i = 0; i < 4; i++) |
1376 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1377 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1378 | c48fcb47 | blueswir1 | for (; i < 8; i++) |
1379 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1380 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\nCurrent Register Window:\n");
|
1381 | c48fcb47 | blueswir1 | for (x = 0; x < 3; x++) { |
1382 | c48fcb47 | blueswir1 | for (i = 0; i < 4; i++) |
1383 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1384 | c48fcb47 | blueswir1 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
1385 | c48fcb47 | blueswir1 | env->regwptr[i + x * 8]);
|
1386 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1387 | c48fcb47 | blueswir1 | for (; i < 8; i++) |
1388 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1389 | c48fcb47 | blueswir1 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
1390 | c48fcb47 | blueswir1 | env->regwptr[i + x * 8]);
|
1391 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1392 | c48fcb47 | blueswir1 | } |
1393 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\nFloating Point Registers:\n");
|
1394 | c48fcb47 | blueswir1 | for (i = 0; i < 32; i++) { |
1395 | c48fcb47 | blueswir1 | if ((i & 3) == 0) |
1396 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%f%02d:", i);
|
1397 | a37ee56c | blueswir1 | cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]); |
1398 | c48fcb47 | blueswir1 | if ((i & 3) == 3) |
1399 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1400 | c48fcb47 | blueswir1 | } |
1401 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
1402 | c48fcb47 | blueswir1 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
1403 | c48fcb47 | blueswir1 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
1404 | 77f193da | blueswir1 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
|
1405 | 77f193da | blueswir1 | "cleanwin %d cwp %d\n",
|
1406 | c48fcb47 | blueswir1 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
1407 | 1a14026e | blueswir1 | env->cleanwin, env->nwindows - 1 - env->cwp);
|
1408 | c48fcb47 | blueswir1 | #else
|
1409 | 77f193da | blueswir1 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
|
1410 | 77f193da | blueswir1 | GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
1411 | 77f193da | blueswir1 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
1412 | 77f193da | blueswir1 | env->psrs?'S':'-', env->psrps?'P':'-', |
1413 | 77f193da | blueswir1 | env->psret?'E':'-', env->wim); |
1414 | c48fcb47 | blueswir1 | #endif
|
1415 | 3a3b925d | blueswir1 | cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
|
1416 | c48fcb47 | blueswir1 | } |
1417 | c48fcb47 | blueswir1 | |
1418 | 87ecb68b | pbrook | #ifdef TARGET_SPARC64
|
1419 | 87ecb68b | pbrook | #if !defined(CONFIG_USER_ONLY)
|
1420 | 87ecb68b | pbrook | #include "qemu-common.h" |
1421 | 87ecb68b | pbrook | #include "hw/irq.h" |
1422 | 87ecb68b | pbrook | #include "qemu-timer.h" |
1423 | 87ecb68b | pbrook | #endif
|
1424 | 87ecb68b | pbrook | |
1425 | ccd4a219 | blueswir1 | void helper_tick_set_count(void *opaque, uint64_t count) |
1426 | 87ecb68b | pbrook | { |
1427 | 87ecb68b | pbrook | #if !defined(CONFIG_USER_ONLY)
|
1428 | 87ecb68b | pbrook | ptimer_set_count(opaque, -count); |
1429 | 87ecb68b | pbrook | #endif
|
1430 | 87ecb68b | pbrook | } |
1431 | 87ecb68b | pbrook | |
1432 | ccd4a219 | blueswir1 | uint64_t helper_tick_get_count(void *opaque)
|
1433 | 87ecb68b | pbrook | { |
1434 | 87ecb68b | pbrook | #if !defined(CONFIG_USER_ONLY)
|
1435 | 87ecb68b | pbrook | return -ptimer_get_count(opaque);
|
1436 | 87ecb68b | pbrook | #else
|
1437 | 87ecb68b | pbrook | return 0; |
1438 | 87ecb68b | pbrook | #endif
|
1439 | 87ecb68b | pbrook | } |
1440 | 87ecb68b | pbrook | |
1441 | ccd4a219 | blueswir1 | void helper_tick_set_limit(void *opaque, uint64_t limit) |
1442 | 87ecb68b | pbrook | { |
1443 | 87ecb68b | pbrook | #if !defined(CONFIG_USER_ONLY)
|
1444 | 87ecb68b | pbrook | ptimer_set_limit(opaque, -limit, 0);
|
1445 | 87ecb68b | pbrook | #endif
|
1446 | 87ecb68b | pbrook | } |
1447 | 87ecb68b | pbrook | #endif |