root / target-sparc / machine.c @ 3a3b925d
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1 | 8dd3dca3 | aurel32 | #include "hw/hw.h" |
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2 | 8dd3dca3 | aurel32 | #include "hw/boards.h" |
3 | 0b8f1b10 | blueswir1 | #include "qemu-timer.h" |
4 | 8dd3dca3 | aurel32 | |
5 | 8dd3dca3 | aurel32 | #include "exec-all.h" |
6 | 8dd3dca3 | aurel32 | |
7 | 8dd3dca3 | aurel32 | void register_machines(void) |
8 | 8dd3dca3 | aurel32 | { |
9 | 8dd3dca3 | aurel32 | #ifdef TARGET_SPARC64
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10 | 8dd3dca3 | aurel32 | qemu_register_machine(&sun4u_machine); |
11 | c7ba218d | blueswir1 | qemu_register_machine(&sun4v_machine); |
12 | 8dd3dca3 | aurel32 | #else
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13 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss5_machine); |
14 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss10_machine); |
15 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss600mp_machine); |
16 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss20_machine); |
17 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss2_machine); |
18 | 8dd3dca3 | aurel32 | qemu_register_machine(&voyager_machine); |
19 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss_lx_machine); |
20 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss4_machine); |
21 | 8dd3dca3 | aurel32 | qemu_register_machine(&scls_machine); |
22 | 8dd3dca3 | aurel32 | qemu_register_machine(&sbook_machine); |
23 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss1000_machine); |
24 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss2000_machine); |
25 | 8dd3dca3 | aurel32 | #endif
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26 | 8dd3dca3 | aurel32 | } |
27 | 8dd3dca3 | aurel32 | |
28 | 8dd3dca3 | aurel32 | void cpu_save(QEMUFile *f, void *opaque) |
29 | 8dd3dca3 | aurel32 | { |
30 | 8dd3dca3 | aurel32 | CPUState *env = opaque; |
31 | 8dd3dca3 | aurel32 | int i;
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32 | 8dd3dca3 | aurel32 | uint32_t tmp; |
33 | 8dd3dca3 | aurel32 | |
34 | a7a044f2 | blueswir1 | // if env->cwp == env->nwindows - 1, this will set the ins of the last
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35 | a7a044f2 | blueswir1 | // window as the outs of the first window
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36 | a7a044f2 | blueswir1 | cpu_set_cwp(env, env->cwp); |
37 | a7a044f2 | blueswir1 | |
38 | 8dd3dca3 | aurel32 | for(i = 0; i < 8; i++) |
39 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->gregs[i]); |
40 | 1a14026e | blueswir1 | qemu_put_be32s(f, &env->nwindows); |
41 | 1a14026e | blueswir1 | for(i = 0; i < env->nwindows * 16; i++) |
42 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->regbase[i]); |
43 | 8dd3dca3 | aurel32 | |
44 | 8dd3dca3 | aurel32 | /* FPU */
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45 | 8dd3dca3 | aurel32 | for(i = 0; i < TARGET_FPREGS; i++) { |
46 | 8dd3dca3 | aurel32 | union {
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47 | 8dd3dca3 | aurel32 | float32 f; |
48 | 8dd3dca3 | aurel32 | uint32_t i; |
49 | 8dd3dca3 | aurel32 | } u; |
50 | 8dd3dca3 | aurel32 | u.f = env->fpr[i]; |
51 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.i); |
52 | 8dd3dca3 | aurel32 | } |
53 | 8dd3dca3 | aurel32 | |
54 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->pc); |
55 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->npc); |
56 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->y); |
57 | 8dd3dca3 | aurel32 | tmp = GET_PSR(env); |
58 | 8dd3dca3 | aurel32 | qemu_put_be32(f, tmp); |
59 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->fsr); |
60 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->tbr); |
61 | a7a044f2 | blueswir1 | tmp = env->interrupt_index; |
62 | a7a044f2 | blueswir1 | qemu_put_be32(f, tmp); |
63 | a7a044f2 | blueswir1 | qemu_put_be32s(f, &env->pil_in); |
64 | 8dd3dca3 | aurel32 | #ifndef TARGET_SPARC64
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65 | 8dd3dca3 | aurel32 | qemu_put_be32s(f, &env->wim); |
66 | 8dd3dca3 | aurel32 | /* MMU */
|
67 | 0b8f1b10 | blueswir1 | for (i = 0; i < 32; i++) |
68 | 8dd3dca3 | aurel32 | qemu_put_be32s(f, &env->mmuregs[i]); |
69 | 0b8f1b10 | blueswir1 | #else
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70 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->lsu); |
71 | 0b8f1b10 | blueswir1 | for (i = 0; i < 16; i++) { |
72 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->immuregs[i]); |
73 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->dmmuregs[i]); |
74 | 0b8f1b10 | blueswir1 | } |
75 | 0b8f1b10 | blueswir1 | for (i = 0; i < 64; i++) { |
76 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->itlb_tag[i]); |
77 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->itlb_tte[i]); |
78 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->dtlb_tag[i]); |
79 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->dtlb_tte[i]); |
80 | 0b8f1b10 | blueswir1 | } |
81 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->mmu_version); |
82 | c19148bd | blueswir1 | for (i = 0; i < MAXTL_MAX; i++) { |
83 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->ts[i].tpc); |
84 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->ts[i].tnpc); |
85 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->ts[i].tstate); |
86 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->ts[i].tt); |
87 | 0b8f1b10 | blueswir1 | } |
88 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->xcc); |
89 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->asi); |
90 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->pstate); |
91 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->tl); |
92 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->cansave); |
93 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->canrestore); |
94 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->otherwin); |
95 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->wstate); |
96 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->cleanwin); |
97 | 0b8f1b10 | blueswir1 | for (i = 0; i < 8; i++) |
98 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->agregs[i]); |
99 | 0b8f1b10 | blueswir1 | for (i = 0; i < 8; i++) |
100 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->bgregs[i]); |
101 | 0b8f1b10 | blueswir1 | for (i = 0; i < 8; i++) |
102 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->igregs[i]); |
103 | 0b8f1b10 | blueswir1 | for (i = 0; i < 8; i++) |
104 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->mgregs[i]); |
105 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->fprs); |
106 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->tick_cmpr); |
107 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->stick_cmpr); |
108 | 0b8f1b10 | blueswir1 | qemu_put_ptimer(f, env->tick); |
109 | 0b8f1b10 | blueswir1 | qemu_put_ptimer(f, env->stick); |
110 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->gsr); |
111 | 0b8f1b10 | blueswir1 | qemu_put_be32s(f, &env->gl); |
112 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->hpstate); |
113 | c19148bd | blueswir1 | for (i = 0; i < MAXTL_MAX; i++) |
114 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->htstate[i]); |
115 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->hintp); |
116 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->htba); |
117 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->hver); |
118 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->hstick_cmpr); |
119 | 0b8f1b10 | blueswir1 | qemu_put_be64s(f, &env->ssr); |
120 | a7a044f2 | blueswir1 | qemu_put_ptimer(f, env->hstick); |
121 | 8dd3dca3 | aurel32 | #endif
|
122 | 8dd3dca3 | aurel32 | } |
123 | 8dd3dca3 | aurel32 | |
124 | 8dd3dca3 | aurel32 | int cpu_load(QEMUFile *f, void *opaque, int version_id) |
125 | 8dd3dca3 | aurel32 | { |
126 | 8dd3dca3 | aurel32 | CPUState *env = opaque; |
127 | 8dd3dca3 | aurel32 | int i;
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128 | 8dd3dca3 | aurel32 | uint32_t tmp; |
129 | 8dd3dca3 | aurel32 | |
130 | 0b8f1b10 | blueswir1 | if (version_id != 5) |
131 | 1a14026e | blueswir1 | return -EINVAL;
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132 | 8dd3dca3 | aurel32 | for(i = 0; i < 8; i++) |
133 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->gregs[i]); |
134 | 1a14026e | blueswir1 | qemu_get_be32s(f, &env->nwindows); |
135 | 1a14026e | blueswir1 | for(i = 0; i < env->nwindows * 16; i++) |
136 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->regbase[i]); |
137 | 8dd3dca3 | aurel32 | |
138 | 8dd3dca3 | aurel32 | /* FPU */
|
139 | 8dd3dca3 | aurel32 | for(i = 0; i < TARGET_FPREGS; i++) { |
140 | 8dd3dca3 | aurel32 | union {
|
141 | 8dd3dca3 | aurel32 | float32 f; |
142 | 8dd3dca3 | aurel32 | uint32_t i; |
143 | 8dd3dca3 | aurel32 | } u; |
144 | 8dd3dca3 | aurel32 | u.i = qemu_get_be32(f); |
145 | 8dd3dca3 | aurel32 | env->fpr[i] = u.f; |
146 | 8dd3dca3 | aurel32 | } |
147 | 8dd3dca3 | aurel32 | |
148 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->pc); |
149 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->npc); |
150 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->y); |
151 | 8dd3dca3 | aurel32 | tmp = qemu_get_be32(f); |
152 | 8dd3dca3 | aurel32 | env->cwp = 0; /* needed to ensure that the wrapping registers are |
153 | 8dd3dca3 | aurel32 | correctly updated */
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154 | 8dd3dca3 | aurel32 | PUT_PSR(env, tmp); |
155 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->fsr); |
156 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->tbr); |
157 | a7a044f2 | blueswir1 | tmp = qemu_get_be32(f); |
158 | a7a044f2 | blueswir1 | env->interrupt_index = tmp; |
159 | a7a044f2 | blueswir1 | qemu_get_be32s(f, &env->pil_in); |
160 | 8dd3dca3 | aurel32 | #ifndef TARGET_SPARC64
|
161 | 8dd3dca3 | aurel32 | qemu_get_be32s(f, &env->wim); |
162 | 8dd3dca3 | aurel32 | /* MMU */
|
163 | 0b8f1b10 | blueswir1 | for (i = 0; i < 32; i++) |
164 | 8dd3dca3 | aurel32 | qemu_get_be32s(f, &env->mmuregs[i]); |
165 | 0b8f1b10 | blueswir1 | #else
|
166 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->lsu); |
167 | 0b8f1b10 | blueswir1 | for (i = 0; i < 16; i++) { |
168 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->immuregs[i]); |
169 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->dmmuregs[i]); |
170 | 0b8f1b10 | blueswir1 | } |
171 | 0b8f1b10 | blueswir1 | for (i = 0; i < 64; i++) { |
172 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->itlb_tag[i]); |
173 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->itlb_tte[i]); |
174 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->dtlb_tag[i]); |
175 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->dtlb_tte[i]); |
176 | 0b8f1b10 | blueswir1 | } |
177 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->mmu_version); |
178 | c19148bd | blueswir1 | for (i = 0; i < MAXTL_MAX; i++) { |
179 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->ts[i].tpc); |
180 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->ts[i].tnpc); |
181 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->ts[i].tstate); |
182 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->ts[i].tt); |
183 | 0b8f1b10 | blueswir1 | } |
184 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->xcc); |
185 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->asi); |
186 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->pstate); |
187 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->tl); |
188 | c19148bd | blueswir1 | env->tsptr = &env->ts[env->tl & MAXTL_MASK]; |
189 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->cansave); |
190 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->canrestore); |
191 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->otherwin); |
192 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->wstate); |
193 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->cleanwin); |
194 | 0b8f1b10 | blueswir1 | for (i = 0; i < 8; i++) |
195 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->agregs[i]); |
196 | 0b8f1b10 | blueswir1 | for (i = 0; i < 8; i++) |
197 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->bgregs[i]); |
198 | 0b8f1b10 | blueswir1 | for (i = 0; i < 8; i++) |
199 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->igregs[i]); |
200 | 0b8f1b10 | blueswir1 | for (i = 0; i < 8; i++) |
201 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->mgregs[i]); |
202 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->fprs); |
203 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->tick_cmpr); |
204 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->stick_cmpr); |
205 | 0b8f1b10 | blueswir1 | qemu_get_ptimer(f, env->tick); |
206 | 0b8f1b10 | blueswir1 | qemu_get_ptimer(f, env->stick); |
207 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->gsr); |
208 | 0b8f1b10 | blueswir1 | qemu_get_be32s(f, &env->gl); |
209 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->hpstate); |
210 | c19148bd | blueswir1 | for (i = 0; i < MAXTL_MAX; i++) |
211 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->htstate[i]); |
212 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->hintp); |
213 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->htba); |
214 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->hver); |
215 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->hstick_cmpr); |
216 | 0b8f1b10 | blueswir1 | qemu_get_be64s(f, &env->ssr); |
217 | 0b8f1b10 | blueswir1 | qemu_get_ptimer(f, env->hstick); |
218 | 8dd3dca3 | aurel32 | #endif
|
219 | 8dd3dca3 | aurel32 | tlb_flush(env, 1);
|
220 | 8dd3dca3 | aurel32 | return 0; |
221 | 8dd3dca3 | aurel32 | } |
222 | 8dd3dca3 | aurel32 |