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root / target-sparc / op_helper.c @ 3a3b925d

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#include "exec.h"
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#include "host-utils.h"
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#include "helper.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h"
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#endif /* !defined(CONFIG_USER_ONLY) */
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//#define DEBUG_MMU
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//#define DEBUG_MXCC
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//#define DEBUG_UNALIGNED
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//#define DEBUG_UNASSIGNED
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//#define DEBUG_ASI
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, args...) \
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do { printf("MMU: " fmt , ##args); } while (0)
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#else
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#define DPRINTF_MMU(fmt, args...) do {} while (0)
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#endif
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#ifdef DEBUG_MXCC
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#define DPRINTF_MXCC(fmt, args...) \
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do { printf("MXCC: " fmt , ##args); } while (0)
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#else
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#define DPRINTF_MXCC(fmt, args...) do {} while (0)
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#endif
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#ifdef DEBUG_ASI
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#define DPRINTF_ASI(fmt, args...) \
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do { printf("ASI: " fmt , ##args); } while (0)
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#else
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#define DPRINTF_ASI(fmt, args...) do {} while (0)
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#endif
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#ifdef TARGET_SPARC64
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#ifndef TARGET_ABI32
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#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
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#else
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#define AM_CHECK(env1) (1)
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#endif
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#endif
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static inline void address_mask(CPUState *env1, target_ulong *addr)
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{
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#ifdef TARGET_SPARC64
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    if (AM_CHECK(env1))
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        *addr &= 0xffffffffULL;
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#endif
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}
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void raise_exception(int tt)
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{
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    env->exception_index = tt;
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    cpu_loop_exit();
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}
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void helper_trap(target_ulong nb_trap)
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{
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    env->exception_index = TT_TRAP + (nb_trap & 0x7f);
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    cpu_loop_exit();
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}
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void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
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{
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    if (do_trap) {
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        env->exception_index = TT_TRAP + (nb_trap & 0x7f);
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        cpu_loop_exit();
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    }
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}
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static inline void set_cwp(int new_cwp)
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{
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    cpu_set_cwp(env, new_cwp);
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}
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void helper_check_align(target_ulong addr, uint32_t align)
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{
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    if (addr & align) {
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#ifdef DEBUG_UNALIGNED
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    printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
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           "\n", addr, env->pc);
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#endif
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        raise_exception(TT_UNALIGNED);
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    }
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}
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#define F_HELPER(name, p) void helper_f##name##p(void)
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#define F_BINOP(name)                                           \
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    F_HELPER(name, s)                                           \
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    {                                                           \
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        FT0 = float32_ ## name (FT0, FT1, &env->fp_status);     \
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    }                                                           \
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    F_HELPER(name, d)                                           \
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    {                                                           \
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        DT0 = float64_ ## name (DT0, DT1, &env->fp_status);     \
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    }                                                           \
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    F_HELPER(name, q)                                           \
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    {                                                           \
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        QT0 = float128_ ## name (QT0, QT1, &env->fp_status);    \
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    }
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F_BINOP(add);
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F_BINOP(sub);
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F_BINOP(mul);
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F_BINOP(div);
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#undef F_BINOP
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void helper_fsmuld(void)
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{
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    DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
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                      float32_to_float64(FT1, &env->fp_status),
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                      &env->fp_status);
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}
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void helper_fdmulq(void)
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{
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    QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
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                       float64_to_float128(DT1, &env->fp_status),
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                       &env->fp_status);
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}
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F_HELPER(neg, s)
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{
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    FT0 = float32_chs(FT1);
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}
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#ifdef TARGET_SPARC64
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F_HELPER(neg, d)
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{
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    DT0 = float64_chs(DT1);
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}
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F_HELPER(neg, q)
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{
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    QT0 = float128_chs(QT1);
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}
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#endif
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/* Integer to float conversion.  */
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F_HELPER(ito, s)
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{
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    FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
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}
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F_HELPER(ito, d)
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{
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    DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
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}
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F_HELPER(ito, q)
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{
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    QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
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}
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#ifdef TARGET_SPARC64
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F_HELPER(xto, s)
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{
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    FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
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}
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F_HELPER(xto, d)
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{
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    DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
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}
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F_HELPER(xto, q)
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{
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    QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
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}
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#endif
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#undef F_HELPER
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/* floating point conversion */
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void helper_fdtos(void)
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{
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    FT0 = float64_to_float32(DT1, &env->fp_status);
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}
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void helper_fstod(void)
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{
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    DT0 = float32_to_float64(FT1, &env->fp_status);
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}
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void helper_fqtos(void)
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{
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    FT0 = float128_to_float32(QT1, &env->fp_status);
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}
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void helper_fstoq(void)
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{
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    QT0 = float32_to_float128(FT1, &env->fp_status);
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}
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void helper_fqtod(void)
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{
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    DT0 = float128_to_float64(QT1, &env->fp_status);
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}
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void helper_fdtoq(void)
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{
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    QT0 = float64_to_float128(DT1, &env->fp_status);
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}
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/* Float to integer conversion.  */
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void helper_fstoi(void)
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{
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    *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
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}
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void helper_fdtoi(void)
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{
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    *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
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}
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void helper_fqtoi(void)
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{
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    *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
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}
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#ifdef TARGET_SPARC64
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void helper_fstox(void)
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{
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    *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
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}
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void helper_fdtox(void)
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{
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    *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
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}
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void helper_fqtox(void)
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{
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    *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
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}
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void helper_faligndata(void)
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{
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    uint64_t tmp;
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    tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
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    /* on many architectures a shift of 64 does nothing */
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    if ((env->gsr & 7) != 0) {
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        tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
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    }
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    *((uint64_t *)&DT0) = tmp;
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}
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void helper_movl_FT0_0(void)
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{
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    *((uint32_t *)&FT0) = 0;
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}
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void helper_movl_DT0_0(void)
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{
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    *((uint64_t *)&DT0) = 0;
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}
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void helper_movl_FT0_1(void)
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{
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    *((uint32_t *)&FT0) = 0xffffffff;
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}
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void helper_movl_DT0_1(void)
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{
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    *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
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}
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void helper_fnot(void)
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{
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    *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
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}
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void helper_fnots(void)
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{
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    *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
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}
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void helper_fnor(void)
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{
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    *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
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}
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void helper_fnors(void)
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{
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    *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
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}
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void helper_for(void)
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{
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    *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
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}
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void helper_fors(void)
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{
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    *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
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}
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void helper_fxor(void)
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{
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    *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
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}
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void helper_fxors(void)
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{
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    *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
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}
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void helper_fand(void)
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{
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    *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
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}
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void helper_fands(void)
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{
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    *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
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}
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void helper_fornot(void)
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{
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    *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
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}
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void helper_fornots(void)
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{
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    *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
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}
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void helper_fandnot(void)
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{
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    *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
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}
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void helper_fandnots(void)
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{
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    *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
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}
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void helper_fnand(void)
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{
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    *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
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}
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void helper_fnands(void)
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{
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    *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
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}
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void helper_fxnor(void)
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{
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    *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
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}
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void helper_fxnors(void)
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{
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    *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
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}
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#ifdef WORDS_BIGENDIAN
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#define VIS_B64(n) b[7 - (n)]
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#define VIS_W64(n) w[3 - (n)]
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#define VIS_SW64(n) sw[3 - (n)]
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#define VIS_L64(n) l[1 - (n)]
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#define VIS_B32(n) b[3 - (n)]
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#define VIS_W32(n) w[1 - (n)]
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#else
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#define VIS_B64(n) b[n]
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#define VIS_W64(n) w[n]
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#define VIS_SW64(n) sw[n]
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#define VIS_L64(n) l[n]
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#define VIS_B32(n) b[n]
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#define VIS_W32(n) w[n]
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#endif
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typedef union {
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    uint8_t b[8];
377 44e7757c blueswir1
    uint16_t w[4];
378 44e7757c blueswir1
    int16_t sw[4];
379 44e7757c blueswir1
    uint32_t l[2];
380 44e7757c blueswir1
    float64 d;
381 44e7757c blueswir1
} vis64;
382 44e7757c blueswir1
383 44e7757c blueswir1
typedef union {
384 44e7757c blueswir1
    uint8_t b[4];
385 44e7757c blueswir1
    uint16_t w[2];
386 44e7757c blueswir1
    uint32_t l;
387 44e7757c blueswir1
    float32 f;
388 44e7757c blueswir1
} vis32;
389 44e7757c blueswir1
390 44e7757c blueswir1
void helper_fpmerge(void)
391 44e7757c blueswir1
{
392 44e7757c blueswir1
    vis64 s, d;
393 44e7757c blueswir1
394 44e7757c blueswir1
    s.d = DT0;
395 44e7757c blueswir1
    d.d = DT1;
396 44e7757c blueswir1
397 44e7757c blueswir1
    // Reverse calculation order to handle overlap
398 44e7757c blueswir1
    d.VIS_B64(7) = s.VIS_B64(3);
399 44e7757c blueswir1
    d.VIS_B64(6) = d.VIS_B64(3);
400 44e7757c blueswir1
    d.VIS_B64(5) = s.VIS_B64(2);
401 44e7757c blueswir1
    d.VIS_B64(4) = d.VIS_B64(2);
402 44e7757c blueswir1
    d.VIS_B64(3) = s.VIS_B64(1);
403 44e7757c blueswir1
    d.VIS_B64(2) = d.VIS_B64(1);
404 44e7757c blueswir1
    d.VIS_B64(1) = s.VIS_B64(0);
405 44e7757c blueswir1
    //d.VIS_B64(0) = d.VIS_B64(0);
406 44e7757c blueswir1
407 44e7757c blueswir1
    DT0 = d.d;
408 44e7757c blueswir1
}
409 44e7757c blueswir1
410 44e7757c blueswir1
void helper_fmul8x16(void)
411 44e7757c blueswir1
{
412 44e7757c blueswir1
    vis64 s, d;
413 44e7757c blueswir1
    uint32_t tmp;
414 44e7757c blueswir1
415 44e7757c blueswir1
    s.d = DT0;
416 44e7757c blueswir1
    d.d = DT1;
417 44e7757c blueswir1
418 44e7757c blueswir1
#define PMUL(r)                                                 \
419 44e7757c blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r);       \
420 44e7757c blueswir1
    if ((tmp & 0xff) > 0x7f)                                    \
421 44e7757c blueswir1
        tmp += 0x100;                                           \
422 44e7757c blueswir1
    d.VIS_W64(r) = tmp >> 8;
423 44e7757c blueswir1
424 44e7757c blueswir1
    PMUL(0);
425 44e7757c blueswir1
    PMUL(1);
426 44e7757c blueswir1
    PMUL(2);
427 44e7757c blueswir1
    PMUL(3);
428 44e7757c blueswir1
#undef PMUL
429 44e7757c blueswir1
430 44e7757c blueswir1
    DT0 = d.d;
431 44e7757c blueswir1
}
432 44e7757c blueswir1
433 44e7757c blueswir1
void helper_fmul8x16al(void)
434 44e7757c blueswir1
{
435 44e7757c blueswir1
    vis64 s, d;
436 44e7757c blueswir1
    uint32_t tmp;
437 44e7757c blueswir1
438 44e7757c blueswir1
    s.d = DT0;
439 44e7757c blueswir1
    d.d = DT1;
440 44e7757c blueswir1
441 44e7757c blueswir1
#define PMUL(r)                                                 \
442 44e7757c blueswir1
    tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r);       \
443 44e7757c blueswir1
    if ((tmp & 0xff) > 0x7f)                                    \
444 44e7757c blueswir1
        tmp += 0x100;                                           \
445 44e7757c blueswir1
    d.VIS_W64(r) = tmp >> 8;
446 44e7757c blueswir1
447 44e7757c blueswir1
    PMUL(0);
448 44e7757c blueswir1
    PMUL(1);
449 44e7757c blueswir1
    PMUL(2);
450 44e7757c blueswir1
    PMUL(3);
451 44e7757c blueswir1
#undef PMUL
452 44e7757c blueswir1
453 44e7757c blueswir1
    DT0 = d.d;
454 44e7757c blueswir1
}
455 44e7757c blueswir1
456 44e7757c blueswir1
void helper_fmul8x16au(void)
457 44e7757c blueswir1
{
458 44e7757c blueswir1
    vis64 s, d;
459 44e7757c blueswir1
    uint32_t tmp;
460 44e7757c blueswir1
461 44e7757c blueswir1
    s.d = DT0;
462 44e7757c blueswir1
    d.d = DT1;
463 44e7757c blueswir1
464 44e7757c blueswir1
#define PMUL(r)                                                 \
465 44e7757c blueswir1
    tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r);       \
466 44e7757c blueswir1
    if ((tmp & 0xff) > 0x7f)                                    \
467 44e7757c blueswir1
        tmp += 0x100;                                           \
468 44e7757c blueswir1
    d.VIS_W64(r) = tmp >> 8;
469 44e7757c blueswir1
470 44e7757c blueswir1
    PMUL(0);
471 44e7757c blueswir1
    PMUL(1);
472 44e7757c blueswir1
    PMUL(2);
473 44e7757c blueswir1
    PMUL(3);
474 44e7757c blueswir1
#undef PMUL
475 44e7757c blueswir1
476 44e7757c blueswir1
    DT0 = d.d;
477 44e7757c blueswir1
}
478 44e7757c blueswir1
479 44e7757c blueswir1
void helper_fmul8sux16(void)
480 44e7757c blueswir1
{
481 44e7757c blueswir1
    vis64 s, d;
482 44e7757c blueswir1
    uint32_t tmp;
483 44e7757c blueswir1
484 44e7757c blueswir1
    s.d = DT0;
485 44e7757c blueswir1
    d.d = DT1;
486 44e7757c blueswir1
487 44e7757c blueswir1
#define PMUL(r)                                                         \
488 44e7757c blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8);       \
489 44e7757c blueswir1
    if ((tmp & 0xff) > 0x7f)                                            \
490 44e7757c blueswir1
        tmp += 0x100;                                                   \
491 44e7757c blueswir1
    d.VIS_W64(r) = tmp >> 8;
492 44e7757c blueswir1
493 44e7757c blueswir1
    PMUL(0);
494 44e7757c blueswir1
    PMUL(1);
495 44e7757c blueswir1
    PMUL(2);
496 44e7757c blueswir1
    PMUL(3);
497 44e7757c blueswir1
#undef PMUL
498 44e7757c blueswir1
499 44e7757c blueswir1
    DT0 = d.d;
500 44e7757c blueswir1
}
501 44e7757c blueswir1
502 44e7757c blueswir1
void helper_fmul8ulx16(void)
503 44e7757c blueswir1
{
504 44e7757c blueswir1
    vis64 s, d;
505 44e7757c blueswir1
    uint32_t tmp;
506 44e7757c blueswir1
507 44e7757c blueswir1
    s.d = DT0;
508 44e7757c blueswir1
    d.d = DT1;
509 44e7757c blueswir1
510 44e7757c blueswir1
#define PMUL(r)                                                         \
511 44e7757c blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2));        \
512 44e7757c blueswir1
    if ((tmp & 0xff) > 0x7f)                                            \
513 44e7757c blueswir1
        tmp += 0x100;                                                   \
514 44e7757c blueswir1
    d.VIS_W64(r) = tmp >> 8;
515 44e7757c blueswir1
516 44e7757c blueswir1
    PMUL(0);
517 44e7757c blueswir1
    PMUL(1);
518 44e7757c blueswir1
    PMUL(2);
519 44e7757c blueswir1
    PMUL(3);
520 44e7757c blueswir1
#undef PMUL
521 44e7757c blueswir1
522 44e7757c blueswir1
    DT0 = d.d;
523 44e7757c blueswir1
}
524 44e7757c blueswir1
525 44e7757c blueswir1
void helper_fmuld8sux16(void)
526 44e7757c blueswir1
{
527 44e7757c blueswir1
    vis64 s, d;
528 44e7757c blueswir1
    uint32_t tmp;
529 44e7757c blueswir1
530 44e7757c blueswir1
    s.d = DT0;
531 44e7757c blueswir1
    d.d = DT1;
532 44e7757c blueswir1
533 44e7757c blueswir1
#define PMUL(r)                                                         \
534 44e7757c blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8);       \
535 44e7757c blueswir1
    if ((tmp & 0xff) > 0x7f)                                            \
536 44e7757c blueswir1
        tmp += 0x100;                                                   \
537 44e7757c blueswir1
    d.VIS_L64(r) = tmp;
538 44e7757c blueswir1
539 44e7757c blueswir1
    // Reverse calculation order to handle overlap
540 44e7757c blueswir1
    PMUL(1);
541 44e7757c blueswir1
    PMUL(0);
542 44e7757c blueswir1
#undef PMUL
543 44e7757c blueswir1
544 44e7757c blueswir1
    DT0 = d.d;
545 44e7757c blueswir1
}
546 44e7757c blueswir1
547 44e7757c blueswir1
void helper_fmuld8ulx16(void)
548 44e7757c blueswir1
{
549 44e7757c blueswir1
    vis64 s, d;
550 44e7757c blueswir1
    uint32_t tmp;
551 44e7757c blueswir1
552 44e7757c blueswir1
    s.d = DT0;
553 44e7757c blueswir1
    d.d = DT1;
554 44e7757c blueswir1
555 44e7757c blueswir1
#define PMUL(r)                                                         \
556 44e7757c blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2));        \
557 44e7757c blueswir1
    if ((tmp & 0xff) > 0x7f)                                            \
558 44e7757c blueswir1
        tmp += 0x100;                                                   \
559 44e7757c blueswir1
    d.VIS_L64(r) = tmp;
560 44e7757c blueswir1
561 44e7757c blueswir1
    // Reverse calculation order to handle overlap
562 44e7757c blueswir1
    PMUL(1);
563 44e7757c blueswir1
    PMUL(0);
564 44e7757c blueswir1
#undef PMUL
565 44e7757c blueswir1
566 44e7757c blueswir1
    DT0 = d.d;
567 44e7757c blueswir1
}
568 44e7757c blueswir1
569 44e7757c blueswir1
void helper_fexpand(void)
570 44e7757c blueswir1
{
571 44e7757c blueswir1
    vis32 s;
572 44e7757c blueswir1
    vis64 d;
573 44e7757c blueswir1
574 44e7757c blueswir1
    s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
575 44e7757c blueswir1
    d.d = DT1;
576 44e7757c blueswir1
    d.VIS_L64(0) = s.VIS_W32(0) << 4;
577 44e7757c blueswir1
    d.VIS_L64(1) = s.VIS_W32(1) << 4;
578 44e7757c blueswir1
    d.VIS_L64(2) = s.VIS_W32(2) << 4;
579 44e7757c blueswir1
    d.VIS_L64(3) = s.VIS_W32(3) << 4;
580 44e7757c blueswir1
581 44e7757c blueswir1
    DT0 = d.d;
582 44e7757c blueswir1
}
583 44e7757c blueswir1
584 44e7757c blueswir1
#define VIS_HELPER(name, F)                             \
585 44e7757c blueswir1
    void name##16(void)                                 \
586 44e7757c blueswir1
    {                                                   \
587 44e7757c blueswir1
        vis64 s, d;                                     \
588 44e7757c blueswir1
                                                        \
589 44e7757c blueswir1
        s.d = DT0;                                      \
590 44e7757c blueswir1
        d.d = DT1;                                      \
591 44e7757c blueswir1
                                                        \
592 44e7757c blueswir1
        d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0));   \
593 44e7757c blueswir1
        d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1));   \
594 44e7757c blueswir1
        d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2));   \
595 44e7757c blueswir1
        d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3));   \
596 44e7757c blueswir1
                                                        \
597 44e7757c blueswir1
        DT0 = d.d;                                      \
598 44e7757c blueswir1
    }                                                   \
599 44e7757c blueswir1
                                                        \
600 44e7757c blueswir1
    void name##16s(void)                                \
601 44e7757c blueswir1
    {                                                   \
602 44e7757c blueswir1
        vis32 s, d;                                     \
603 44e7757c blueswir1
                                                        \
604 44e7757c blueswir1
        s.f = FT0;                                      \
605 44e7757c blueswir1
        d.f = FT1;                                      \
606 44e7757c blueswir1
                                                        \
607 44e7757c blueswir1
        d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0));   \
608 44e7757c blueswir1
        d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1));   \
609 44e7757c blueswir1
                                                        \
610 44e7757c blueswir1
        FT0 = d.f;                                      \
611 44e7757c blueswir1
    }                                                   \
612 44e7757c blueswir1
                                                        \
613 44e7757c blueswir1
    void name##32(void)                                 \
614 44e7757c blueswir1
    {                                                   \
615 44e7757c blueswir1
        vis64 s, d;                                     \
616 44e7757c blueswir1
                                                        \
617 44e7757c blueswir1
        s.d = DT0;                                      \
618 44e7757c blueswir1
        d.d = DT1;                                      \
619 44e7757c blueswir1
                                                        \
620 44e7757c blueswir1
        d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0));   \
621 44e7757c blueswir1
        d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1));   \
622 44e7757c blueswir1
                                                        \
623 44e7757c blueswir1
        DT0 = d.d;                                      \
624 44e7757c blueswir1
    }                                                   \
625 44e7757c blueswir1
                                                        \
626 44e7757c blueswir1
    void name##32s(void)                                \
627 44e7757c blueswir1
    {                                                   \
628 44e7757c blueswir1
        vis32 s, d;                                     \
629 44e7757c blueswir1
                                                        \
630 44e7757c blueswir1
        s.f = FT0;                                      \
631 44e7757c blueswir1
        d.f = FT1;                                      \
632 44e7757c blueswir1
                                                        \
633 44e7757c blueswir1
        d.l = F(d.l, s.l);                              \
634 44e7757c blueswir1
                                                        \
635 44e7757c blueswir1
        FT0 = d.f;                                      \
636 44e7757c blueswir1
    }
637 44e7757c blueswir1
638 44e7757c blueswir1
#define FADD(a, b) ((a) + (b))
639 44e7757c blueswir1
#define FSUB(a, b) ((a) - (b))
640 44e7757c blueswir1
VIS_HELPER(helper_fpadd, FADD)
641 44e7757c blueswir1
VIS_HELPER(helper_fpsub, FSUB)
642 44e7757c blueswir1
643 44e7757c blueswir1
#define VIS_CMPHELPER(name, F)                                        \
644 44e7757c blueswir1
    void name##16(void)                                           \
645 44e7757c blueswir1
    {                                                             \
646 44e7757c blueswir1
        vis64 s, d;                                               \
647 44e7757c blueswir1
                                                                  \
648 44e7757c blueswir1
        s.d = DT0;                                                \
649 44e7757c blueswir1
        d.d = DT1;                                                \
650 44e7757c blueswir1
                                                                  \
651 44e7757c blueswir1
        d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0;       \
652 44e7757c blueswir1
        d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0;      \
653 44e7757c blueswir1
        d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0;      \
654 44e7757c blueswir1
        d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0;      \
655 44e7757c blueswir1
                                                                  \
656 44e7757c blueswir1
        DT0 = d.d;                                                \
657 44e7757c blueswir1
    }                                                             \
658 44e7757c blueswir1
                                                                  \
659 44e7757c blueswir1
    void name##32(void)                                           \
660 44e7757c blueswir1
    {                                                             \
661 44e7757c blueswir1
        vis64 s, d;                                               \
662 44e7757c blueswir1
                                                                  \
663 44e7757c blueswir1
        s.d = DT0;                                                \
664 44e7757c blueswir1
        d.d = DT1;                                                \
665 44e7757c blueswir1
                                                                  \
666 44e7757c blueswir1
        d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0;       \
667 44e7757c blueswir1
        d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0;      \
668 44e7757c blueswir1
                                                                  \
669 44e7757c blueswir1
        DT0 = d.d;                                                \
670 44e7757c blueswir1
    }
671 44e7757c blueswir1
672 44e7757c blueswir1
#define FCMPGT(a, b) ((a) > (b))
673 44e7757c blueswir1
#define FCMPEQ(a, b) ((a) == (b))
674 44e7757c blueswir1
#define FCMPLE(a, b) ((a) <= (b))
675 44e7757c blueswir1
#define FCMPNE(a, b) ((a) != (b))
676 44e7757c blueswir1
677 44e7757c blueswir1
VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
678 44e7757c blueswir1
VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
679 44e7757c blueswir1
VIS_CMPHELPER(helper_fcmple, FCMPLE)
680 44e7757c blueswir1
VIS_CMPHELPER(helper_fcmpne, FCMPNE)
681 44e7757c blueswir1
#endif
682 44e7757c blueswir1
683 44e7757c blueswir1
void helper_check_ieee_exceptions(void)
684 44e7757c blueswir1
{
685 44e7757c blueswir1
    target_ulong status;
686 44e7757c blueswir1
687 44e7757c blueswir1
    status = get_float_exception_flags(&env->fp_status);
688 44e7757c blueswir1
    if (status) {
689 44e7757c blueswir1
        /* Copy IEEE 754 flags into FSR */
690 44e7757c blueswir1
        if (status & float_flag_invalid)
691 44e7757c blueswir1
            env->fsr |= FSR_NVC;
692 44e7757c blueswir1
        if (status & float_flag_overflow)
693 44e7757c blueswir1
            env->fsr |= FSR_OFC;
694 44e7757c blueswir1
        if (status & float_flag_underflow)
695 44e7757c blueswir1
            env->fsr |= FSR_UFC;
696 44e7757c blueswir1
        if (status & float_flag_divbyzero)
697 44e7757c blueswir1
            env->fsr |= FSR_DZC;
698 44e7757c blueswir1
        if (status & float_flag_inexact)
699 44e7757c blueswir1
            env->fsr |= FSR_NXC;
700 44e7757c blueswir1
701 44e7757c blueswir1
        if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
702 44e7757c blueswir1
            /* Unmasked exception, generate a trap */
703 44e7757c blueswir1
            env->fsr |= FSR_FTT_IEEE_EXCP;
704 44e7757c blueswir1
            raise_exception(TT_FP_EXCP);
705 44e7757c blueswir1
        } else {
706 44e7757c blueswir1
            /* Accumulate exceptions */
707 44e7757c blueswir1
            env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
708 44e7757c blueswir1
        }
709 44e7757c blueswir1
    }
710 44e7757c blueswir1
}
711 44e7757c blueswir1
712 44e7757c blueswir1
void helper_clear_float_exceptions(void)
713 44e7757c blueswir1
{
714 44e7757c blueswir1
    set_float_exception_flags(0, &env->fp_status);
715 44e7757c blueswir1
}
716 44e7757c blueswir1
717 7e8c2b6c blueswir1
void helper_fabss(void)
718 e8af50a3 bellard
{
719 7a0e1f41 bellard
    FT0 = float32_abs(FT1);
720 e8af50a3 bellard
}
721 e8af50a3 bellard
722 3475187d bellard
#ifdef TARGET_SPARC64
723 7e8c2b6c blueswir1
void helper_fabsd(void)
724 3475187d bellard
{
725 3475187d bellard
    DT0 = float64_abs(DT1);
726 3475187d bellard
}
727 4e14008f blueswir1
728 4e14008f blueswir1
void helper_fabsq(void)
729 4e14008f blueswir1
{
730 4e14008f blueswir1
    QT0 = float128_abs(QT1);
731 4e14008f blueswir1
}
732 4e14008f blueswir1
#endif
733 3475187d bellard
734 7e8c2b6c blueswir1
void helper_fsqrts(void)
735 e8af50a3 bellard
{
736 7a0e1f41 bellard
    FT0 = float32_sqrt(FT1, &env->fp_status);
737 e8af50a3 bellard
}
738 e8af50a3 bellard
739 7e8c2b6c blueswir1
void helper_fsqrtd(void)
740 e8af50a3 bellard
{
741 7a0e1f41 bellard
    DT0 = float64_sqrt(DT1, &env->fp_status);
742 e8af50a3 bellard
}
743 e8af50a3 bellard
744 4e14008f blueswir1
void helper_fsqrtq(void)
745 4e14008f blueswir1
{
746 4e14008f blueswir1
    QT0 = float128_sqrt(QT1, &env->fp_status);
747 4e14008f blueswir1
}
748 4e14008f blueswir1
749 417454b0 blueswir1
#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP)                      \
750 7e8c2b6c blueswir1
    void glue(helper_, name) (void)                                     \
751 65ce8c2f bellard
    {                                                                   \
752 1a2fb1c0 blueswir1
        target_ulong new_fsr;                                           \
753 1a2fb1c0 blueswir1
                                                                        \
754 65ce8c2f bellard
        env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \
755 65ce8c2f bellard
        switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
756 65ce8c2f bellard
        case float_relation_unordered:                                  \
757 1a2fb1c0 blueswir1
            new_fsr = (FSR_FCC1 | FSR_FCC0) << FS;                      \
758 417454b0 blueswir1
            if ((env->fsr & FSR_NVM) || TRAP) {                         \
759 1a2fb1c0 blueswir1
                env->fsr |= new_fsr;                                    \
760 417454b0 blueswir1
                env->fsr |= FSR_NVC;                                    \
761 417454b0 blueswir1
                env->fsr |= FSR_FTT_IEEE_EXCP;                          \
762 65ce8c2f bellard
                raise_exception(TT_FP_EXCP);                            \
763 65ce8c2f bellard
            } else {                                                    \
764 65ce8c2f bellard
                env->fsr |= FSR_NVA;                                    \
765 65ce8c2f bellard
            }                                                           \
766 65ce8c2f bellard
            break;                                                      \
767 65ce8c2f bellard
        case float_relation_less:                                       \
768 1a2fb1c0 blueswir1
            new_fsr = FSR_FCC0 << FS;                                   \
769 65ce8c2f bellard
            break;                                                      \
770 65ce8c2f bellard
        case float_relation_greater:                                    \
771 1a2fb1c0 blueswir1
            new_fsr = FSR_FCC1 << FS;                                   \
772 65ce8c2f bellard
            break;                                                      \
773 65ce8c2f bellard
        default:                                                        \
774 1a2fb1c0 blueswir1
            new_fsr = 0;                                                \
775 65ce8c2f bellard
            break;                                                      \
776 65ce8c2f bellard
        }                                                               \
777 1a2fb1c0 blueswir1
        env->fsr |= new_fsr;                                            \
778 e8af50a3 bellard
    }
779 e8af50a3 bellard
780 417454b0 blueswir1
GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
781 417454b0 blueswir1
GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
782 417454b0 blueswir1
783 417454b0 blueswir1
GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
784 417454b0 blueswir1
GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
785 3475187d bellard
786 4e14008f blueswir1
GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
787 4e14008f blueswir1
GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
788 4e14008f blueswir1
789 3475187d bellard
#ifdef TARGET_SPARC64
790 417454b0 blueswir1
GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
791 417454b0 blueswir1
GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
792 64a88d5d blueswir1
GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
793 417454b0 blueswir1
794 417454b0 blueswir1
GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
795 417454b0 blueswir1
GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
796 64a88d5d blueswir1
GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
797 417454b0 blueswir1
798 417454b0 blueswir1
GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
799 417454b0 blueswir1
GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
800 64a88d5d blueswir1
GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
801 417454b0 blueswir1
802 417454b0 blueswir1
GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
803 417454b0 blueswir1
GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
804 64a88d5d blueswir1
GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
805 3475187d bellard
806 417454b0 blueswir1
GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
807 417454b0 blueswir1
GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
808 64a88d5d blueswir1
GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
809 3475187d bellard
810 417454b0 blueswir1
GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
811 417454b0 blueswir1
GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
812 4e14008f blueswir1
GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
813 4e14008f blueswir1
#endif
814 3475187d bellard
815 77f193da blueswir1
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
816 77f193da blueswir1
    defined(DEBUG_MXCC)
817 952a328f blueswir1
static void dump_mxcc(CPUState *env)
818 952a328f blueswir1
{
819 952a328f blueswir1
    printf("mxccdata: %016llx %016llx %016llx %016llx\n",
820 77f193da blueswir1
           env->mxccdata[0], env->mxccdata[1],
821 77f193da blueswir1
           env->mxccdata[2], env->mxccdata[3]);
822 952a328f blueswir1
    printf("mxccregs: %016llx %016llx %016llx %016llx\n"
823 952a328f blueswir1
           "          %016llx %016llx %016llx %016llx\n",
824 77f193da blueswir1
           env->mxccregs[0], env->mxccregs[1],
825 77f193da blueswir1
           env->mxccregs[2], env->mxccregs[3],
826 77f193da blueswir1
           env->mxccregs[4], env->mxccregs[5],
827 77f193da blueswir1
           env->mxccregs[6], env->mxccregs[7]);
828 952a328f blueswir1
}
829 952a328f blueswir1
#endif
830 952a328f blueswir1
831 1a2fb1c0 blueswir1
#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
832 1a2fb1c0 blueswir1
    && defined(DEBUG_ASI)
833 1a2fb1c0 blueswir1
static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
834 1a2fb1c0 blueswir1
                     uint64_t r1)
835 8543e2cf blueswir1
{
836 8543e2cf blueswir1
    switch (size)
837 8543e2cf blueswir1
    {
838 8543e2cf blueswir1
    case 1:
839 1a2fb1c0 blueswir1
        DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
840 1a2fb1c0 blueswir1
                    addr, asi, r1 & 0xff);
841 8543e2cf blueswir1
        break;
842 8543e2cf blueswir1
    case 2:
843 1a2fb1c0 blueswir1
        DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
844 1a2fb1c0 blueswir1
                    addr, asi, r1 & 0xffff);
845 8543e2cf blueswir1
        break;
846 8543e2cf blueswir1
    case 4:
847 1a2fb1c0 blueswir1
        DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
848 1a2fb1c0 blueswir1
                    addr, asi, r1 & 0xffffffff);
849 8543e2cf blueswir1
        break;
850 8543e2cf blueswir1
    case 8:
851 1a2fb1c0 blueswir1
        DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
852 1a2fb1c0 blueswir1
                    addr, asi, r1);
853 8543e2cf blueswir1
        break;
854 8543e2cf blueswir1
    }
855 8543e2cf blueswir1
}
856 8543e2cf blueswir1
#endif
857 8543e2cf blueswir1
858 1a2fb1c0 blueswir1
#ifndef TARGET_SPARC64
859 1a2fb1c0 blueswir1
#ifndef CONFIG_USER_ONLY
860 1a2fb1c0 blueswir1
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
861 e8af50a3 bellard
{
862 1a2fb1c0 blueswir1
    uint64_t ret = 0;
863 8543e2cf blueswir1
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
864 1a2fb1c0 blueswir1
    uint32_t last_addr = addr;
865 952a328f blueswir1
#endif
866 e80cfcfc bellard
867 c2bc0e38 blueswir1
    helper_check_align(addr, size - 1);
868 e80cfcfc bellard
    switch (asi) {
869 6c36d3fa blueswir1
    case 2: /* SuperSparc MXCC registers */
870 1a2fb1c0 blueswir1
        switch (addr) {
871 952a328f blueswir1
        case 0x01c00a00: /* MXCC control register */
872 1a2fb1c0 blueswir1
            if (size == 8)
873 1a2fb1c0 blueswir1
                ret = env->mxccregs[3];
874 1a2fb1c0 blueswir1
            else
875 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
876 77f193da blueswir1
                             size);
877 952a328f blueswir1
            break;
878 952a328f blueswir1
        case 0x01c00a04: /* MXCC control register */
879 952a328f blueswir1
            if (size == 4)
880 952a328f blueswir1
                ret = env->mxccregs[3];
881 952a328f blueswir1
            else
882 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
883 77f193da blueswir1
                             size);
884 952a328f blueswir1
            break;
885 295db113 blueswir1
        case 0x01c00c00: /* Module reset register */
886 295db113 blueswir1
            if (size == 8) {
887 1a2fb1c0 blueswir1
                ret = env->mxccregs[5];
888 295db113 blueswir1
                // should we do something here?
889 295db113 blueswir1
            } else
890 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
891 77f193da blueswir1
                             size);
892 295db113 blueswir1
            break;
893 952a328f blueswir1
        case 0x01c00f00: /* MBus port address register */
894 1a2fb1c0 blueswir1
            if (size == 8)
895 1a2fb1c0 blueswir1
                ret = env->mxccregs[7];
896 1a2fb1c0 blueswir1
            else
897 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
898 77f193da blueswir1
                             size);
899 952a328f blueswir1
            break;
900 952a328f blueswir1
        default:
901 77f193da blueswir1
            DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
902 77f193da blueswir1
                         size);
903 952a328f blueswir1
            break;
904 952a328f blueswir1
        }
905 77f193da blueswir1
        DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
906 77f193da blueswir1
                     "addr = %08x -> ret = %08x,"
907 1a2fb1c0 blueswir1
                     "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
908 952a328f blueswir1
#ifdef DEBUG_MXCC
909 952a328f blueswir1
        dump_mxcc(env);
910 952a328f blueswir1
#endif
911 6c36d3fa blueswir1
        break;
912 e8af50a3 bellard
    case 3: /* MMU probe */
913 0f8a249a blueswir1
        {
914 0f8a249a blueswir1
            int mmulev;
915 0f8a249a blueswir1
916 1a2fb1c0 blueswir1
            mmulev = (addr >> 8) & 15;
917 0f8a249a blueswir1
            if (mmulev > 4)
918 0f8a249a blueswir1
                ret = 0;
919 1a2fb1c0 blueswir1
            else
920 1a2fb1c0 blueswir1
                ret = mmu_probe(env, addr, mmulev);
921 1a2fb1c0 blueswir1
            DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
922 1a2fb1c0 blueswir1
                        addr, mmulev, ret);
923 0f8a249a blueswir1
        }
924 0f8a249a blueswir1
        break;
925 e8af50a3 bellard
    case 4: /* read MMU regs */
926 0f8a249a blueswir1
        {
927 1a2fb1c0 blueswir1
            int reg = (addr >> 8) & 0x1f;
928 3b46e624 ths
929 0f8a249a blueswir1
            ret = env->mmuregs[reg];
930 0f8a249a blueswir1
            if (reg == 3) /* Fault status cleared on read */
931 3dd9a152 blueswir1
                env->mmuregs[3] = 0;
932 3dd9a152 blueswir1
            else if (reg == 0x13) /* Fault status read */
933 3dd9a152 blueswir1
                ret = env->mmuregs[3];
934 3dd9a152 blueswir1
            else if (reg == 0x14) /* Fault address read */
935 3dd9a152 blueswir1
                ret = env->mmuregs[4];
936 1a2fb1c0 blueswir1
            DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
937 0f8a249a blueswir1
        }
938 0f8a249a blueswir1
        break;
939 045380be blueswir1
    case 5: // Turbosparc ITLB Diagnostic
940 045380be blueswir1
    case 6: // Turbosparc DTLB Diagnostic
941 045380be blueswir1
    case 7: // Turbosparc IOTLB Diagnostic
942 045380be blueswir1
        break;
943 6c36d3fa blueswir1
    case 9: /* Supervisor code access */
944 6c36d3fa blueswir1
        switch(size) {
945 6c36d3fa blueswir1
        case 1:
946 1a2fb1c0 blueswir1
            ret = ldub_code(addr);
947 6c36d3fa blueswir1
            break;
948 6c36d3fa blueswir1
        case 2:
949 a4e7dd52 blueswir1
            ret = lduw_code(addr);
950 6c36d3fa blueswir1
            break;
951 6c36d3fa blueswir1
        default:
952 6c36d3fa blueswir1
        case 4:
953 a4e7dd52 blueswir1
            ret = ldl_code(addr);
954 6c36d3fa blueswir1
            break;
955 6c36d3fa blueswir1
        case 8:
956 a4e7dd52 blueswir1
            ret = ldq_code(addr);
957 6c36d3fa blueswir1
            break;
958 6c36d3fa blueswir1
        }
959 6c36d3fa blueswir1
        break;
960 81ad8ba2 blueswir1
    case 0xa: /* User data access */
961 81ad8ba2 blueswir1
        switch(size) {
962 81ad8ba2 blueswir1
        case 1:
963 1a2fb1c0 blueswir1
            ret = ldub_user(addr);
964 81ad8ba2 blueswir1
            break;
965 81ad8ba2 blueswir1
        case 2:
966 a4e7dd52 blueswir1
            ret = lduw_user(addr);
967 81ad8ba2 blueswir1
            break;
968 81ad8ba2 blueswir1
        default:
969 81ad8ba2 blueswir1
        case 4:
970 a4e7dd52 blueswir1
            ret = ldl_user(addr);
971 81ad8ba2 blueswir1
            break;
972 81ad8ba2 blueswir1
        case 8:
973 a4e7dd52 blueswir1
            ret = ldq_user(addr);
974 81ad8ba2 blueswir1
            break;
975 81ad8ba2 blueswir1
        }
976 81ad8ba2 blueswir1
        break;
977 81ad8ba2 blueswir1
    case 0xb: /* Supervisor data access */
978 81ad8ba2 blueswir1
        switch(size) {
979 81ad8ba2 blueswir1
        case 1:
980 1a2fb1c0 blueswir1
            ret = ldub_kernel(addr);
981 81ad8ba2 blueswir1
            break;
982 81ad8ba2 blueswir1
        case 2:
983 a4e7dd52 blueswir1
            ret = lduw_kernel(addr);
984 81ad8ba2 blueswir1
            break;
985 81ad8ba2 blueswir1
        default:
986 81ad8ba2 blueswir1
        case 4:
987 a4e7dd52 blueswir1
            ret = ldl_kernel(addr);
988 81ad8ba2 blueswir1
            break;
989 81ad8ba2 blueswir1
        case 8:
990 a4e7dd52 blueswir1
            ret = ldq_kernel(addr);
991 81ad8ba2 blueswir1
            break;
992 81ad8ba2 blueswir1
        }
993 81ad8ba2 blueswir1
        break;
994 6c36d3fa blueswir1
    case 0xc: /* I-cache tag */
995 6c36d3fa blueswir1
    case 0xd: /* I-cache data */
996 6c36d3fa blueswir1
    case 0xe: /* D-cache tag */
997 6c36d3fa blueswir1
    case 0xf: /* D-cache data */
998 6c36d3fa blueswir1
        break;
999 6c36d3fa blueswir1
    case 0x20: /* MMU passthrough */
1000 02aab46a bellard
        switch(size) {
1001 02aab46a bellard
        case 1:
1002 1a2fb1c0 blueswir1
            ret = ldub_phys(addr);
1003 02aab46a bellard
            break;
1004 02aab46a bellard
        case 2:
1005 a4e7dd52 blueswir1
            ret = lduw_phys(addr);
1006 02aab46a bellard
            break;
1007 02aab46a bellard
        default:
1008 02aab46a bellard
        case 4:
1009 a4e7dd52 blueswir1
            ret = ldl_phys(addr);
1010 02aab46a bellard
            break;
1011 9e61bde5 bellard
        case 8:
1012 a4e7dd52 blueswir1
            ret = ldq_phys(addr);
1013 0f8a249a blueswir1
            break;
1014 02aab46a bellard
        }
1015 0f8a249a blueswir1
        break;
1016 7d85892b blueswir1
    case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1017 5dcb6b91 blueswir1
        switch(size) {
1018 5dcb6b91 blueswir1
        case 1:
1019 1a2fb1c0 blueswir1
            ret = ldub_phys((target_phys_addr_t)addr
1020 5dcb6b91 blueswir1
                            | ((target_phys_addr_t)(asi & 0xf) << 32));
1021 5dcb6b91 blueswir1
            break;
1022 5dcb6b91 blueswir1
        case 2:
1023 a4e7dd52 blueswir1
            ret = lduw_phys((target_phys_addr_t)addr
1024 5dcb6b91 blueswir1
                            | ((target_phys_addr_t)(asi & 0xf) << 32));
1025 5dcb6b91 blueswir1
            break;
1026 5dcb6b91 blueswir1
        default:
1027 5dcb6b91 blueswir1
        case 4:
1028 a4e7dd52 blueswir1
            ret = ldl_phys((target_phys_addr_t)addr
1029 5dcb6b91 blueswir1
                           | ((target_phys_addr_t)(asi & 0xf) << 32));
1030 5dcb6b91 blueswir1
            break;
1031 5dcb6b91 blueswir1
        case 8:
1032 a4e7dd52 blueswir1
            ret = ldq_phys((target_phys_addr_t)addr
1033 5dcb6b91 blueswir1
                           | ((target_phys_addr_t)(asi & 0xf) << 32));
1034 0f8a249a blueswir1
            break;
1035 5dcb6b91 blueswir1
        }
1036 0f8a249a blueswir1
        break;
1037 045380be blueswir1
    case 0x30: // Turbosparc secondary cache diagnostic
1038 045380be blueswir1
    case 0x31: // Turbosparc RAM snoop
1039 045380be blueswir1
    case 0x32: // Turbosparc page table descriptor diagnostic
1040 666c87aa blueswir1
    case 0x39: /* data cache diagnostic register */
1041 666c87aa blueswir1
        ret = 0;
1042 666c87aa blueswir1
        break;
1043 045380be blueswir1
    case 8: /* User code access, XXX */
1044 e8af50a3 bellard
    default:
1045 1a2fb1c0 blueswir1
        do_unassigned_access(addr, 0, 0, asi);
1046 0f8a249a blueswir1
        ret = 0;
1047 0f8a249a blueswir1
        break;
1048 e8af50a3 bellard
    }
1049 81ad8ba2 blueswir1
    if (sign) {
1050 81ad8ba2 blueswir1
        switch(size) {
1051 81ad8ba2 blueswir1
        case 1:
1052 1a2fb1c0 blueswir1
            ret = (int8_t) ret;
1053 e32664fb blueswir1
            break;
1054 81ad8ba2 blueswir1
        case 2:
1055 1a2fb1c0 blueswir1
            ret = (int16_t) ret;
1056 1a2fb1c0 blueswir1
            break;
1057 1a2fb1c0 blueswir1
        case 4:
1058 1a2fb1c0 blueswir1
            ret = (int32_t) ret;
1059 e32664fb blueswir1
            break;
1060 81ad8ba2 blueswir1
        default:
1061 81ad8ba2 blueswir1
            break;
1062 81ad8ba2 blueswir1
        }
1063 81ad8ba2 blueswir1
    }
1064 8543e2cf blueswir1
#ifdef DEBUG_ASI
1065 1a2fb1c0 blueswir1
    dump_asi("read ", last_addr, asi, size, ret);
1066 8543e2cf blueswir1
#endif
1067 1a2fb1c0 blueswir1
    return ret;
1068 e8af50a3 bellard
}
1069 e8af50a3 bellard
1070 1a2fb1c0 blueswir1
void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1071 e8af50a3 bellard
{
1072 c2bc0e38 blueswir1
    helper_check_align(addr, size - 1);
1073 e8af50a3 bellard
    switch(asi) {
1074 6c36d3fa blueswir1
    case 2: /* SuperSparc MXCC registers */
1075 1a2fb1c0 blueswir1
        switch (addr) {
1076 952a328f blueswir1
        case 0x01c00000: /* MXCC stream data register 0 */
1077 952a328f blueswir1
            if (size == 8)
1078 1a2fb1c0 blueswir1
                env->mxccdata[0] = val;
1079 952a328f blueswir1
            else
1080 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1081 77f193da blueswir1
                             size);
1082 952a328f blueswir1
            break;
1083 952a328f blueswir1
        case 0x01c00008: /* MXCC stream data register 1 */
1084 952a328f blueswir1
            if (size == 8)
1085 1a2fb1c0 blueswir1
                env->mxccdata[1] = val;
1086 952a328f blueswir1
            else
1087 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1088 77f193da blueswir1
                             size);
1089 952a328f blueswir1
            break;
1090 952a328f blueswir1
        case 0x01c00010: /* MXCC stream data register 2 */
1091 952a328f blueswir1
            if (size == 8)
1092 1a2fb1c0 blueswir1
                env->mxccdata[2] = val;
1093 952a328f blueswir1
            else
1094 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1095 77f193da blueswir1
                             size);
1096 952a328f blueswir1
            break;
1097 952a328f blueswir1
        case 0x01c00018: /* MXCC stream data register 3 */
1098 952a328f blueswir1
            if (size == 8)
1099 1a2fb1c0 blueswir1
                env->mxccdata[3] = val;
1100 952a328f blueswir1
            else
1101 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1102 77f193da blueswir1
                             size);
1103 952a328f blueswir1
            break;
1104 952a328f blueswir1
        case 0x01c00100: /* MXCC stream source */
1105 952a328f blueswir1
            if (size == 8)
1106 1a2fb1c0 blueswir1
                env->mxccregs[0] = val;
1107 952a328f blueswir1
            else
1108 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1109 77f193da blueswir1
                             size);
1110 77f193da blueswir1
            env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1111 77f193da blueswir1
                                        0);
1112 77f193da blueswir1
            env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1113 77f193da blueswir1
                                        8);
1114 77f193da blueswir1
            env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1115 77f193da blueswir1
                                        16);
1116 77f193da blueswir1
            env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1117 77f193da blueswir1
                                        24);
1118 952a328f blueswir1
            break;
1119 952a328f blueswir1
        case 0x01c00200: /* MXCC stream destination */
1120 952a328f blueswir1
            if (size == 8)
1121 1a2fb1c0 blueswir1
                env->mxccregs[1] = val;
1122 952a328f blueswir1
            else
1123 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1124 77f193da blueswir1
                             size);
1125 77f193da blueswir1
            stq_phys((env->mxccregs[1] & 0xffffffffULL) +  0,
1126 77f193da blueswir1
                     env->mxccdata[0]);
1127 77f193da blueswir1
            stq_phys((env->mxccregs[1] & 0xffffffffULL) +  8,
1128 77f193da blueswir1
                     env->mxccdata[1]);
1129 77f193da blueswir1
            stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1130 77f193da blueswir1
                     env->mxccdata[2]);
1131 77f193da blueswir1
            stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1132 77f193da blueswir1
                     env->mxccdata[3]);
1133 952a328f blueswir1
            break;
1134 952a328f blueswir1
        case 0x01c00a00: /* MXCC control register */
1135 952a328f blueswir1
            if (size == 8)
1136 1a2fb1c0 blueswir1
                env->mxccregs[3] = val;
1137 952a328f blueswir1
            else
1138 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1139 77f193da blueswir1
                             size);
1140 952a328f blueswir1
            break;
1141 952a328f blueswir1
        case 0x01c00a04: /* MXCC control register */
1142 952a328f blueswir1
            if (size == 4)
1143 77f193da blueswir1
                env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL)
1144 77f193da blueswir1
                    | val;
1145 952a328f blueswir1
            else
1146 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1147 77f193da blueswir1
                             size);
1148 952a328f blueswir1
            break;
1149 952a328f blueswir1
        case 0x01c00e00: /* MXCC error register  */
1150 bbf7d96b blueswir1
            // writing a 1 bit clears the error
1151 952a328f blueswir1
            if (size == 8)
1152 1a2fb1c0 blueswir1
                env->mxccregs[6] &= ~val;
1153 952a328f blueswir1
            else
1154 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1155 77f193da blueswir1
                             size);
1156 952a328f blueswir1
            break;
1157 952a328f blueswir1
        case 0x01c00f00: /* MBus port address register */
1158 952a328f blueswir1
            if (size == 8)
1159 1a2fb1c0 blueswir1
                env->mxccregs[7] = val;
1160 952a328f blueswir1
            else
1161 77f193da blueswir1
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1162 77f193da blueswir1
                             size);
1163 952a328f blueswir1
            break;
1164 952a328f blueswir1
        default:
1165 77f193da blueswir1
            DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1166 77f193da blueswir1
                         size);
1167 952a328f blueswir1
            break;
1168 952a328f blueswir1
        }
1169 77f193da blueswir1
        DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi,
1170 77f193da blueswir1
                     size, addr, val);
1171 952a328f blueswir1
#ifdef DEBUG_MXCC
1172 952a328f blueswir1
        dump_mxcc(env);
1173 952a328f blueswir1
#endif
1174 6c36d3fa blueswir1
        break;
1175 e8af50a3 bellard
    case 3: /* MMU flush */
1176 0f8a249a blueswir1
        {
1177 0f8a249a blueswir1
            int mmulev;
1178 e80cfcfc bellard
1179 1a2fb1c0 blueswir1
            mmulev = (addr >> 8) & 15;
1180 952a328f blueswir1
            DPRINTF_MMU("mmu flush level %d\n", mmulev);
1181 0f8a249a blueswir1
            switch (mmulev) {
1182 0f8a249a blueswir1
            case 0: // flush page
1183 1a2fb1c0 blueswir1
                tlb_flush_page(env, addr & 0xfffff000);
1184 0f8a249a blueswir1
                break;
1185 0f8a249a blueswir1
            case 1: // flush segment (256k)
1186 0f8a249a blueswir1
            case 2: // flush region (16M)
1187 0f8a249a blueswir1
            case 3: // flush context (4G)
1188 0f8a249a blueswir1
            case 4: // flush entire
1189 0f8a249a blueswir1
                tlb_flush(env, 1);
1190 0f8a249a blueswir1
                break;
1191 0f8a249a blueswir1
            default:
1192 0f8a249a blueswir1
                break;
1193 0f8a249a blueswir1
            }
1194 55754d9e bellard
#ifdef DEBUG_MMU
1195 0f8a249a blueswir1
            dump_mmu(env);
1196 55754d9e bellard
#endif
1197 0f8a249a blueswir1
        }
1198 8543e2cf blueswir1
        break;
1199 e8af50a3 bellard
    case 4: /* write MMU regs */
1200 0f8a249a blueswir1
        {
1201 1a2fb1c0 blueswir1
            int reg = (addr >> 8) & 0x1f;
1202 0f8a249a blueswir1
            uint32_t oldreg;
1203 3b46e624 ths
1204 0f8a249a blueswir1
            oldreg = env->mmuregs[reg];
1205 55754d9e bellard
            switch(reg) {
1206 3deaeab7 blueswir1
            case 0: // Control Register
1207 3dd9a152 blueswir1
                env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1208 1a2fb1c0 blueswir1
                                    (val & 0x00ffffff);
1209 0f8a249a blueswir1
                // Mappings generated during no-fault mode or MMU
1210 0f8a249a blueswir1
                // disabled mode are invalid in normal mode
1211 5578ceab blueswir1
                if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1212 5578ceab blueswir1
                    (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
1213 55754d9e bellard
                    tlb_flush(env, 1);
1214 55754d9e bellard
                break;
1215 3deaeab7 blueswir1
            case 1: // Context Table Pointer Register
1216 5578ceab blueswir1
                env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
1217 3deaeab7 blueswir1
                break;
1218 3deaeab7 blueswir1
            case 2: // Context Register
1219 5578ceab blueswir1
                env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
1220 55754d9e bellard
                if (oldreg != env->mmuregs[reg]) {
1221 55754d9e bellard
                    /* we flush when the MMU context changes because
1222 55754d9e bellard
                       QEMU has no MMU context support */
1223 55754d9e bellard
                    tlb_flush(env, 1);
1224 55754d9e bellard
                }
1225 55754d9e bellard
                break;
1226 3deaeab7 blueswir1
            case 3: // Synchronous Fault Status Register with Clear
1227 3deaeab7 blueswir1
            case 4: // Synchronous Fault Address Register
1228 3deaeab7 blueswir1
                break;
1229 3deaeab7 blueswir1
            case 0x10: // TLB Replacement Control Register
1230 5578ceab blueswir1
                env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
1231 55754d9e bellard
                break;
1232 3deaeab7 blueswir1
            case 0x13: // Synchronous Fault Status Register with Read and Clear
1233 5578ceab blueswir1
                env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
1234 3dd9a152 blueswir1
                break;
1235 3deaeab7 blueswir1
            case 0x14: // Synchronous Fault Address Register
1236 1a2fb1c0 blueswir1
                env->mmuregs[4] = val;
1237 3dd9a152 blueswir1
                break;
1238 55754d9e bellard
            default:
1239 1a2fb1c0 blueswir1
                env->mmuregs[reg] = val;
1240 55754d9e bellard
                break;
1241 55754d9e bellard
            }
1242 55754d9e bellard
            if (oldreg != env->mmuregs[reg]) {
1243 77f193da blueswir1
                DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1244 77f193da blueswir1
                            reg, oldreg, env->mmuregs[reg]);
1245 55754d9e bellard
            }
1246 952a328f blueswir1
#ifdef DEBUG_MMU
1247 0f8a249a blueswir1
            dump_mmu(env);
1248 55754d9e bellard
#endif
1249 0f8a249a blueswir1
        }
1250 8543e2cf blueswir1
        break;
1251 045380be blueswir1
    case 5: // Turbosparc ITLB Diagnostic
1252 045380be blueswir1
    case 6: // Turbosparc DTLB Diagnostic
1253 045380be blueswir1
    case 7: // Turbosparc IOTLB Diagnostic
1254 045380be blueswir1
        break;
1255 81ad8ba2 blueswir1
    case 0xa: /* User data access */
1256 81ad8ba2 blueswir1
        switch(size) {
1257 81ad8ba2 blueswir1
        case 1:
1258 1a2fb1c0 blueswir1
            stb_user(addr, val);
1259 81ad8ba2 blueswir1
            break;
1260 81ad8ba2 blueswir1
        case 2:
1261 a4e7dd52 blueswir1
            stw_user(addr, val);
1262 81ad8ba2 blueswir1
            break;
1263 81ad8ba2 blueswir1
        default:
1264 81ad8ba2 blueswir1
        case 4:
1265 a4e7dd52 blueswir1
            stl_user(addr, val);
1266 81ad8ba2 blueswir1
            break;
1267 81ad8ba2 blueswir1
        case 8:
1268 a4e7dd52 blueswir1
            stq_user(addr, val);
1269 81ad8ba2 blueswir1
            break;
1270 81ad8ba2 blueswir1
        }
1271 81ad8ba2 blueswir1
        break;
1272 81ad8ba2 blueswir1
    case 0xb: /* Supervisor data access */
1273 81ad8ba2 blueswir1
        switch(size) {
1274 81ad8ba2 blueswir1
        case 1:
1275 1a2fb1c0 blueswir1
            stb_kernel(addr, val);
1276 81ad8ba2 blueswir1
            break;
1277 81ad8ba2 blueswir1
        case 2:
1278 a4e7dd52 blueswir1
            stw_kernel(addr, val);
1279 81ad8ba2 blueswir1
            break;
1280 81ad8ba2 blueswir1
        default:
1281 81ad8ba2 blueswir1
        case 4:
1282 a4e7dd52 blueswir1
            stl_kernel(addr, val);
1283 81ad8ba2 blueswir1
            break;
1284 81ad8ba2 blueswir1
        case 8:
1285 a4e7dd52 blueswir1
            stq_kernel(addr, val);
1286 81ad8ba2 blueswir1
            break;
1287 81ad8ba2 blueswir1
        }
1288 81ad8ba2 blueswir1
        break;
1289 6c36d3fa blueswir1
    case 0xc: /* I-cache tag */
1290 6c36d3fa blueswir1
    case 0xd: /* I-cache data */
1291 6c36d3fa blueswir1
    case 0xe: /* D-cache tag */
1292 6c36d3fa blueswir1
    case 0xf: /* D-cache data */
1293 6c36d3fa blueswir1
    case 0x10: /* I/D-cache flush page */
1294 6c36d3fa blueswir1
    case 0x11: /* I/D-cache flush segment */
1295 6c36d3fa blueswir1
    case 0x12: /* I/D-cache flush region */
1296 6c36d3fa blueswir1
    case 0x13: /* I/D-cache flush context */
1297 6c36d3fa blueswir1
    case 0x14: /* I/D-cache flush user */
1298 6c36d3fa blueswir1
        break;
1299 e80cfcfc bellard
    case 0x17: /* Block copy, sta access */
1300 0f8a249a blueswir1
        {
1301 1a2fb1c0 blueswir1
            // val = src
1302 1a2fb1c0 blueswir1
            // addr = dst
1303 0f8a249a blueswir1
            // copy 32 bytes
1304 6c36d3fa blueswir1
            unsigned int i;
1305 1a2fb1c0 blueswir1
            uint32_t src = val & ~3, dst = addr & ~3, temp;
1306 3b46e624 ths
1307 6c36d3fa blueswir1
            for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1308 6c36d3fa blueswir1
                temp = ldl_kernel(src);
1309 6c36d3fa blueswir1
                stl_kernel(dst, temp);
1310 6c36d3fa blueswir1
            }
1311 0f8a249a blueswir1
        }
1312 8543e2cf blueswir1
        break;
1313 e80cfcfc bellard
    case 0x1f: /* Block fill, stda access */
1314 0f8a249a blueswir1
        {
1315 1a2fb1c0 blueswir1
            // addr = dst
1316 1a2fb1c0 blueswir1
            // fill 32 bytes with val
1317 6c36d3fa blueswir1
            unsigned int i;
1318 1a2fb1c0 blueswir1
            uint32_t dst = addr & 7;
1319 6c36d3fa blueswir1
1320 6c36d3fa blueswir1
            for (i = 0; i < 32; i += 8, dst += 8)
1321 6c36d3fa blueswir1
                stq_kernel(dst, val);
1322 0f8a249a blueswir1
        }
1323 8543e2cf blueswir1
        break;
1324 6c36d3fa blueswir1
    case 0x20: /* MMU passthrough */
1325 0f8a249a blueswir1
        {
1326 02aab46a bellard
            switch(size) {
1327 02aab46a bellard
            case 1:
1328 1a2fb1c0 blueswir1
                stb_phys(addr, val);
1329 02aab46a bellard
                break;
1330 02aab46a bellard
            case 2:
1331 a4e7dd52 blueswir1
                stw_phys(addr, val);
1332 02aab46a bellard
                break;
1333 02aab46a bellard
            case 4:
1334 02aab46a bellard
            default:
1335 a4e7dd52 blueswir1
                stl_phys(addr, val);
1336 02aab46a bellard
                break;
1337 9e61bde5 bellard
            case 8:
1338 a4e7dd52 blueswir1
                stq_phys(addr, val);
1339 9e61bde5 bellard
                break;
1340 02aab46a bellard
            }
1341 0f8a249a blueswir1
        }
1342 8543e2cf blueswir1
        break;
1343 045380be blueswir1
    case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1344 0f8a249a blueswir1
        {
1345 5dcb6b91 blueswir1
            switch(size) {
1346 5dcb6b91 blueswir1
            case 1:
1347 1a2fb1c0 blueswir1
                stb_phys((target_phys_addr_t)addr
1348 1a2fb1c0 blueswir1
                         | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1349 5dcb6b91 blueswir1
                break;
1350 5dcb6b91 blueswir1
            case 2:
1351 a4e7dd52 blueswir1
                stw_phys((target_phys_addr_t)addr
1352 1a2fb1c0 blueswir1
                         | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1353 5dcb6b91 blueswir1
                break;
1354 5dcb6b91 blueswir1
            case 4:
1355 5dcb6b91 blueswir1
            default:
1356 a4e7dd52 blueswir1
                stl_phys((target_phys_addr_t)addr
1357 1a2fb1c0 blueswir1
                         | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1358 5dcb6b91 blueswir1
                break;
1359 5dcb6b91 blueswir1
            case 8:
1360 a4e7dd52 blueswir1
                stq_phys((target_phys_addr_t)addr
1361 1a2fb1c0 blueswir1
                         | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1362 5dcb6b91 blueswir1
                break;
1363 5dcb6b91 blueswir1
            }
1364 0f8a249a blueswir1
        }
1365 8543e2cf blueswir1
        break;
1366 045380be blueswir1
    case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1367 045380be blueswir1
    case 0x31: // store buffer data, Ross RT620 I-cache flush or
1368 045380be blueswir1
               // Turbosparc snoop RAM
1369 77f193da blueswir1
    case 0x32: // store buffer control or Turbosparc page table
1370 77f193da blueswir1
               // descriptor diagnostic
1371 6c36d3fa blueswir1
    case 0x36: /* I-cache flash clear */
1372 6c36d3fa blueswir1
    case 0x37: /* D-cache flash clear */
1373 666c87aa blueswir1
    case 0x38: /* breakpoint diagnostics */
1374 666c87aa blueswir1
    case 0x4c: /* breakpoint action */
1375 6c36d3fa blueswir1
        break;
1376 045380be blueswir1
    case 8: /* User code access, XXX */
1377 6c36d3fa blueswir1
    case 9: /* Supervisor code access, XXX */
1378 e8af50a3 bellard
    default:
1379 1a2fb1c0 blueswir1
        do_unassigned_access(addr, 1, 0, asi);
1380 8543e2cf blueswir1
        break;
1381 e8af50a3 bellard
    }
1382 8543e2cf blueswir1
#ifdef DEBUG_ASI
1383 1a2fb1c0 blueswir1
    dump_asi("write", addr, asi, size, val);
1384 8543e2cf blueswir1
#endif
1385 e8af50a3 bellard
}
1386 e8af50a3 bellard
1387 81ad8ba2 blueswir1
#endif /* CONFIG_USER_ONLY */
1388 81ad8ba2 blueswir1
#else /* TARGET_SPARC64 */
1389 81ad8ba2 blueswir1
1390 81ad8ba2 blueswir1
#ifdef CONFIG_USER_ONLY
1391 1a2fb1c0 blueswir1
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1392 81ad8ba2 blueswir1
{
1393 81ad8ba2 blueswir1
    uint64_t ret = 0;
1394 1a2fb1c0 blueswir1
#if defined(DEBUG_ASI)
1395 1a2fb1c0 blueswir1
    target_ulong last_addr = addr;
1396 1a2fb1c0 blueswir1
#endif
1397 81ad8ba2 blueswir1
1398 81ad8ba2 blueswir1
    if (asi < 0x80)
1399 81ad8ba2 blueswir1
        raise_exception(TT_PRIV_ACT);
1400 81ad8ba2 blueswir1
1401 c2bc0e38 blueswir1
    helper_check_align(addr, size - 1);
1402 2cade6a3 blueswir1
    address_mask(env, &addr);
1403 c2bc0e38 blueswir1
1404 81ad8ba2 blueswir1
    switch (asi) {
1405 81ad8ba2 blueswir1
    case 0x82: // Primary no-fault
1406 81ad8ba2 blueswir1
    case 0x8a: // Primary no-fault LE
1407 e83ce550 blueswir1
        if (page_check_range(addr, size, PAGE_READ) == -1) {
1408 e83ce550 blueswir1
#ifdef DEBUG_ASI
1409 e83ce550 blueswir1
            dump_asi("read ", last_addr, asi, size, ret);
1410 e83ce550 blueswir1
#endif
1411 e83ce550 blueswir1
            return 0;
1412 e83ce550 blueswir1
        }
1413 e83ce550 blueswir1
        // Fall through
1414 e83ce550 blueswir1
    case 0x80: // Primary
1415 e83ce550 blueswir1
    case 0x88: // Primary LE
1416 81ad8ba2 blueswir1
        {
1417 81ad8ba2 blueswir1
            switch(size) {
1418 81ad8ba2 blueswir1
            case 1:
1419 1a2fb1c0 blueswir1
                ret = ldub_raw(addr);
1420 81ad8ba2 blueswir1
                break;
1421 81ad8ba2 blueswir1
            case 2:
1422 a4e7dd52 blueswir1
                ret = lduw_raw(addr);
1423 81ad8ba2 blueswir1
                break;
1424 81ad8ba2 blueswir1
            case 4:
1425 a4e7dd52 blueswir1
                ret = ldl_raw(addr);
1426 81ad8ba2 blueswir1
                break;
1427 81ad8ba2 blueswir1
            default:
1428 81ad8ba2 blueswir1
            case 8:
1429 a4e7dd52 blueswir1
                ret = ldq_raw(addr);
1430 81ad8ba2 blueswir1
                break;
1431 81ad8ba2 blueswir1
            }
1432 81ad8ba2 blueswir1
        }
1433 81ad8ba2 blueswir1
        break;
1434 81ad8ba2 blueswir1
    case 0x83: // Secondary no-fault
1435 81ad8ba2 blueswir1
    case 0x8b: // Secondary no-fault LE
1436 e83ce550 blueswir1
        if (page_check_range(addr, size, PAGE_READ) == -1) {
1437 e83ce550 blueswir1
#ifdef DEBUG_ASI
1438 e83ce550 blueswir1
            dump_asi("read ", last_addr, asi, size, ret);
1439 e83ce550 blueswir1
#endif
1440 e83ce550 blueswir1
            return 0;
1441 e83ce550 blueswir1
        }
1442 e83ce550 blueswir1
        // Fall through
1443 e83ce550 blueswir1
    case 0x81: // Secondary
1444 e83ce550 blueswir1
    case 0x89: // Secondary LE
1445 81ad8ba2 blueswir1
        // XXX
1446 81ad8ba2 blueswir1
        break;
1447 81ad8ba2 blueswir1
    default:
1448 81ad8ba2 blueswir1
        break;
1449 81ad8ba2 blueswir1
    }
1450 81ad8ba2 blueswir1
1451 81ad8ba2 blueswir1
    /* Convert from little endian */
1452 81ad8ba2 blueswir1
    switch (asi) {
1453 81ad8ba2 blueswir1
    case 0x88: // Primary LE
1454 81ad8ba2 blueswir1
    case 0x89: // Secondary LE
1455 81ad8ba2 blueswir1
    case 0x8a: // Primary no-fault LE
1456 81ad8ba2 blueswir1
    case 0x8b: // Secondary no-fault LE
1457 81ad8ba2 blueswir1
        switch(size) {
1458 81ad8ba2 blueswir1
        case 2:
1459 81ad8ba2 blueswir1
            ret = bswap16(ret);
1460 e32664fb blueswir1
            break;
1461 81ad8ba2 blueswir1
        case 4:
1462 81ad8ba2 blueswir1
            ret = bswap32(ret);
1463 e32664fb blueswir1
            break;
1464 81ad8ba2 blueswir1
        case 8:
1465 81ad8ba2 blueswir1
            ret = bswap64(ret);
1466 e32664fb blueswir1
            break;
1467 81ad8ba2 blueswir1
        default:
1468 81ad8ba2 blueswir1
            break;
1469 81ad8ba2 blueswir1
        }
1470 81ad8ba2 blueswir1
    default:
1471 81ad8ba2 blueswir1
        break;
1472 81ad8ba2 blueswir1
    }
1473 81ad8ba2 blueswir1
1474 81ad8ba2 blueswir1
    /* Convert to signed number */
1475 81ad8ba2 blueswir1
    if (sign) {
1476 81ad8ba2 blueswir1
        switch(size) {
1477 81ad8ba2 blueswir1
        case 1:
1478 81ad8ba2 blueswir1
            ret = (int8_t) ret;
1479 e32664fb blueswir1
            break;
1480 81ad8ba2 blueswir1
        case 2:
1481 81ad8ba2 blueswir1
            ret = (int16_t) ret;
1482 e32664fb blueswir1
            break;
1483 81ad8ba2 blueswir1
        case 4:
1484 81ad8ba2 blueswir1
            ret = (int32_t) ret;
1485 e32664fb blueswir1
            break;
1486 81ad8ba2 blueswir1
        default:
1487 81ad8ba2 blueswir1
            break;
1488 81ad8ba2 blueswir1
        }
1489 81ad8ba2 blueswir1
    }
1490 1a2fb1c0 blueswir1
#ifdef DEBUG_ASI
1491 1a2fb1c0 blueswir1
    dump_asi("read ", last_addr, asi, size, ret);
1492 1a2fb1c0 blueswir1
#endif
1493 1a2fb1c0 blueswir1
    return ret;
1494 81ad8ba2 blueswir1
}
1495 81ad8ba2 blueswir1
1496 1a2fb1c0 blueswir1
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1497 81ad8ba2 blueswir1
{
1498 1a2fb1c0 blueswir1
#ifdef DEBUG_ASI
1499 1a2fb1c0 blueswir1
    dump_asi("write", addr, asi, size, val);
1500 1a2fb1c0 blueswir1
#endif
1501 81ad8ba2 blueswir1
    if (asi < 0x80)
1502 81ad8ba2 blueswir1
        raise_exception(TT_PRIV_ACT);
1503 81ad8ba2 blueswir1
1504 c2bc0e38 blueswir1
    helper_check_align(addr, size - 1);
1505 2cade6a3 blueswir1
    address_mask(env, &addr);
1506 c2bc0e38 blueswir1
1507 81ad8ba2 blueswir1
    /* Convert to little endian */
1508 81ad8ba2 blueswir1
    switch (asi) {
1509 81ad8ba2 blueswir1
    case 0x88: // Primary LE
1510 81ad8ba2 blueswir1
    case 0x89: // Secondary LE
1511 81ad8ba2 blueswir1
        switch(size) {
1512 81ad8ba2 blueswir1
        case 2:
1513 1a2fb1c0 blueswir1
            addr = bswap16(addr);
1514 e32664fb blueswir1
            break;
1515 81ad8ba2 blueswir1
        case 4:
1516 1a2fb1c0 blueswir1
            addr = bswap32(addr);
1517 e32664fb blueswir1
            break;
1518 81ad8ba2 blueswir1
        case 8:
1519 1a2fb1c0 blueswir1
            addr = bswap64(addr);
1520 e32664fb blueswir1
            break;
1521 81ad8ba2 blueswir1
        default:
1522 81ad8ba2 blueswir1
            break;
1523 81ad8ba2 blueswir1
        }
1524 81ad8ba2 blueswir1
    default:
1525 81ad8ba2 blueswir1
        break;
1526 81ad8ba2 blueswir1
    }
1527 81ad8ba2 blueswir1
1528 81ad8ba2 blueswir1
    switch(asi) {
1529 81ad8ba2 blueswir1
    case 0x80: // Primary
1530 81ad8ba2 blueswir1
    case 0x88: // Primary LE
1531 81ad8ba2 blueswir1
        {
1532 81ad8ba2 blueswir1
            switch(size) {
1533 81ad8ba2 blueswir1
            case 1:
1534 1a2fb1c0 blueswir1
                stb_raw(addr, val);
1535 81ad8ba2 blueswir1
                break;
1536 81ad8ba2 blueswir1
            case 2:
1537 a4e7dd52 blueswir1
                stw_raw(addr, val);
1538 81ad8ba2 blueswir1
                break;
1539 81ad8ba2 blueswir1
            case 4:
1540 a4e7dd52 blueswir1
                stl_raw(addr, val);
1541 81ad8ba2 blueswir1
                break;
1542 81ad8ba2 blueswir1
            case 8:
1543 81ad8ba2 blueswir1
            default:
1544 a4e7dd52 blueswir1
                stq_raw(addr, val);
1545 81ad8ba2 blueswir1
                break;
1546 81ad8ba2 blueswir1
            }
1547 81ad8ba2 blueswir1
        }
1548 81ad8ba2 blueswir1
        break;
1549 81ad8ba2 blueswir1
    case 0x81: // Secondary
1550 81ad8ba2 blueswir1
    case 0x89: // Secondary LE
1551 81ad8ba2 blueswir1
        // XXX
1552 81ad8ba2 blueswir1
        return;
1553 81ad8ba2 blueswir1
1554 81ad8ba2 blueswir1
    case 0x82: // Primary no-fault, RO
1555 81ad8ba2 blueswir1
    case 0x83: // Secondary no-fault, RO
1556 81ad8ba2 blueswir1
    case 0x8a: // Primary no-fault LE, RO
1557 81ad8ba2 blueswir1
    case 0x8b: // Secondary no-fault LE, RO
1558 81ad8ba2 blueswir1
    default:
1559 1a2fb1c0 blueswir1
        do_unassigned_access(addr, 1, 0, 1);
1560 81ad8ba2 blueswir1
        return;
1561 81ad8ba2 blueswir1
    }
1562 81ad8ba2 blueswir1
}
1563 81ad8ba2 blueswir1
1564 81ad8ba2 blueswir1
#else /* CONFIG_USER_ONLY */
1565 3475187d bellard
1566 1a2fb1c0 blueswir1
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1567 3475187d bellard
{
1568 83469015 bellard
    uint64_t ret = 0;
1569 1a2fb1c0 blueswir1
#if defined(DEBUG_ASI)
1570 1a2fb1c0 blueswir1
    target_ulong last_addr = addr;
1571 1a2fb1c0 blueswir1
#endif
1572 3475187d bellard
1573 6f27aba6 blueswir1
    if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1574 5578ceab blueswir1
        || ((env->def->features & CPU_FEATURE_HYPV)
1575 5578ceab blueswir1
            && asi >= 0x30 && asi < 0x80
1576 fb79ceb9 blueswir1
            && !(env->hpstate & HS_PRIV)))
1577 0f8a249a blueswir1
        raise_exception(TT_PRIV_ACT);
1578 3475187d bellard
1579 c2bc0e38 blueswir1
    helper_check_align(addr, size - 1);
1580 3475187d bellard
    switch (asi) {
1581 e83ce550 blueswir1
    case 0x82: // Primary no-fault
1582 e83ce550 blueswir1
    case 0x8a: // Primary no-fault LE
1583 e83ce550 blueswir1
        if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1584 e83ce550 blueswir1
#ifdef DEBUG_ASI
1585 e83ce550 blueswir1
            dump_asi("read ", last_addr, asi, size, ret);
1586 e83ce550 blueswir1
#endif
1587 e83ce550 blueswir1
            return 0;
1588 e83ce550 blueswir1
        }
1589 e83ce550 blueswir1
        // Fall through
1590 81ad8ba2 blueswir1
    case 0x10: // As if user primary
1591 81ad8ba2 blueswir1
    case 0x18: // As if user primary LE
1592 81ad8ba2 blueswir1
    case 0x80: // Primary
1593 81ad8ba2 blueswir1
    case 0x88: // Primary LE
1594 81ad8ba2 blueswir1
        if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1595 5578ceab blueswir1
            if ((env->def->features & CPU_FEATURE_HYPV)
1596 5578ceab blueswir1
                && env->hpstate & HS_PRIV) {
1597 6f27aba6 blueswir1
                switch(size) {
1598 6f27aba6 blueswir1
                case 1:
1599 1a2fb1c0 blueswir1
                    ret = ldub_hypv(addr);
1600 6f27aba6 blueswir1
                    break;
1601 6f27aba6 blueswir1
                case 2:
1602 a4e7dd52 blueswir1
                    ret = lduw_hypv(addr);
1603 6f27aba6 blueswir1
                    break;
1604 6f27aba6 blueswir1
                case 4:
1605 a4e7dd52 blueswir1
                    ret = ldl_hypv(addr);
1606 6f27aba6 blueswir1
                    break;
1607 6f27aba6 blueswir1
                default:
1608 6f27aba6 blueswir1
                case 8:
1609 a4e7dd52 blueswir1
                    ret = ldq_hypv(addr);
1610 6f27aba6 blueswir1
                    break;
1611 6f27aba6 blueswir1
                }
1612 6f27aba6 blueswir1
            } else {
1613 6f27aba6 blueswir1
                switch(size) {
1614 6f27aba6 blueswir1
                case 1:
1615 1a2fb1c0 blueswir1
                    ret = ldub_kernel(addr);
1616 6f27aba6 blueswir1
                    break;
1617 6f27aba6 blueswir1
                case 2:
1618 a4e7dd52 blueswir1
                    ret = lduw_kernel(addr);
1619 6f27aba6 blueswir1
                    break;
1620 6f27aba6 blueswir1
                case 4:
1621 a4e7dd52 blueswir1
                    ret = ldl_kernel(addr);
1622 6f27aba6 blueswir1
                    break;
1623 6f27aba6 blueswir1
                default:
1624 6f27aba6 blueswir1
                case 8:
1625 a4e7dd52 blueswir1
                    ret = ldq_kernel(addr);
1626 6f27aba6 blueswir1
                    break;
1627 6f27aba6 blueswir1
                }
1628 81ad8ba2 blueswir1
            }
1629 81ad8ba2 blueswir1
        } else {
1630 81ad8ba2 blueswir1
            switch(size) {
1631 81ad8ba2 blueswir1
            case 1:
1632 1a2fb1c0 blueswir1
                ret = ldub_user(addr);
1633 81ad8ba2 blueswir1
                break;
1634 81ad8ba2 blueswir1
            case 2:
1635 a4e7dd52 blueswir1
                ret = lduw_user(addr);
1636 81ad8ba2 blueswir1
                break;
1637 81ad8ba2 blueswir1
            case 4:
1638 a4e7dd52 blueswir1
                ret = ldl_user(addr);
1639 81ad8ba2 blueswir1
                break;
1640 81ad8ba2 blueswir1
            default:
1641 81ad8ba2 blueswir1
            case 8:
1642 a4e7dd52 blueswir1
                ret = ldq_user(addr);
1643 81ad8ba2 blueswir1
                break;
1644 81ad8ba2 blueswir1
            }
1645 81ad8ba2 blueswir1
        }
1646 81ad8ba2 blueswir1
        break;
1647 3475187d bellard
    case 0x14: // Bypass
1648 3475187d bellard
    case 0x15: // Bypass, non-cacheable
1649 81ad8ba2 blueswir1
    case 0x1c: // Bypass LE
1650 81ad8ba2 blueswir1
    case 0x1d: // Bypass, non-cacheable LE
1651 0f8a249a blueswir1
        {
1652 02aab46a bellard
            switch(size) {
1653 02aab46a bellard
            case 1:
1654 1a2fb1c0 blueswir1
                ret = ldub_phys(addr);
1655 02aab46a bellard
                break;
1656 02aab46a bellard
            case 2:
1657 a4e7dd52 blueswir1
                ret = lduw_phys(addr);
1658 02aab46a bellard
                break;
1659 02aab46a bellard
            case 4:
1660 a4e7dd52 blueswir1
                ret = ldl_phys(addr);
1661 02aab46a bellard
                break;
1662 02aab46a bellard
            default:
1663 02aab46a bellard
            case 8:
1664 a4e7dd52 blueswir1
                ret = ldq_phys(addr);
1665 02aab46a bellard
                break;
1666 02aab46a bellard
            }
1667 0f8a249a blueswir1
            break;
1668 0f8a249a blueswir1
        }
1669 db166940 blueswir1
    case 0x24: // Nucleus quad LDD 128 bit atomic
1670 db166940 blueswir1
    case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1671 db166940 blueswir1
        //  Only ldda allowed
1672 db166940 blueswir1
        raise_exception(TT_ILL_INSN);
1673 db166940 blueswir1
        return 0;
1674 e83ce550 blueswir1
    case 0x83: // Secondary no-fault
1675 e83ce550 blueswir1
    case 0x8b: // Secondary no-fault LE
1676 e83ce550 blueswir1
        if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1677 e83ce550 blueswir1
#ifdef DEBUG_ASI
1678 e83ce550 blueswir1
            dump_asi("read ", last_addr, asi, size, ret);
1679 e83ce550 blueswir1
#endif
1680 e83ce550 blueswir1
            return 0;
1681 e83ce550 blueswir1
        }
1682 e83ce550 blueswir1
        // Fall through
1683 83469015 bellard
    case 0x04: // Nucleus
1684 83469015 bellard
    case 0x0c: // Nucleus Little Endian (LE)
1685 83469015 bellard
    case 0x11: // As if user secondary
1686 83469015 bellard
    case 0x19: // As if user secondary LE
1687 83469015 bellard
    case 0x4a: // UPA config
1688 81ad8ba2 blueswir1
    case 0x81: // Secondary
1689 83469015 bellard
    case 0x89: // Secondary LE
1690 0f8a249a blueswir1
        // XXX
1691 0f8a249a blueswir1
        break;
1692 3475187d bellard
    case 0x45: // LSU
1693 0f8a249a blueswir1
        ret = env->lsu;
1694 0f8a249a blueswir1
        break;
1695 3475187d bellard
    case 0x50: // I-MMU regs
1696 0f8a249a blueswir1
        {
1697 1a2fb1c0 blueswir1
            int reg = (addr >> 3) & 0xf;
1698 3475187d bellard
1699 0f8a249a blueswir1
            ret = env->immuregs[reg];
1700 0f8a249a blueswir1
            break;
1701 0f8a249a blueswir1
        }
1702 3475187d bellard
    case 0x51: // I-MMU 8k TSB pointer
1703 3475187d bellard
    case 0x52: // I-MMU 64k TSB pointer
1704 0f8a249a blueswir1
        // XXX
1705 0f8a249a blueswir1
        break;
1706 a5a52cf2 blueswir1
    case 0x55: // I-MMU data access
1707 a5a52cf2 blueswir1
        {
1708 a5a52cf2 blueswir1
            int reg = (addr >> 3) & 0x3f;
1709 a5a52cf2 blueswir1
1710 a5a52cf2 blueswir1
            ret = env->itlb_tte[reg];
1711 a5a52cf2 blueswir1
            break;
1712 a5a52cf2 blueswir1
        }
1713 83469015 bellard
    case 0x56: // I-MMU tag read
1714 0f8a249a blueswir1
        {
1715 43e9e742 blueswir1
            int reg = (addr >> 3) & 0x3f;
1716 0f8a249a blueswir1
1717 43e9e742 blueswir1
            ret = env->itlb_tag[reg];
1718 0f8a249a blueswir1
            break;
1719 0f8a249a blueswir1
        }
1720 3475187d bellard
    case 0x58: // D-MMU regs
1721 0f8a249a blueswir1
        {
1722 1a2fb1c0 blueswir1
            int reg = (addr >> 3) & 0xf;
1723 3475187d bellard
1724 0f8a249a blueswir1
            ret = env->dmmuregs[reg];
1725 0f8a249a blueswir1
            break;
1726 0f8a249a blueswir1
        }
1727 a5a52cf2 blueswir1
    case 0x5d: // D-MMU data access
1728 a5a52cf2 blueswir1
        {
1729 a5a52cf2 blueswir1
            int reg = (addr >> 3) & 0x3f;
1730 a5a52cf2 blueswir1
1731 a5a52cf2 blueswir1
            ret = env->dtlb_tte[reg];
1732 a5a52cf2 blueswir1
            break;
1733 a5a52cf2 blueswir1
        }
1734 83469015 bellard
    case 0x5e: // D-MMU tag read
1735 0f8a249a blueswir1
        {
1736 43e9e742 blueswir1
            int reg = (addr >> 3) & 0x3f;
1737 0f8a249a blueswir1
1738 43e9e742 blueswir1
            ret = env->dtlb_tag[reg];
1739 0f8a249a blueswir1
            break;
1740 0f8a249a blueswir1
        }
1741 f7350b47 blueswir1
    case 0x46: // D-cache data
1742 f7350b47 blueswir1
    case 0x47: // D-cache tag access
1743 a5a52cf2 blueswir1
    case 0x4b: // E-cache error enable
1744 a5a52cf2 blueswir1
    case 0x4c: // E-cache asynchronous fault status
1745 a5a52cf2 blueswir1
    case 0x4d: // E-cache asynchronous fault address
1746 f7350b47 blueswir1
    case 0x4e: // E-cache tag data
1747 f7350b47 blueswir1
    case 0x66: // I-cache instruction access
1748 f7350b47 blueswir1
    case 0x67: // I-cache tag access
1749 f7350b47 blueswir1
    case 0x6e: // I-cache predecode
1750 f7350b47 blueswir1
    case 0x6f: // I-cache LRU etc.
1751 f7350b47 blueswir1
    case 0x76: // E-cache tag
1752 f7350b47 blueswir1
    case 0x7e: // E-cache tag
1753 f7350b47 blueswir1
        break;
1754 3475187d bellard
    case 0x59: // D-MMU 8k TSB pointer
1755 3475187d bellard
    case 0x5a: // D-MMU 64k TSB pointer
1756 3475187d bellard
    case 0x5b: // D-MMU data pointer
1757 83469015 bellard
    case 0x48: // Interrupt dispatch, RO
1758 83469015 bellard
    case 0x49: // Interrupt data receive
1759 83469015 bellard
    case 0x7f: // Incoming interrupt vector, RO
1760 0f8a249a blueswir1
        // XXX
1761 0f8a249a blueswir1
        break;
1762 3475187d bellard
    case 0x54: // I-MMU data in, WO
1763 3475187d bellard
    case 0x57: // I-MMU demap, WO
1764 3475187d bellard
    case 0x5c: // D-MMU data in, WO
1765 3475187d bellard
    case 0x5f: // D-MMU demap, WO
1766 83469015 bellard
    case 0x77: // Interrupt vector, WO
1767 3475187d bellard
    default:
1768 1a2fb1c0 blueswir1
        do_unassigned_access(addr, 0, 0, 1);
1769 0f8a249a blueswir1
        ret = 0;
1770 0f8a249a blueswir1
        break;
1771 3475187d bellard
    }
1772 81ad8ba2 blueswir1
1773 81ad8ba2 blueswir1
    /* Convert from little endian */
1774 81ad8ba2 blueswir1
    switch (asi) {
1775 81ad8ba2 blueswir1
    case 0x0c: // Nucleus Little Endian (LE)
1776 81ad8ba2 blueswir1
    case 0x18: // As if user primary LE
1777 81ad8ba2 blueswir1
    case 0x19: // As if user secondary LE
1778 81ad8ba2 blueswir1
    case 0x1c: // Bypass LE
1779 81ad8ba2 blueswir1
    case 0x1d: // Bypass, non-cacheable LE
1780 81ad8ba2 blueswir1
    case 0x88: // Primary LE
1781 81ad8ba2 blueswir1
    case 0x89: // Secondary LE
1782 81ad8ba2 blueswir1
    case 0x8a: // Primary no-fault LE
1783 81ad8ba2 blueswir1
    case 0x8b: // Secondary no-fault LE
1784 81ad8ba2 blueswir1
        switch(size) {
1785 81ad8ba2 blueswir1
        case 2:
1786 81ad8ba2 blueswir1
            ret = bswap16(ret);
1787 e32664fb blueswir1
            break;
1788 81ad8ba2 blueswir1
        case 4:
1789 81ad8ba2 blueswir1
            ret = bswap32(ret);
1790 e32664fb blueswir1
            break;
1791 81ad8ba2 blueswir1
        case 8:
1792 81ad8ba2 blueswir1
            ret = bswap64(ret);
1793 e32664fb blueswir1
            break;
1794 81ad8ba2 blueswir1
        default:
1795 81ad8ba2 blueswir1
            break;
1796 81ad8ba2 blueswir1
        }
1797 81ad8ba2 blueswir1
    default:
1798 81ad8ba2 blueswir1
        break;
1799 81ad8ba2 blueswir1
    }
1800 81ad8ba2 blueswir1
1801 81ad8ba2 blueswir1
    /* Convert to signed number */
1802 81ad8ba2 blueswir1
    if (sign) {
1803 81ad8ba2 blueswir1
        switch(size) {
1804 81ad8ba2 blueswir1
        case 1:
1805 81ad8ba2 blueswir1
            ret = (int8_t) ret;
1806 e32664fb blueswir1
            break;
1807 81ad8ba2 blueswir1
        case 2:
1808 81ad8ba2 blueswir1
            ret = (int16_t) ret;
1809 e32664fb blueswir1
            break;
1810 81ad8ba2 blueswir1
        case 4:
1811 81ad8ba2 blueswir1
            ret = (int32_t) ret;
1812 e32664fb blueswir1
            break;
1813 81ad8ba2 blueswir1
        default:
1814 81ad8ba2 blueswir1
            break;
1815 81ad8ba2 blueswir1
        }
1816 81ad8ba2 blueswir1
    }
1817 1a2fb1c0 blueswir1
#ifdef DEBUG_ASI
1818 1a2fb1c0 blueswir1
    dump_asi("read ", last_addr, asi, size, ret);
1819 1a2fb1c0 blueswir1
#endif
1820 1a2fb1c0 blueswir1
    return ret;
1821 3475187d bellard
}
1822 3475187d bellard
1823 1a2fb1c0 blueswir1
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1824 3475187d bellard
{
1825 1a2fb1c0 blueswir1
#ifdef DEBUG_ASI
1826 1a2fb1c0 blueswir1
    dump_asi("write", addr, asi, size, val);
1827 1a2fb1c0 blueswir1
#endif
1828 6f27aba6 blueswir1
    if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1829 5578ceab blueswir1
        || ((env->def->features & CPU_FEATURE_HYPV)
1830 5578ceab blueswir1
            && asi >= 0x30 && asi < 0x80
1831 fb79ceb9 blueswir1
            && !(env->hpstate & HS_PRIV)))
1832 0f8a249a blueswir1
        raise_exception(TT_PRIV_ACT);
1833 3475187d bellard
1834 c2bc0e38 blueswir1
    helper_check_align(addr, size - 1);
1835 81ad8ba2 blueswir1
    /* Convert to little endian */
1836 81ad8ba2 blueswir1
    switch (asi) {
1837 81ad8ba2 blueswir1
    case 0x0c: // Nucleus Little Endian (LE)
1838 81ad8ba2 blueswir1
    case 0x18: // As if user primary LE
1839 81ad8ba2 blueswir1
    case 0x19: // As if user secondary LE
1840 81ad8ba2 blueswir1
    case 0x1c: // Bypass LE
1841 81ad8ba2 blueswir1
    case 0x1d: // Bypass, non-cacheable LE
1842 81ad8ba2 blueswir1
    case 0x88: // Primary LE
1843 81ad8ba2 blueswir1
    case 0x89: // Secondary LE
1844 81ad8ba2 blueswir1
        switch(size) {
1845 81ad8ba2 blueswir1
        case 2:
1846 1a2fb1c0 blueswir1
            addr = bswap16(addr);
1847 e32664fb blueswir1
            break;
1848 81ad8ba2 blueswir1
        case 4:
1849 1a2fb1c0 blueswir1
            addr = bswap32(addr);
1850 e32664fb blueswir1
            break;
1851 81ad8ba2 blueswir1
        case 8:
1852 1a2fb1c0 blueswir1
            addr = bswap64(addr);
1853 e32664fb blueswir1
            break;
1854 81ad8ba2 blueswir1
        default:
1855 81ad8ba2 blueswir1
            break;
1856 81ad8ba2 blueswir1
        }
1857 81ad8ba2 blueswir1
    default:
1858 81ad8ba2 blueswir1
        break;
1859 81ad8ba2 blueswir1
    }
1860 81ad8ba2 blueswir1
1861 3475187d bellard
    switch(asi) {
1862 81ad8ba2 blueswir1
    case 0x10: // As if user primary
1863 81ad8ba2 blueswir1
    case 0x18: // As if user primary LE
1864 81ad8ba2 blueswir1
    case 0x80: // Primary
1865 81ad8ba2 blueswir1
    case 0x88: // Primary LE
1866 81ad8ba2 blueswir1
        if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1867 5578ceab blueswir1
            if ((env->def->features & CPU_FEATURE_HYPV)
1868 5578ceab blueswir1
                && env->hpstate & HS_PRIV) {
1869 6f27aba6 blueswir1
                switch(size) {
1870 6f27aba6 blueswir1
                case 1:
1871 1a2fb1c0 blueswir1
                    stb_hypv(addr, val);
1872 6f27aba6 blueswir1
                    break;
1873 6f27aba6 blueswir1
                case 2:
1874 a4e7dd52 blueswir1
                    stw_hypv(addr, val);
1875 6f27aba6 blueswir1
                    break;
1876 6f27aba6 blueswir1
                case 4:
1877 a4e7dd52 blueswir1
                    stl_hypv(addr, val);
1878 6f27aba6 blueswir1
                    break;
1879 6f27aba6 blueswir1
                case 8:
1880 6f27aba6 blueswir1
                default:
1881 a4e7dd52 blueswir1
                    stq_hypv(addr, val);
1882 6f27aba6 blueswir1
                    break;
1883 6f27aba6 blueswir1
                }
1884 6f27aba6 blueswir1
            } else {
1885 6f27aba6 blueswir1
                switch(size) {
1886 6f27aba6 blueswir1
                case 1:
1887 1a2fb1c0 blueswir1
                    stb_kernel(addr, val);
1888 6f27aba6 blueswir1
                    break;
1889 6f27aba6 blueswir1
                case 2:
1890 a4e7dd52 blueswir1
                    stw_kernel(addr, val);
1891 6f27aba6 blueswir1
                    break;
1892 6f27aba6 blueswir1
                case 4:
1893 a4e7dd52 blueswir1
                    stl_kernel(addr, val);
1894 6f27aba6 blueswir1
                    break;
1895 6f27aba6 blueswir1
                case 8:
1896 6f27aba6 blueswir1
                default:
1897 a4e7dd52 blueswir1
                    stq_kernel(addr, val);
1898 6f27aba6 blueswir1
                    break;
1899 6f27aba6 blueswir1
                }
1900 81ad8ba2 blueswir1
            }
1901 81ad8ba2 blueswir1
        } else {
1902 81ad8ba2 blueswir1
            switch(size) {
1903 81ad8ba2 blueswir1
            case 1:
1904 1a2fb1c0 blueswir1
                stb_user(addr, val);
1905 81ad8ba2 blueswir1
                break;
1906 81ad8ba2 blueswir1
            case 2:
1907 a4e7dd52 blueswir1
                stw_user(addr, val);
1908 81ad8ba2 blueswir1
                break;
1909 81ad8ba2 blueswir1
            case 4:
1910 a4e7dd52 blueswir1
                stl_user(addr, val);
1911 81ad8ba2 blueswir1
                break;
1912 81ad8ba2 blueswir1
            case 8:
1913 81ad8ba2 blueswir1
            default:
1914 a4e7dd52 blueswir1
                stq_user(addr, val);
1915 81ad8ba2 blueswir1
                break;
1916 81ad8ba2 blueswir1
            }
1917 81ad8ba2 blueswir1
        }
1918 81ad8ba2 blueswir1
        break;
1919 3475187d bellard
    case 0x14: // Bypass
1920 3475187d bellard
    case 0x15: // Bypass, non-cacheable
1921 81ad8ba2 blueswir1
    case 0x1c: // Bypass LE
1922 81ad8ba2 blueswir1
    case 0x1d: // Bypass, non-cacheable LE
1923 0f8a249a blueswir1
        {
1924 02aab46a bellard
            switch(size) {
1925 02aab46a bellard
            case 1:
1926 1a2fb1c0 blueswir1
                stb_phys(addr, val);
1927 02aab46a bellard
                break;
1928 02aab46a bellard
            case 2:
1929 a4e7dd52 blueswir1
                stw_phys(addr, val);
1930 02aab46a bellard
                break;
1931 02aab46a bellard
            case 4:
1932 a4e7dd52 blueswir1
                stl_phys(addr, val);
1933 02aab46a bellard
                break;
1934 02aab46a bellard
            case 8:
1935 02aab46a bellard
            default:
1936 a4e7dd52 blueswir1
                stq_phys(addr, val);
1937 02aab46a bellard
                break;
1938 02aab46a bellard
            }
1939 0f8a249a blueswir1
        }
1940 0f8a249a blueswir1
        return;
1941 db166940 blueswir1
    case 0x24: // Nucleus quad LDD 128 bit atomic
1942 db166940 blueswir1
    case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1943 db166940 blueswir1
        //  Only ldda allowed
1944 db166940 blueswir1
        raise_exception(TT_ILL_INSN);
1945 db166940 blueswir1
        return;
1946 83469015 bellard
    case 0x04: // Nucleus
1947 83469015 bellard
    case 0x0c: // Nucleus Little Endian (LE)
1948 83469015 bellard
    case 0x11: // As if user secondary
1949 83469015 bellard
    case 0x19: // As if user secondary LE
1950 83469015 bellard
    case 0x4a: // UPA config
1951 51996525 blueswir1
    case 0x81: // Secondary
1952 83469015 bellard
    case 0x89: // Secondary LE
1953 0f8a249a blueswir1
        // XXX
1954 0f8a249a blueswir1
        return;
1955 3475187d bellard
    case 0x45: // LSU
1956 0f8a249a blueswir1
        {
1957 0f8a249a blueswir1
            uint64_t oldreg;
1958 0f8a249a blueswir1
1959 0f8a249a blueswir1
            oldreg = env->lsu;
1960 1a2fb1c0 blueswir1
            env->lsu = val & (DMMU_E | IMMU_E);
1961 0f8a249a blueswir1
            // Mappings generated during D/I MMU disabled mode are
1962 0f8a249a blueswir1
            // invalid in normal mode
1963 0f8a249a blueswir1
            if (oldreg != env->lsu) {
1964 77f193da blueswir1
                DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1965 77f193da blueswir1
                            oldreg, env->lsu);
1966 83469015 bellard
#ifdef DEBUG_MMU
1967 0f8a249a blueswir1
                dump_mmu(env);
1968 83469015 bellard
#endif
1969 0f8a249a blueswir1
                tlb_flush(env, 1);
1970 0f8a249a blueswir1
            }
1971 0f8a249a blueswir1
            return;
1972 0f8a249a blueswir1
        }
1973 3475187d bellard
    case 0x50: // I-MMU regs
1974 0f8a249a blueswir1
        {
1975 1a2fb1c0 blueswir1
            int reg = (addr >> 3) & 0xf;
1976 0f8a249a blueswir1
            uint64_t oldreg;
1977 3b46e624 ths
1978 0f8a249a blueswir1
            oldreg = env->immuregs[reg];
1979 3475187d bellard
            switch(reg) {
1980 3475187d bellard
            case 0: // RO
1981 3475187d bellard
            case 4:
1982 3475187d bellard
                return;
1983 3475187d bellard
            case 1: // Not in I-MMU
1984 3475187d bellard
            case 2:
1985 3475187d bellard
            case 7:
1986 3475187d bellard
            case 8:
1987 3475187d bellard
                return;
1988 3475187d bellard
            case 3: // SFSR
1989 1a2fb1c0 blueswir1
                if ((val & 1) == 0)
1990 1a2fb1c0 blueswir1
                    val = 0; // Clear SFSR
1991 3475187d bellard
                break;
1992 3475187d bellard
            case 5: // TSB access
1993 3475187d bellard
            case 6: // Tag access
1994 3475187d bellard
            default:
1995 3475187d bellard
                break;
1996 3475187d bellard
            }
1997 1a2fb1c0 blueswir1
            env->immuregs[reg] = val;
1998 3475187d bellard
            if (oldreg != env->immuregs[reg]) {
1999 77f193da blueswir1
                DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2000 77f193da blueswir1
                            PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
2001 3475187d bellard
            }
2002 952a328f blueswir1
#ifdef DEBUG_MMU
2003 0f8a249a blueswir1
            dump_mmu(env);
2004 3475187d bellard
#endif
2005 0f8a249a blueswir1
            return;
2006 0f8a249a blueswir1
        }
2007 3475187d bellard
    case 0x54: // I-MMU data in
2008 0f8a249a blueswir1
        {
2009 0f8a249a blueswir1
            unsigned int i;
2010 0f8a249a blueswir1
2011 0f8a249a blueswir1
            // Try finding an invalid entry
2012 0f8a249a blueswir1
            for (i = 0; i < 64; i++) {
2013 0f8a249a blueswir1
                if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
2014 0f8a249a blueswir1
                    env->itlb_tag[i] = env->immuregs[6];
2015 1a2fb1c0 blueswir1
                    env->itlb_tte[i] = val;
2016 0f8a249a blueswir1
                    return;
2017 0f8a249a blueswir1
                }
2018 0f8a249a blueswir1
            }
2019 0f8a249a blueswir1
            // Try finding an unlocked entry
2020 0f8a249a blueswir1
            for (i = 0; i < 64; i++) {
2021 0f8a249a blueswir1
                if ((env->itlb_tte[i] & 0x40) == 0) {
2022 0f8a249a blueswir1
                    env->itlb_tag[i] = env->immuregs[6];
2023 1a2fb1c0 blueswir1
                    env->itlb_tte[i] = val;
2024 0f8a249a blueswir1
                    return;
2025 0f8a249a blueswir1
                }
2026 0f8a249a blueswir1
            }
2027 0f8a249a blueswir1
            // error state?
2028 0f8a249a blueswir1
            return;
2029 0f8a249a blueswir1
        }
2030 3475187d bellard
    case 0x55: // I-MMU data access
2031 0f8a249a blueswir1
        {
2032 1a2fb1c0 blueswir1
            unsigned int i = (addr >> 3) & 0x3f;
2033 3475187d bellard
2034 0f8a249a blueswir1
            env->itlb_tag[i] = env->immuregs[6];
2035 1a2fb1c0 blueswir1
            env->itlb_tte[i] = val;
2036 0f8a249a blueswir1
            return;
2037 0f8a249a blueswir1
        }
2038 3475187d bellard
    case 0x57: // I-MMU demap
2039 0f8a249a blueswir1
        // XXX
2040 0f8a249a blueswir1
        return;
2041 3475187d bellard
    case 0x58: // D-MMU regs
2042 0f8a249a blueswir1
        {
2043 1a2fb1c0 blueswir1
            int reg = (addr >> 3) & 0xf;
2044 0f8a249a blueswir1
            uint64_t oldreg;
2045 3b46e624 ths
2046 0f8a249a blueswir1
            oldreg = env->dmmuregs[reg];
2047 3475187d bellard
            switch(reg) {
2048 3475187d bellard
            case 0: // RO
2049 3475187d bellard
            case 4:
2050 3475187d bellard
                return;
2051 3475187d bellard
            case 3: // SFSR
2052 1a2fb1c0 blueswir1
                if ((val & 1) == 0) {
2053 1a2fb1c0 blueswir1
                    val = 0; // Clear SFSR, Fault address
2054 0f8a249a blueswir1
                    env->dmmuregs[4] = 0;
2055 0f8a249a blueswir1
                }
2056 1a2fb1c0 blueswir1
                env->dmmuregs[reg] = val;
2057 3475187d bellard
                break;
2058 3475187d bellard
            case 1: // Primary context
2059 3475187d bellard
            case 2: // Secondary context
2060 3475187d bellard
            case 5: // TSB access
2061 3475187d bellard
            case 6: // Tag access
2062 3475187d bellard
            case 7: // Virtual Watchpoint
2063 3475187d bellard
            case 8: // Physical Watchpoint
2064 3475187d bellard
            default:
2065 3475187d bellard
                break;
2066 3475187d bellard
            }
2067 1a2fb1c0 blueswir1
            env->dmmuregs[reg] = val;
2068 3475187d bellard
            if (oldreg != env->dmmuregs[reg]) {
2069 77f193da blueswir1
                DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2070 77f193da blueswir1
                            PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
2071 3475187d bellard
            }
2072 952a328f blueswir1
#ifdef DEBUG_MMU
2073 0f8a249a blueswir1
            dump_mmu(env);
2074 3475187d bellard
#endif
2075 0f8a249a blueswir1
            return;
2076 0f8a249a blueswir1
        }
2077 3475187d bellard
    case 0x5c: // D-MMU data in
2078 0f8a249a blueswir1
        {
2079 0f8a249a blueswir1
            unsigned int i;
2080 0f8a249a blueswir1
2081 0f8a249a blueswir1
            // Try finding an invalid entry
2082 0f8a249a blueswir1
            for (i = 0; i < 64; i++) {
2083 0f8a249a blueswir1
                if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
2084 0f8a249a blueswir1
                    env->dtlb_tag[i] = env->dmmuregs[6];
2085 1a2fb1c0 blueswir1
                    env->dtlb_tte[i] = val;
2086 0f8a249a blueswir1
                    return;
2087 0f8a249a blueswir1
                }
2088 0f8a249a blueswir1
            }
2089 0f8a249a blueswir1
            // Try finding an unlocked entry
2090 0f8a249a blueswir1
            for (i = 0; i < 64; i++) {
2091 0f8a249a blueswir1
                if ((env->dtlb_tte[i] & 0x40) == 0) {
2092 0f8a249a blueswir1
                    env->dtlb_tag[i] = env->dmmuregs[6];
2093 1a2fb1c0 blueswir1
                    env->dtlb_tte[i] = val;
2094 0f8a249a blueswir1
                    return;
2095 0f8a249a blueswir1
                }
2096 0f8a249a blueswir1
            }
2097 0f8a249a blueswir1
            // error state?
2098 0f8a249a blueswir1
            return;
2099 0f8a249a blueswir1
        }
2100 3475187d bellard
    case 0x5d: // D-MMU data access
2101 0f8a249a blueswir1
        {
2102 1a2fb1c0 blueswir1
            unsigned int i = (addr >> 3) & 0x3f;
2103 3475187d bellard
2104 0f8a249a blueswir1
            env->dtlb_tag[i] = env->dmmuregs[6];
2105 1a2fb1c0 blueswir1
            env->dtlb_tte[i] = val;
2106 0f8a249a blueswir1
            return;
2107 0f8a249a blueswir1
        }
2108 3475187d bellard
    case 0x5f: // D-MMU demap
2109 83469015 bellard
    case 0x49: // Interrupt data receive
2110 0f8a249a blueswir1
        // XXX
2111 0f8a249a blueswir1
        return;
2112 f7350b47 blueswir1
    case 0x46: // D-cache data
2113 f7350b47 blueswir1
    case 0x47: // D-cache tag access
2114 a5a52cf2 blueswir1
    case 0x4b: // E-cache error enable
2115 a5a52cf2 blueswir1
    case 0x4c: // E-cache asynchronous fault status
2116 a5a52cf2 blueswir1
    case 0x4d: // E-cache asynchronous fault address
2117 f7350b47 blueswir1
    case 0x4e: // E-cache tag data
2118 f7350b47 blueswir1
    case 0x66: // I-cache instruction access
2119 f7350b47 blueswir1
    case 0x67: // I-cache tag access
2120 f7350b47 blueswir1
    case 0x6e: // I-cache predecode
2121 f7350b47 blueswir1
    case 0x6f: // I-cache LRU etc.
2122 f7350b47 blueswir1
    case 0x76: // E-cache tag
2123 f7350b47 blueswir1
    case 0x7e: // E-cache tag
2124 f7350b47 blueswir1
        return;
2125 3475187d bellard
    case 0x51: // I-MMU 8k TSB pointer, RO
2126 3475187d bellard
    case 0x52: // I-MMU 64k TSB pointer, RO
2127 3475187d bellard
    case 0x56: // I-MMU tag read, RO
2128 3475187d bellard
    case 0x59: // D-MMU 8k TSB pointer, RO
2129 3475187d bellard
    case 0x5a: // D-MMU 64k TSB pointer, RO
2130 3475187d bellard
    case 0x5b: // D-MMU data pointer, RO
2131 3475187d bellard
    case 0x5e: // D-MMU tag read, RO
2132 83469015 bellard
    case 0x48: // Interrupt dispatch, RO
2133 83469015 bellard
    case 0x7f: // Incoming interrupt vector, RO
2134 83469015 bellard
    case 0x82: // Primary no-fault, RO
2135 83469015 bellard
    case 0x83: // Secondary no-fault, RO
2136 83469015 bellard
    case 0x8a: // Primary no-fault LE, RO
2137 83469015 bellard
    case 0x8b: // Secondary no-fault LE, RO
2138 3475187d bellard
    default:
2139 1a2fb1c0 blueswir1
        do_unassigned_access(addr, 1, 0, 1);
2140 0f8a249a blueswir1
        return;
2141 3475187d bellard
    }
2142 3475187d bellard
}
2143 81ad8ba2 blueswir1
#endif /* CONFIG_USER_ONLY */
2144 3391c818 blueswir1
2145 db166940 blueswir1
void helper_ldda_asi(target_ulong addr, int asi, int rd)
2146 db166940 blueswir1
{
2147 db166940 blueswir1
    if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2148 5578ceab blueswir1
        || ((env->def->features & CPU_FEATURE_HYPV)
2149 5578ceab blueswir1
            && asi >= 0x30 && asi < 0x80
2150 fb79ceb9 blueswir1
            && !(env->hpstate & HS_PRIV)))
2151 db166940 blueswir1
        raise_exception(TT_PRIV_ACT);
2152 db166940 blueswir1
2153 db166940 blueswir1
    switch (asi) {
2154 db166940 blueswir1
    case 0x24: // Nucleus quad LDD 128 bit atomic
2155 db166940 blueswir1
    case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2156 db166940 blueswir1
        helper_check_align(addr, 0xf);
2157 db166940 blueswir1
        if (rd == 0) {
2158 db166940 blueswir1
            env->gregs[1] = ldq_kernel(addr + 8);
2159 db166940 blueswir1
            if (asi == 0x2c)
2160 db166940 blueswir1
                bswap64s(&env->gregs[1]);
2161 db166940 blueswir1
        } else if (rd < 8) {
2162 db166940 blueswir1
            env->gregs[rd] = ldq_kernel(addr);
2163 db166940 blueswir1
            env->gregs[rd + 1] = ldq_kernel(addr + 8);
2164 db166940 blueswir1
            if (asi == 0x2c) {
2165 db166940 blueswir1
                bswap64s(&env->gregs[rd]);
2166 db166940 blueswir1
                bswap64s(&env->gregs[rd + 1]);
2167 db166940 blueswir1
            }
2168 db166940 blueswir1
        } else {
2169 db166940 blueswir1
            env->regwptr[rd] = ldq_kernel(addr);
2170 db166940 blueswir1
            env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2171 db166940 blueswir1
            if (asi == 0x2c) {
2172 db166940 blueswir1
                bswap64s(&env->regwptr[rd]);
2173 db166940 blueswir1
                bswap64s(&env->regwptr[rd + 1]);
2174 db166940 blueswir1
            }
2175 db166940 blueswir1
        }
2176 db166940 blueswir1
        break;
2177 db166940 blueswir1
    default:
2178 db166940 blueswir1
        helper_check_align(addr, 0x3);
2179 db166940 blueswir1
        if (rd == 0)
2180 db166940 blueswir1
            env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2181 db166940 blueswir1
        else if (rd < 8) {
2182 db166940 blueswir1
            env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2183 db166940 blueswir1
            env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2184 db166940 blueswir1
        } else {
2185 db166940 blueswir1
            env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2186 db166940 blueswir1
            env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2187 db166940 blueswir1
        }
2188 db166940 blueswir1
        break;
2189 db166940 blueswir1
    }
2190 db166940 blueswir1
}
2191 db166940 blueswir1
2192 1a2fb1c0 blueswir1
void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2193 3391c818 blueswir1
{
2194 3391c818 blueswir1
    unsigned int i;
2195 1a2fb1c0 blueswir1
    target_ulong val;
2196 3391c818 blueswir1
2197 c2bc0e38 blueswir1
    helper_check_align(addr, 3);
2198 3391c818 blueswir1
    switch (asi) {
2199 3391c818 blueswir1
    case 0xf0: // Block load primary
2200 3391c818 blueswir1
    case 0xf1: // Block load secondary
2201 3391c818 blueswir1
    case 0xf8: // Block load primary LE
2202 3391c818 blueswir1
    case 0xf9: // Block load secondary LE
2203 51996525 blueswir1
        if (rd & 7) {
2204 51996525 blueswir1
            raise_exception(TT_ILL_INSN);
2205 51996525 blueswir1
            return;
2206 51996525 blueswir1
        }
2207 c2bc0e38 blueswir1
        helper_check_align(addr, 0x3f);
2208 51996525 blueswir1
        for (i = 0; i < 16; i++) {
2209 77f193da blueswir1
            *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2210 77f193da blueswir1
                                                         0);
2211 1a2fb1c0 blueswir1
            addr += 4;
2212 3391c818 blueswir1
        }
2213 3391c818 blueswir1
2214 3391c818 blueswir1
        return;
2215 3391c818 blueswir1
    default:
2216 3391c818 blueswir1
        break;
2217 3391c818 blueswir1
    }
2218 3391c818 blueswir1
2219 1a2fb1c0 blueswir1
    val = helper_ld_asi(addr, asi, size, 0);
2220 3391c818 blueswir1
    switch(size) {
2221 3391c818 blueswir1
    default:
2222 3391c818 blueswir1
    case 4:
2223 1a2fb1c0 blueswir1
        *((uint32_t *)&FT0) = val;
2224 3391c818 blueswir1
        break;
2225 3391c818 blueswir1
    case 8:
2226 1a2fb1c0 blueswir1
        *((int64_t *)&DT0) = val;
2227 3391c818 blueswir1
        break;
2228 1f587329 blueswir1
    case 16:
2229 1f587329 blueswir1
        // XXX
2230 1f587329 blueswir1
        break;
2231 3391c818 blueswir1
    }
2232 3391c818 blueswir1
}
2233 3391c818 blueswir1
2234 1a2fb1c0 blueswir1
void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2235 3391c818 blueswir1
{
2236 3391c818 blueswir1
    unsigned int i;
2237 1a2fb1c0 blueswir1
    target_ulong val = 0;
2238 3391c818 blueswir1
2239 c2bc0e38 blueswir1
    helper_check_align(addr, 3);
2240 3391c818 blueswir1
    switch (asi) {
2241 3391c818 blueswir1
    case 0xf0: // Block store primary
2242 3391c818 blueswir1
    case 0xf1: // Block store secondary
2243 3391c818 blueswir1
    case 0xf8: // Block store primary LE
2244 3391c818 blueswir1
    case 0xf9: // Block store secondary LE
2245 51996525 blueswir1
        if (rd & 7) {
2246 51996525 blueswir1
            raise_exception(TT_ILL_INSN);
2247 51996525 blueswir1
            return;
2248 51996525 blueswir1
        }
2249 c2bc0e38 blueswir1
        helper_check_align(addr, 0x3f);
2250 51996525 blueswir1
        for (i = 0; i < 16; i++) {
2251 1a2fb1c0 blueswir1
            val = *(uint32_t *)&env->fpr[rd++];
2252 1a2fb1c0 blueswir1
            helper_st_asi(addr, val, asi & 0x8f, 4);
2253 1a2fb1c0 blueswir1
            addr += 4;
2254 3391c818 blueswir1
        }
2255 3391c818 blueswir1
2256 3391c818 blueswir1
        return;
2257 3391c818 blueswir1
    default:
2258 3391c818 blueswir1
        break;
2259 3391c818 blueswir1
    }
2260 3391c818 blueswir1
2261 3391c818 blueswir1
    switch(size) {
2262 3391c818 blueswir1
    default:
2263 3391c818 blueswir1
    case 4:
2264 1a2fb1c0 blueswir1
        val = *((uint32_t *)&FT0);
2265 3391c818 blueswir1
        break;
2266 3391c818 blueswir1
    case 8:
2267 1a2fb1c0 blueswir1
        val = *((int64_t *)&DT0);
2268 3391c818 blueswir1
        break;
2269 1f587329 blueswir1
    case 16:
2270 1f587329 blueswir1
        // XXX
2271 1f587329 blueswir1
        break;
2272 3391c818 blueswir1
    }
2273 1a2fb1c0 blueswir1
    helper_st_asi(addr, val, asi, size);
2274 1a2fb1c0 blueswir1
}
2275 1a2fb1c0 blueswir1
2276 1a2fb1c0 blueswir1
target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2277 1a2fb1c0 blueswir1
                            target_ulong val2, uint32_t asi)
2278 1a2fb1c0 blueswir1
{
2279 1a2fb1c0 blueswir1
    target_ulong ret;
2280 1a2fb1c0 blueswir1
2281 1a2fb1c0 blueswir1
    val1 &= 0xffffffffUL;
2282 1a2fb1c0 blueswir1
    ret = helper_ld_asi(addr, asi, 4, 0);
2283 1a2fb1c0 blueswir1
    ret &= 0xffffffffUL;
2284 1a2fb1c0 blueswir1
    if (val1 == ret)
2285 1a2fb1c0 blueswir1
        helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
2286 1a2fb1c0 blueswir1
    return ret;
2287 3391c818 blueswir1
}
2288 3391c818 blueswir1
2289 1a2fb1c0 blueswir1
target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2290 1a2fb1c0 blueswir1
                             target_ulong val2, uint32_t asi)
2291 1a2fb1c0 blueswir1
{
2292 1a2fb1c0 blueswir1
    target_ulong ret;
2293 1a2fb1c0 blueswir1
2294 1a2fb1c0 blueswir1
    ret = helper_ld_asi(addr, asi, 8, 0);
2295 1a2fb1c0 blueswir1
    if (val1 == ret)
2296 1a2fb1c0 blueswir1
        helper_st_asi(addr, val2, asi, 8);
2297 1a2fb1c0 blueswir1
    return ret;
2298 1a2fb1c0 blueswir1
}
2299 81ad8ba2 blueswir1
#endif /* TARGET_SPARC64 */
2300 3475187d bellard
2301 3475187d bellard
#ifndef TARGET_SPARC64
2302 1a2fb1c0 blueswir1
void helper_rett(void)
2303 e8af50a3 bellard
{
2304 af7bf89b bellard
    unsigned int cwp;
2305 af7bf89b bellard
2306 d4218d99 blueswir1
    if (env->psret == 1)
2307 d4218d99 blueswir1
        raise_exception(TT_ILL_INSN);
2308 d4218d99 blueswir1
2309 e8af50a3 bellard
    env->psret = 1;
2310 1a14026e blueswir1
    cwp = cpu_cwp_inc(env, env->cwp + 1) ;
2311 e8af50a3 bellard
    if (env->wim & (1 << cwp)) {
2312 e8af50a3 bellard
        raise_exception(TT_WIN_UNF);
2313 e8af50a3 bellard
    }
2314 e8af50a3 bellard
    set_cwp(cwp);
2315 e8af50a3 bellard
    env->psrs = env->psrps;
2316 e8af50a3 bellard
}
2317 3475187d bellard
#endif
2318 e8af50a3 bellard
2319 3b89f26c blueswir1
target_ulong helper_udiv(target_ulong a, target_ulong b)
2320 3b89f26c blueswir1
{
2321 3b89f26c blueswir1
    uint64_t x0;
2322 3b89f26c blueswir1
    uint32_t x1;
2323 3b89f26c blueswir1
2324 7621a90d blueswir1
    x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2325 3b89f26c blueswir1
    x1 = b;
2326 3b89f26c blueswir1
2327 3b89f26c blueswir1
    if (x1 == 0) {
2328 3b89f26c blueswir1
        raise_exception(TT_DIV_ZERO);
2329 3b89f26c blueswir1
    }
2330 3b89f26c blueswir1
2331 3b89f26c blueswir1
    x0 = x0 / x1;
2332