Revision 3a3b925d target-sparc/cpu.h
| b/target-sparc/cpu.h | ||
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#ifdef TARGET_SPARC64 |
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#define FSR_FTT_NMASK 0xfffffffffffe3fffULL |
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#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL |
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#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL |
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#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL |
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#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL |
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#else |
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#define FSR_FTT_NMASK 0xfffe3fffULL |
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#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL |
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#define FSR_LDFSR_OLDMASK 0x000fc000ULL |
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#endif |
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#define FSR_LDFSR_MASK 0xcfc00fffULL |
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#define FSR_FTT_IEEE_EXCP (1ULL << 14) |
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#define FSR_FTT_UNIMPFPOP (3ULL << 14) |
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#define FSR_FTT_SEQ_ERROR (4ULL << 14) |
| ... | ... | |
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sparc_def_t *def; |
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} CPUSPARCState; |
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#if defined(TARGET_SPARC64) |
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#define GET_FSR32(env) (env->fsr & 0xcfc1ffff) |
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#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
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env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \ |
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} while (0) |
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#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL) |
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#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
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env->fsr = _tmp & 0x3fcfc1c3ffULL; \ |
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} while (0) |
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#else |
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#define GET_FSR32(env) (env->fsr) |
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#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
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env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \ |
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} while (0) |
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#endif |
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/* helper.c */ |
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CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
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void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
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