Revision 3a3b925d target-sparc/translate.c

b/target-sparc/translate.c
4368 4368 
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4369 4369 
                                   offsetof(CPUState, fpr[rd]));
4370 4370 
                    break;
4371 
                case 0x21:      /* load fsr */
4371 
                case 0x21:      /* ldfsr, V9 ldxfsr */
4372 
#ifdef TARGET_SPARC64
4372 4373 
                    gen_address_mask(dc, cpu_addr);
4373 
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4374 
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4375 
                                   offsetof(CPUState, ft0));
4376 
                    tcg_gen_helper_0_0(helper_ldfsr);
4374 
                    if (rd == 1) {
4375 
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4376 
                        tcg_gen_helper_0_1(helper_ldxfsr, cpu_tmp64);
4377 
                    } else
4378 
#else
4379 
                    {
4380 
                        tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4381 
                        tcg_gen_helper_0_1(helper_ldfsr, cpu_tmp32);
4382 
                    }
4383 
#endif
4377 4384 
                    break;
4378 4385 
                case 0x22:      /* load quad fpreg */
4379 4386 
                    {
......
4506 4513 
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4507 4514 
                    break;
4508 4515 
                case 0x25: /* stfsr, V9 stxfsr */
4516 
#ifdef TARGET_SPARC64
4509 4517 
                    gen_address_mask(dc, cpu_addr);
4510 
                    tcg_gen_helper_0_0(helper_stfsr);
4511 
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4512 
                                   offsetof(CPUState, ft0));
4518 
                    tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
4519 
                    if (rd == 1)
4520 
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4521 
                    else {
4522 
                        tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp64);
4523 
                        tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4524 
                    }
4525 
#else
4526 
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
4513 4527 
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4528 
#endif
4514 4529 
                    break;
4515 4530 
                case 0x26:
4516 4531 
#ifdef TARGET_SPARC64

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