Statistics
| Branch: | Revision:

root / target-sparc / cpu.h @ 3a3b925d

History | View | Annotate | Download (14.2 kB)

1
#ifndef CPU_SPARC_H
2
#define CPU_SPARC_H
3

    
4
#include "config.h"
5

    
6
#if !defined(TARGET_SPARC64)
7
#define TARGET_LONG_BITS 32
8
#define TARGET_FPREGS 32
9
#define TARGET_PAGE_BITS 12 /* 4k */
10
#else
11
#define TARGET_LONG_BITS 64
12
#define TARGET_FPREGS 64
13
#define TARGET_PAGE_BITS 13 /* 8k */
14
#endif
15

    
16
#define TARGET_PHYS_ADDR_BITS 64
17

    
18
#include "cpu-defs.h"
19

    
20
#include "softfloat.h"
21

    
22
#define TARGET_HAS_ICE 1
23

    
24
#if !defined(TARGET_SPARC64)
25
#define ELF_MACHINE     EM_SPARC
26
#else
27
#define ELF_MACHINE     EM_SPARCV9
28
#endif
29

    
30
/*#define EXCP_INTERRUPT 0x100*/
31

    
32
/* trap definitions */
33
#ifndef TARGET_SPARC64
34
#define TT_TFAULT   0x01
35
#define TT_ILL_INSN 0x02
36
#define TT_PRIV_INSN 0x03
37
#define TT_NFPU_INSN 0x04
38
#define TT_WIN_OVF  0x05
39
#define TT_WIN_UNF  0x06
40
#define TT_UNALIGNED 0x07
41
#define TT_FP_EXCP  0x08
42
#define TT_DFAULT   0x09
43
#define TT_TOVF     0x0a
44
#define TT_EXTINT   0x10
45
#define TT_CODE_ACCESS 0x21
46
#define TT_UNIMP_FLUSH 0x25
47
#define TT_DATA_ACCESS 0x29
48
#define TT_DIV_ZERO 0x2a
49
#define TT_NCP_INSN 0x24
50
#define TT_TRAP     0x80
51
#else
52
#define TT_TFAULT   0x08
53
#define TT_CODE_ACCESS 0x0a
54
#define TT_ILL_INSN 0x10
55
#define TT_UNIMP_FLUSH TT_ILL_INSN
56
#define TT_PRIV_INSN 0x11
57
#define TT_NFPU_INSN 0x20
58
#define TT_FP_EXCP  0x21
59
#define TT_TOVF     0x23
60
#define TT_CLRWIN   0x24
61
#define TT_DIV_ZERO 0x28
62
#define TT_DFAULT   0x30
63
#define TT_DATA_ACCESS 0x32
64
#define TT_UNALIGNED 0x34
65
#define TT_PRIV_ACT 0x37
66
#define TT_EXTINT   0x40
67
#define TT_IVEC     0x60
68
#define TT_TMISS    0x64
69
#define TT_DMISS    0x68
70
#define TT_DPROT    0x6c
71
#define TT_SPILL    0x80
72
#define TT_FILL     0xc0
73
#define TT_WOTHER   0x10
74
#define TT_TRAP     0x100
75
#endif
76

    
77
#define PSR_NEG_SHIFT 23
78
#define PSR_NEG   (1 << PSR_NEG_SHIFT)
79
#define PSR_ZERO_SHIFT 22
80
#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
81
#define PSR_OVF_SHIFT 21
82
#define PSR_OVF   (1 << PSR_OVF_SHIFT)
83
#define PSR_CARRY_SHIFT 20
84
#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
85
#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
86
#define PSR_EF    (1<<12)
87
#define PSR_PIL   0xf00
88
#define PSR_S     (1<<7)
89
#define PSR_PS    (1<<6)
90
#define PSR_ET    (1<<5)
91
#define PSR_CWP   0x1f
92

    
93
/* Trap base register */
94
#define TBR_BASE_MASK 0xfffff000
95

    
96
#if defined(TARGET_SPARC64)
97
#define PS_IG    (1<<11)
98
#define PS_MG    (1<<10)
99
#define PS_RMO   (1<<7)
100
#define PS_RED   (1<<5)
101
#define PS_PEF   (1<<4)
102
#define PS_AM    (1<<3)
103
#define PS_PRIV  (1<<2)
104
#define PS_IE    (1<<1)
105
#define PS_AG    (1<<0)
106

    
107
#define FPRS_FEF (1<<2)
108

    
109
#define HS_PRIV  (1<<2)
110
#endif
111

    
112
/* Fcc */
113
#define FSR_RD1        (1ULL << 31)
114
#define FSR_RD0        (1ULL << 30)
115
#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
116
#define FSR_RD_NEAREST 0
117
#define FSR_RD_ZERO    FSR_RD0
118
#define FSR_RD_POS     FSR_RD1
119
#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
120

    
121
#define FSR_NVM   (1ULL << 27)
122
#define FSR_OFM   (1ULL << 26)
123
#define FSR_UFM   (1ULL << 25)
124
#define FSR_DZM   (1ULL << 24)
125
#define FSR_NXM   (1ULL << 23)
126
#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
127

    
128
#define FSR_NVA   (1ULL << 9)
129
#define FSR_OFA   (1ULL << 8)
130
#define FSR_UFA   (1ULL << 7)
131
#define FSR_DZA   (1ULL << 6)
132
#define FSR_NXA   (1ULL << 5)
133
#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
134

    
135
#define FSR_NVC   (1ULL << 4)
136
#define FSR_OFC   (1ULL << 3)
137
#define FSR_UFC   (1ULL << 2)
138
#define FSR_DZC   (1ULL << 1)
139
#define FSR_NXC   (1ULL << 0)
140
#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
141

    
142
#define FSR_FTT2   (1ULL << 16)
143
#define FSR_FTT1   (1ULL << 15)
144
#define FSR_FTT0   (1ULL << 14)
145
//gcc warns about constant overflow for ~FSR_FTT_MASK
146
//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
147
#ifdef TARGET_SPARC64
148
#define FSR_FTT_NMASK      0xfffffffffffe3fffULL
149
#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
150
#define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
151
#define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
152
#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
153
#else
154
#define FSR_FTT_NMASK      0xfffe3fffULL
155
#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
156
#define FSR_LDFSR_OLDMASK  0x000fc000ULL
157
#endif
158
#define FSR_LDFSR_MASK     0xcfc00fffULL
159
#define FSR_FTT_IEEE_EXCP (1ULL << 14)
160
#define FSR_FTT_UNIMPFPOP (3ULL << 14)
161
#define FSR_FTT_SEQ_ERROR (4ULL << 14)
162
#define FSR_FTT_INVAL_FPR (6ULL << 14)
163

    
164
#define FSR_FCC1_SHIFT 11
165
#define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
166
#define FSR_FCC0_SHIFT 10
167
#define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
168

    
169
/* MMU */
170
#define MMU_E     (1<<0)
171
#define MMU_NF    (1<<1)
172

    
173
#define PTE_ENTRYTYPE_MASK 3
174
#define PTE_ACCESS_MASK    0x1c
175
#define PTE_ACCESS_SHIFT   2
176
#define PTE_PPN_SHIFT      7
177
#define PTE_ADDR_MASK      0xffffff00
178

    
179
#define PG_ACCESSED_BIT 5
180
#define PG_MODIFIED_BIT 6
181
#define PG_CACHE_BIT    7
182

    
183
#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
184
#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
185
#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
186

    
187
/* 3 <= NWINDOWS <= 32. */
188
#define MIN_NWINDOWS 3
189
#define MAX_NWINDOWS 32
190

    
191
#if !defined(TARGET_SPARC64)
192
#define NB_MMU_MODES 2
193
#else
194
#define NB_MMU_MODES 3
195
typedef struct trap_state {
196
    uint64_t tpc;
197
    uint64_t tnpc;
198
    uint64_t tstate;
199
    uint32_t tt;
200
} trap_state;
201
#endif
202

    
203
typedef struct sparc_def_t {
204
    const char *name;
205
    target_ulong iu_version;
206
    uint32_t fpu_version;
207
    uint32_t mmu_version;
208
    uint32_t mmu_bm;
209
    uint32_t mmu_ctpr_mask;
210
    uint32_t mmu_cxr_mask;
211
    uint32_t mmu_sfsr_mask;
212
    uint32_t mmu_trcr_mask;
213
    uint32_t features;
214
    uint32_t nwindows;
215
    uint32_t maxtl;
216
} sparc_def_t;
217

    
218
#define CPU_FEATURE_FLOAT    (1 << 0)
219
#define CPU_FEATURE_FLOAT128 (1 << 1)
220
#define CPU_FEATURE_SWAP     (1 << 2)
221
#define CPU_FEATURE_MUL      (1 << 3)
222
#define CPU_FEATURE_DIV      (1 << 4)
223
#define CPU_FEATURE_FLUSH    (1 << 5)
224
#define CPU_FEATURE_FSQRT    (1 << 6)
225
#define CPU_FEATURE_FMUL     (1 << 7)
226
#define CPU_FEATURE_VIS1     (1 << 8)
227
#define CPU_FEATURE_VIS2     (1 << 9)
228
#define CPU_FEATURE_FSMULD   (1 << 10)
229
#define CPU_FEATURE_HYPV     (1 << 11)
230
#define CPU_FEATURE_CMT      (1 << 12)
231
#define CPU_FEATURE_GL       (1 << 13)
232
#ifndef TARGET_SPARC64
233
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
234
                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
235
                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
236
                              CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
237
#else
238
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
239
                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
240
                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
241
                              CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
242
                              CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
243
enum {
244
    mmu_us_12, // Ultrasparc < III (64 entry TLB)
245
    mmu_us_3,  // Ultrasparc III (512 entry TLB)
246
    mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
247
    mmu_sun4v, // T1, T2
248
};
249
#endif
250

    
251
typedef struct CPUSPARCState {
252
    target_ulong gregs[8]; /* general registers */
253
    target_ulong *regwptr; /* pointer to current register window */
254
    target_ulong pc;       /* program counter */
255
    target_ulong npc;      /* next program counter */
256
    target_ulong y;        /* multiply/divide register */
257

    
258
    /* emulator internal flags handling */
259
    target_ulong cc_src, cc_src2;
260
    target_ulong cc_dst;
261

    
262
    target_ulong t0, t1; /* temporaries live across basic blocks */
263
    target_ulong cond; /* conditional branch result (XXX: save it in a
264
                          temporary register when possible) */
265

    
266
    uint32_t psr;      /* processor state register */
267
    target_ulong fsr;      /* FPU state register */
268
    float32 fpr[TARGET_FPREGS];  /* floating point registers */
269
    uint32_t cwp;      /* index of current register window (extracted
270
                          from PSR) */
271
    uint32_t wim;      /* window invalid mask */
272
    target_ulong tbr;  /* trap base register */
273
    int      psrs;     /* supervisor mode (extracted from PSR) */
274
    int      psrps;    /* previous supervisor mode */
275
    int      psret;    /* enable traps */
276
    uint32_t psrpil;   /* interrupt blocking level */
277
    uint32_t pil_in;   /* incoming interrupt level bitmap */
278
    int      psref;    /* enable fpu */
279
    target_ulong version;
280
    int interrupt_index;
281
    uint32_t nwindows;
282
    /* NOTE: we allow 8 more registers to handle wrapping */
283
    target_ulong regbase[MAX_NWINDOWS * 16 + 8];
284

    
285
    CPU_COMMON
286

    
287
    /* MMU regs */
288
#if defined(TARGET_SPARC64)
289
    uint64_t lsu;
290
#define DMMU_E 0x8
291
#define IMMU_E 0x4
292
    uint64_t immuregs[16];
293
    uint64_t dmmuregs[16];
294
    uint64_t itlb_tag[64];
295
    uint64_t itlb_tte[64];
296
    uint64_t dtlb_tag[64];
297
    uint64_t dtlb_tte[64];
298
    uint32_t mmu_version;
299
#else
300
    uint32_t mmuregs[32];
301
    uint64_t mxccdata[4];
302
    uint64_t mxccregs[8];
303
    uint64_t prom_addr;
304
#endif
305
    /* temporary float registers */
306
    float32 ft0, ft1;
307
    float64 dt0, dt1;
308
    float128 qt0, qt1;
309
    float_status fp_status;
310
#if defined(TARGET_SPARC64)
311
#define MAXTL_MAX 8
312
#define MAXTL_MASK (MAXTL_MAX - 1)
313
    trap_state *tsptr;
314
    trap_state ts[MAXTL_MAX];
315
    uint32_t xcc;               /* Extended integer condition codes */
316
    uint32_t asi;
317
    uint32_t pstate;
318
    uint32_t tl;
319
    uint32_t maxtl;
320
    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
321
    uint64_t agregs[8]; /* alternate general registers */
322
    uint64_t bgregs[8]; /* backup for normal global registers */
323
    uint64_t igregs[8]; /* interrupt general registers */
324
    uint64_t mgregs[8]; /* mmu general registers */
325
    uint64_t fprs;
326
    uint64_t tick_cmpr, stick_cmpr;
327
    void *tick, *stick;
328
    uint64_t gsr;
329
    uint32_t gl; // UA2005
330
    /* UA 2005 hyperprivileged registers */
331
    uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
332
    void *hstick; // UA 2005
333
#endif
334
    sparc_def_t *def;
335
} CPUSPARCState;
336

    
337
/* helper.c */
338
CPUSPARCState *cpu_sparc_init(const char *cpu_model);
339
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
340
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
341
                                                 ...));
342

    
343
/* translate.c */
344
void gen_intermediate_code_init(CPUSPARCState *env);
345

    
346
/* cpu-exec.c */
347
int cpu_sparc_exec(CPUSPARCState *s);
348

    
349
#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
350
                      (env->psref? PSR_EF : 0) |                        \
351
                      (env->psrpil << 8) |                              \
352
                      (env->psrs? PSR_S : 0) |                          \
353
                      (env->psrps? PSR_PS : 0) |                        \
354
                      (env->psret? PSR_ET : 0) | env->cwp)
355

    
356
#ifndef NO_CPU_IO_DEFS
357
static inline void memcpy32(target_ulong *dst, const target_ulong *src)
358
{
359
    dst[0] = src[0];
360
    dst[1] = src[1];
361
    dst[2] = src[2];
362
    dst[3] = src[3];
363
    dst[4] = src[4];
364
    dst[5] = src[5];
365
    dst[6] = src[6];
366
    dst[7] = src[7];
367
}
368

    
369
static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
370
{
371
    /* put the modified wrap registers at their proper location */
372
    if (env1->cwp == env1->nwindows - 1)
373
        memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
374
    env1->cwp = new_cwp;
375
    /* put the wrap registers at their temporary location */
376
    if (new_cwp == env1->nwindows - 1)
377
        memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
378
    env1->regwptr = env1->regbase + (new_cwp * 16);
379
}
380

    
381
static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
382
{
383
    if (unlikely(cwp >= env1->nwindows))
384
        cwp -= env1->nwindows;
385
    return cwp;
386
}
387

    
388
static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
389
{
390
    if (unlikely(cwp < 0))
391
        cwp += env1->nwindows;
392
    return cwp;
393
}
394
#endif
395

    
396
#define PUT_PSR(env, val) do { int _tmp = val;                          \
397
        env->psr = _tmp & PSR_ICC;                                      \
398
        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
399
        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
400
        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
401
        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
402
        env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
403
        cpu_set_cwp(env, _tmp & PSR_CWP);                               \
404
    } while (0)
405

    
406
#ifdef TARGET_SPARC64
407
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
408
#define PUT_CCR(env, val) do { int _tmp = val;                          \
409
        env->xcc = (_tmp >> 4) << 20;                                   \
410
        env->psr = (_tmp & 0xf) << 20;                                  \
411
    } while (0)
412
#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
413

    
414
#ifndef NO_CPU_IO_DEFS
415
static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
416
{
417
    if (unlikely(cwp >= env1->nwindows || cwp < 0))
418
        cwp = 0;
419
    cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
420
}
421
#endif
422
#endif
423

    
424
/* cpu-exec.c */
425
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
426
                          int is_asi);
427

    
428
#define CPUState CPUSPARCState
429
#define cpu_init cpu_sparc_init
430
#define cpu_exec cpu_sparc_exec
431
#define cpu_gen_code cpu_sparc_gen_code
432
#define cpu_signal_handler cpu_sparc_signal_handler
433
#define cpu_list sparc_cpu_list
434

    
435
#define CPU_SAVE_VERSION 5
436

    
437
/* MMU modes definitions */
438
#define MMU_MODE0_SUFFIX _user
439
#define MMU_MODE1_SUFFIX _kernel
440
#ifdef TARGET_SPARC64
441
#define MMU_MODE2_SUFFIX _hypv
442
#endif
443
#define MMU_USER_IDX   0
444
#define MMU_KERNEL_IDX 1
445
#define MMU_HYPV_IDX   2
446

    
447
static inline int cpu_mmu_index(CPUState *env1)
448
{
449
#if defined(CONFIG_USER_ONLY)
450
    return MMU_USER_IDX;
451
#elif !defined(TARGET_SPARC64)
452
    return env1->psrs;
453
#else
454
    if (!env1->psrs)
455
        return MMU_USER_IDX;
456
    else if ((env1->hpstate & HS_PRIV) == 0)
457
        return MMU_KERNEL_IDX;
458
    else
459
        return MMU_HYPV_IDX;
460
#endif
461
}
462

    
463
static inline int cpu_fpu_enabled(CPUState *env1)
464
{
465
#if defined(CONFIG_USER_ONLY)
466
    return 1;
467
#elif !defined(TARGET_SPARC64)
468
    return env1->psref;
469
#else
470
    return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
471
#endif
472
}
473

    
474
#if defined(CONFIG_USER_ONLY)
475
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
476
{
477
    if (newsp)
478
        env->regwptr[22] = newsp;
479
    env->regwptr[0] = 0;
480
    /* FIXME: Do we also need to clear CF?  */
481
    /* XXXXX */
482
    printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
483
}
484
#endif
485

    
486
#define CPU_PC_FROM_TB(env, tb) do { \
487
    env->pc = tb->pc; \
488
    env->npc = tb->cs_base; \
489
    } while(0)
490

    
491
#include "cpu-all.h"
492

    
493
#endif