root / target-ppc / op_helper_mem.h @ 3a607854
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/*
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* PowerPC emulation micro-operations helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Multiple word / string load and store */
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static inline target_ulong glue(ld32r, MEMSUFFIX) (target_ulong EA) |
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{
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uint32_t tmp = glue(ldl, MEMSUFFIX)(EA); |
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return ((tmp & 0xFF000000UL) >> 24) | ((tmp & 0x00FF0000UL) >> 8) | |
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((tmp & 0x0000FF00UL) << 8) | ((tmp & 0x000000FFUL) << 24); |
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} |
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static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, target_ulong data) |
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{
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uint32_t tmp = |
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((data & 0xFF000000UL) >> 24) | ((data & 0x00FF0000UL) >> 8) | |
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((data & 0x0000FF00UL) << 8) | ((data & 0x000000FFUL) << 24); |
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glue(stl, MEMSUFFIX)(EA, tmp); |
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} |
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void glue(do_lmw, MEMSUFFIX) (int dst) |
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{
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for (; dst < 32; dst++, T0 += 4) { |
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ugpr(dst) = glue(ldl, MEMSUFFIX)((uint32_t)T0); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_lmw_64, MEMSUFFIX) (int dst) |
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{
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for (; dst < 32; dst++, T0 += 4) { |
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ugpr(dst) = glue(ldl, MEMSUFFIX)((uint64_t)T0); |
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} |
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} |
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#endif
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void glue(do_stmw, MEMSUFFIX) (int src) |
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{
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for (; src < 32; src++, T0 += 4) { |
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glue(stl, MEMSUFFIX)((uint32_t)T0, ugpr(src)); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_stmw_64, MEMSUFFIX) (int src) |
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{
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for (; src < 32; src++, T0 += 4) { |
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glue(stl, MEMSUFFIX)((uint64_t)T0, ugpr(src)); |
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} |
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} |
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#endif
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void glue(do_lmw_le, MEMSUFFIX) (int dst) |
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{
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for (; dst < 32; dst++, T0 += 4) { |
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ugpr(dst) = glue(ld32r, MEMSUFFIX)((uint32_t)T0); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_lmw_le_64, MEMSUFFIX) (int dst) |
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{
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for (; dst < 32; dst++, T0 += 4) { |
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ugpr(dst) = glue(ld32r, MEMSUFFIX)((uint64_t)T0); |
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} |
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} |
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#endif
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void glue(do_stmw_le, MEMSUFFIX) (int src) |
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{
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for (; src < 32; src++, T0 += 4) { |
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glue(st32r, MEMSUFFIX)((uint32_t)T0, ugpr(src)); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_stmw_le_64, MEMSUFFIX) (int src) |
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{
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for (; src < 32; src++, T0 += 4) { |
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glue(st32r, MEMSUFFIX)((uint64_t)T0, ugpr(src)); |
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} |
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} |
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#endif
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void glue(do_lsw, MEMSUFFIX) (int dst) |
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{
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uint32_t tmp; |
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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ugpr(dst++) = glue(ldl, MEMSUFFIX)((uint32_t)T0); |
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if (unlikely(dst == 32)) |
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dst = 0;
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} |
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if (unlikely(T1 != 0)) { |
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tmp = 0;
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) { |
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tmp |= glue(ldub, MEMSUFFIX)((uint32_t)T0) << sh; |
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} |
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ugpr(dst) = tmp; |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_lsw_64, MEMSUFFIX) (int dst) |
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{
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uint32_t tmp; |
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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ugpr(dst++) = glue(ldl, MEMSUFFIX)((uint64_t)T0); |
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if (unlikely(dst == 32)) |
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dst = 0;
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} |
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if (unlikely(T1 != 0)) { |
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tmp = 0;
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) { |
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tmp |= glue(ldub, MEMSUFFIX)((uint64_t)T0) << sh; |
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} |
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ugpr(dst) = tmp; |
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} |
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} |
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#endif
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void glue(do_stsw, MEMSUFFIX) (int src) |
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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glue(stl, MEMSUFFIX)((uint32_t)T0, ugpr(src++)); |
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if (unlikely(src == 32)) |
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src = 0;
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} |
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if (unlikely(T1 != 0)) { |
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) |
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glue(stb, MEMSUFFIX)((uint32_t)T0, (ugpr(src) >> sh) & 0xFF);
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_stsw_64, MEMSUFFIX) (int src) |
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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glue(stl, MEMSUFFIX)((uint64_t)T0, ugpr(src++)); |
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if (unlikely(src == 32)) |
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src = 0;
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} |
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if (unlikely(T1 != 0)) { |
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) |
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glue(stb, MEMSUFFIX)((uint64_t)T0, (ugpr(src) >> sh) & 0xFF);
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} |
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} |
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#endif
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void glue(do_lsw_le, MEMSUFFIX) (int dst) |
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{
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uint32_t tmp; |
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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ugpr(dst++) = glue(ld32r, MEMSUFFIX)((uint32_t)T0); |
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if (unlikely(dst == 32)) |
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dst = 0;
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} |
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if (unlikely(T1 != 0)) { |
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tmp = 0;
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) { |
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tmp |= glue(ldub, MEMSUFFIX)((uint32_t)T0) << sh; |
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} |
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ugpr(dst) = tmp; |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_lsw_le_64, MEMSUFFIX) (int dst) |
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{
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uint32_t tmp; |
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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ugpr(dst++) = glue(ld32r, MEMSUFFIX)((uint64_t)T0); |
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if (unlikely(dst == 32)) |
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dst = 0;
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} |
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if (unlikely(T1 != 0)) { |
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tmp = 0;
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) { |
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tmp |= glue(ldub, MEMSUFFIX)((uint64_t)T0) << sh; |
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} |
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ugpr(dst) = tmp; |
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} |
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} |
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#endif
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void glue(do_stsw_le, MEMSUFFIX) (int src) |
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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glue(st32r, MEMSUFFIX)((uint32_t)T0, ugpr(src++)); |
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if (unlikely(src == 32)) |
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src = 0;
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} |
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if (unlikely(T1 != 0)) { |
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) |
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glue(stb, MEMSUFFIX)((uint32_t)T0, (ugpr(src) >> sh) & 0xFF);
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_stsw_le_64, MEMSUFFIX) (int src) |
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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glue(st32r, MEMSUFFIX)((uint64_t)T0, ugpr(src++)); |
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if (unlikely(src == 32)) |
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src = 0;
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} |
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if (unlikely(T1 != 0)) { |
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) |
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glue(stb, MEMSUFFIX)((uint64_t)T0, (ugpr(src) >> sh) & 0xFF);
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} |
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} |
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#endif
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/* Instruction cache invalidation helper */
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void glue(do_icbi, MEMSUFFIX) (void) |
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{
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uint32_t tmp; |
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/* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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*/
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tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0); |
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T0 &= ~(ICACHE_LINE_SIZE - 1);
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tb_invalidate_page_range((uint32_t)T0, (uint32_t)(T0 + ICACHE_LINE_SIZE)); |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_icbi_64, MEMSUFFIX) (void) |
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{
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uint64_t tmp; |
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/* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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*/
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tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0); |
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T0 &= ~(ICACHE_LINE_SIZE - 1);
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tb_invalidate_page_range((uint64_t)T0, (uint64_t)(T0 + ICACHE_LINE_SIZE)); |
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} |
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#endif
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/* PPC 601 specific instructions (POWER bridge) */
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// XXX: to be tested
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void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb) |
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{
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int i, c, d, reg;
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d = 24;
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reg = dest; |
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for (i = 0; i < T1; i++) { |
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c = glue(ldub, MEMSUFFIX)((uint32_t)T0++); |
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/* ra (if not 0) and rb are never modified */
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if (likely(reg != rb && (ra == 0 || reg != ra))) { |
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ugpr(reg) = (ugpr(reg) & ~(0xFF << d)) | (c << d);
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} |
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if (unlikely(c == T2))
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break;
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if (likely(d != 0)) { |
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d -= 8;
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} else {
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d = 24;
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reg++; |
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reg = reg & 0x1F;
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} |
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} |
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T0 = i; |
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} |
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/* XXX: TAGs are not managed */
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void glue(do_POWER2_lfq, MEMSUFFIX) (void) |
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{
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FT0 = glue(ldfq, MEMSUFFIX)((uint32_t)T0); |
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FT1 = glue(ldfq, MEMSUFFIX)((uint32_t)(T0 + 4));
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} |
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static inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA) |
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{
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union {
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double d;
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uint64_t u; |
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} u; |
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u.d = glue(ldfq, MEMSUFFIX)(EA); |
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u.u = ((u.u & 0xFF00000000000000ULL) >> 56) | |
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((u.u & 0x00FF000000000000ULL) >> 40) | |
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((u.u & 0x0000FF0000000000ULL) >> 24) | |
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((u.u & 0x000000FF00000000ULL) >> 8) | |
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((u.u & 0x00000000FF000000ULL) << 8) | |
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((u.u & 0x0000000000FF0000ULL) << 24) | |
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((u.u & 0x000000000000FF00ULL) << 40) | |
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((u.u & 0x00000000000000FFULL) << 56); |
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return u.d;
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} |
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void glue(do_POWER2_lfq_le, MEMSUFFIX) (void) |
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{
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FT0 = glue(ldfqr, MEMSUFFIX)((uint32_t)(T0 + 4));
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FT1 = glue(ldfqr, MEMSUFFIX)((uint32_t)T0); |
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} |
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void glue(do_POWER2_stfq, MEMSUFFIX) (void) |
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{
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glue(stfq, MEMSUFFIX)((uint32_t)T0, FT0); |
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glue(stfq, MEMSUFFIX)((uint32_t)(T0 + 4), FT1);
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} |
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static inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d) |
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{
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union {
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double d;
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uint64_t u; |
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} u; |
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u.d = d; |
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u.u = ((u.u & 0xFF00000000000000ULL) >> 56) | |
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((u.u & 0x00FF000000000000ULL) >> 40) | |
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((u.u & 0x0000FF0000000000ULL) >> 24) | |
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((u.u & 0x000000FF00000000ULL) >> 8) | |
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((u.u & 0x00000000FF000000ULL) << 8) | |
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((u.u & 0x0000000000FF0000ULL) << 24) | |
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((u.u & 0x000000000000FF00ULL) << 40) | |
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((u.u & 0x00000000000000FFULL) << 56); |
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glue(stfq, MEMSUFFIX)(EA, u.d); |
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} |
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void glue(do_POWER2_stfq_le, MEMSUFFIX) (void) |
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{
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glue(stfqr, MEMSUFFIX)((uint32_t)(T0 + 4), FT0);
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glue(stfqr, MEMSUFFIX)((uint32_t)T0, FT1); |
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} |
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#undef MEMSUFFIX
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