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1
/*
2
 *  PowerPC CPU initialization for qemu.
3
 * 
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
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 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20

    
21
/* A lot of PowerPC definition have been included here.
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 * Most of them are not usable for now but have been kept
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 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
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 */
25

    
26
//#define PPC_DUMP_CPU
27
//#define PPC_DEBUG_SPR
28
//#define PPC_DEBUG_IRQ
29

    
30
struct ppc_def_t {
31
    const unsigned char *name;
32
    uint32_t pvr;
33
    uint32_t pvr_mask;
34
    uint64_t insns_flags;
35
    uint32_t flags;
36
    uint64_t msr_mask;
37
};
38

    
39
/* For user-mode emulation, we don't emulate any IRQ controller */
40
#if defined(CONFIG_USER_ONLY)
41
#define PPC_IRQ_INIT_FN(name)                                         \
42
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43
{                                                                     \
44
}
45
#else
46
#define PPC_IRQ_INIT_FN(name)                                         \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48
#endif
49
PPC_IRQ_INIT_FN(405);
50
PPC_IRQ_INIT_FN(6xx);
51
PPC_IRQ_INIT_FN(970);
52

    
53
/* Generic callbacks:
54
 * do nothing but store/retrieve spr value
55
 */
56
static void spr_read_generic (void *opaque, int sprn)
57
{
58
    gen_op_load_spr(sprn);
59
}
60

    
61
static void spr_write_generic (void *opaque, int sprn)
62
{
63
    gen_op_store_spr(sprn);
64
}
65

    
66
static void spr_read_dump (void *opaque, int sprn)
67
{
68
    gen_op_load_dump_spr(sprn);
69
}
70

    
71
static void spr_write_dump (void *opaque, int sprn)
72
{
73
    gen_op_store_dump_spr(sprn);
74
}
75

    
76
#if !defined(CONFIG_USER_ONLY)
77
static void spr_write_clear (void *opaque, int sprn)
78
{
79
    gen_op_mask_spr(sprn);
80
}
81
#endif
82

    
83
/* SPR common to all PowerPC */
84
/* XER */
85
static void spr_read_xer (void *opaque, int sprn)
86
{
87
    gen_op_load_xer();
88
}
89

    
90
static void spr_write_xer (void *opaque, int sprn)
91
{
92
    gen_op_store_xer();
93
}
94

    
95
/* LR */
96
static void spr_read_lr (void *opaque, int sprn)
97
{
98
    gen_op_load_lr();
99
}
100

    
101
static void spr_write_lr (void *opaque, int sprn)
102
{
103
    gen_op_store_lr();
104
}
105

    
106
/* CTR */
107
static void spr_read_ctr (void *opaque, int sprn)
108
{
109
    gen_op_load_ctr();
110
}
111

    
112
static void spr_write_ctr (void *opaque, int sprn)
113
{
114
    gen_op_store_ctr();
115
}
116

    
117
/* User read access to SPR */
118
/* USPRx */
119
/* UMMCRx */
120
/* UPMCx */
121
/* USIA */
122
/* UDECR */
123
static void spr_read_ureg (void *opaque, int sprn)
124
{
125
    gen_op_load_spr(sprn + 0x10);
126
}
127

    
128
/* SPR common to all non-embedded PowerPC */
129
/* DECR */
130
#if !defined(CONFIG_USER_ONLY)
131
static void spr_read_decr (void *opaque, int sprn)
132
{
133
    gen_op_load_decr();
134
}
135

    
136
static void spr_write_decr (void *opaque, int sprn)
137
{
138
    gen_op_store_decr();
139
}
140
#endif
141

    
142
/* SPR common to all non-embedded PowerPC, except 601 */
143
/* Time base */
144
static void spr_read_tbl (void *opaque, int sprn)
145
{
146
    gen_op_load_tbl();
147
}
148

    
149
static void spr_read_tbu (void *opaque, int sprn)
150
{
151
    gen_op_load_tbu();
152
}
153

    
154
#if !defined(CONFIG_USER_ONLY)
155
static void spr_write_tbl (void *opaque, int sprn)
156
{
157
    gen_op_store_tbl();
158
}
159

    
160
static void spr_write_tbu (void *opaque, int sprn)
161
{
162
    gen_op_store_tbu();
163
}
164
#endif
165

    
166
#if !defined(CONFIG_USER_ONLY)
167
/* IBAT0U...IBAT0U */
168
/* IBAT0L...IBAT7L */
169
static void spr_read_ibat (void *opaque, int sprn)
170
{
171
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
172
}
173

    
174
static void spr_read_ibat_h (void *opaque, int sprn)
175
{
176
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
177
}
178

    
179
static void spr_write_ibatu (void *opaque, int sprn)
180
{
181
    DisasContext *ctx = opaque;
182

    
183
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
184
    RET_STOP(ctx);
185
}
186

    
187
static void spr_write_ibatu_h (void *opaque, int sprn)
188
{
189
    DisasContext *ctx = opaque;
190

    
191
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
192
    RET_STOP(ctx);
193
}
194

    
195
static void spr_write_ibatl (void *opaque, int sprn)
196
{
197
    DisasContext *ctx = opaque;
198

    
199
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
200
    RET_STOP(ctx);
201
}
202

    
203
static void spr_write_ibatl_h (void *opaque, int sprn)
204
{
205
    DisasContext *ctx = opaque;
206

    
207
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
208
    RET_STOP(ctx);
209
}
210

    
211
/* DBAT0U...DBAT7U */
212
/* DBAT0L...DBAT7L */
213
static void spr_read_dbat (void *opaque, int sprn)
214
{
215
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
216
}
217

    
218
static void spr_read_dbat_h (void *opaque, int sprn)
219
{
220
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
221
}
222

    
223
static void spr_write_dbatu (void *opaque, int sprn)
224
{
225
    DisasContext *ctx = opaque;
226

    
227
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
228
    RET_STOP(ctx);
229
}
230

    
231
static void spr_write_dbatu_h (void *opaque, int sprn)
232
{
233
    DisasContext *ctx = opaque;
234

    
235
    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
236
    RET_STOP(ctx);
237
}
238

    
239
static void spr_write_dbatl (void *opaque, int sprn)
240
{
241
    DisasContext *ctx = opaque;
242

    
243
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
244
    RET_STOP(ctx);
245
}
246

    
247
static void spr_write_dbatl_h (void *opaque, int sprn)
248
{
249
    DisasContext *ctx = opaque;
250

    
251
    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
252
    RET_STOP(ctx);
253
}
254

    
255
/* SDR1 */
256
static void spr_read_sdr1 (void *opaque, int sprn)
257
{
258
    gen_op_load_sdr1();
259
}
260

    
261
static void spr_write_sdr1 (void *opaque, int sprn)
262
{
263
    DisasContext *ctx = opaque;
264

    
265
    gen_op_store_sdr1();
266
    RET_STOP(ctx);
267
}
268

    
269
/* 64 bits PowerPC specific SPRs */
270
/* ASR */
271
#if defined(TARGET_PPC64)
272
static void spr_read_asr (void *opaque, int sprn)
273
{
274
    gen_op_load_asr();
275
}
276

    
277
static void spr_write_asr (void *opaque, int sprn)
278
{
279
    DisasContext *ctx = opaque;
280

    
281
    gen_op_store_asr();
282
    RET_STOP(ctx);
283
}
284
#endif
285
#endif /* !defined(CONFIG_USER_ONLY) */
286

    
287
/* PowerPC 601 specific registers */
288
/* RTC */
289
static void spr_read_601_rtcl (void *opaque, int sprn)
290
{
291
    gen_op_load_601_rtcl();
292
}
293

    
294
static void spr_read_601_rtcu (void *opaque, int sprn)
295
{
296
    gen_op_load_601_rtcu();
297
}
298

    
299
#if !defined(CONFIG_USER_ONLY)
300
static void spr_write_601_rtcu (void *opaque, int sprn)
301
{
302
    gen_op_store_601_rtcu();
303
}
304

    
305
static void spr_write_601_rtcl (void *opaque, int sprn)
306
{
307
    gen_op_store_601_rtcl();
308
}
309
#endif
310

    
311
/* Unified bats */
312
#if !defined(CONFIG_USER_ONLY)
313
static void spr_read_601_ubat (void *opaque, int sprn)
314
{
315
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
316
}
317

    
318
static void spr_write_601_ubatu (void *opaque, int sprn)
319
{
320
    DisasContext *ctx = opaque;
321

    
322
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
323
    RET_STOP(ctx);
324
}
325

    
326
static void spr_write_601_ubatl (void *opaque, int sprn)
327
{
328
    DisasContext *ctx = opaque;
329

    
330
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
331
    RET_STOP(ctx);
332
}
333
#endif
334

    
335
/* PowerPC 40x specific registers */
336
#if !defined(CONFIG_USER_ONLY)
337
static void spr_read_40x_pit (void *opaque, int sprn)
338
{
339
    gen_op_load_40x_pit();
340
}
341

    
342
static void spr_write_40x_pit (void *opaque, int sprn)
343
{
344
    gen_op_store_40x_pit();
345
}
346

    
347
static void spr_write_booke_tcr (void *opaque, int sprn)
348
{
349
    gen_op_store_booke_tcr();
350
}
351

    
352
static void spr_write_booke_tsr (void *opaque, int sprn)
353
{
354
    gen_op_store_booke_tsr();
355
}
356
#endif
357

    
358
/* PowerPC 403 specific registers */
359
/* PBL1 / PBU1 / PBL2 / PBU2 */
360
#if !defined(CONFIG_USER_ONLY)
361
static void spr_read_403_pbr (void *opaque, int sprn)
362
{
363
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
364
}
365

    
366
static void spr_write_403_pbr (void *opaque, int sprn)
367
{
368
    DisasContext *ctx = opaque;
369

    
370
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
371
    RET_STOP(ctx);
372
}
373

    
374
static void spr_write_pir (void *opaque, int sprn)
375
{
376
    gen_op_store_pir();
377
}
378
#endif
379

    
380
#if defined(CONFIG_USER_ONLY)
381
#define spr_register(env, num, name, uea_read, uea_write,                     \
382
                     oea_read, oea_write, initial_value)                      \
383
do {                                                                          \
384
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
385
} while (0)
386
static inline void _spr_register (CPUPPCState *env, int num,
387
                                  const unsigned char *name,
388
                                  void (*uea_read)(void *opaque, int sprn),
389
                                  void (*uea_write)(void *opaque, int sprn),
390
                                  target_ulong initial_value)
391
#else
392
static inline void spr_register (CPUPPCState *env, int num,
393
                                 const unsigned char *name,
394
                                 void (*uea_read)(void *opaque, int sprn),
395
                                 void (*uea_write)(void *opaque, int sprn),
396
                                 void (*oea_read)(void *opaque, int sprn),
397
                                 void (*oea_write)(void *opaque, int sprn),
398
                                 target_ulong initial_value)
399
#endif
400
{
401
    ppc_spr_t *spr;
402

    
403
    spr = &env->spr_cb[num];
404
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
405
#if !defined(CONFIG_USER_ONLY)
406
        spr->oea_read != NULL || spr->oea_write != NULL ||
407
#endif
408
        spr->uea_read != NULL || spr->uea_write != NULL) {
409
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
410
        exit(1);
411
    }
412
#if defined(PPC_DEBUG_SPR)
413
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
414
           initial_value);
415
#endif
416
    spr->name = name;
417
    spr->uea_read = uea_read;
418
    spr->uea_write = uea_write;
419
#if !defined(CONFIG_USER_ONLY)
420
    spr->oea_read = oea_read;
421
    spr->oea_write = oea_write;
422
#endif
423
    env->spr[num] = initial_value;
424
}
425

    
426
/* Generic PowerPC SPRs */
427
static void gen_spr_generic (CPUPPCState *env)
428
{
429
    /* Integer processing */
430
    spr_register(env, SPR_XER, "XER",
431
                 &spr_read_xer, &spr_write_xer,
432
                 &spr_read_xer, &spr_write_xer,
433
                 0x00000000);
434
    /* Branch contol */
435
    spr_register(env, SPR_LR, "LR",
436
                 &spr_read_lr, &spr_write_lr,
437
                 &spr_read_lr, &spr_write_lr,
438
                 0x00000000);
439
    spr_register(env, SPR_CTR, "CTR",
440
                 &spr_read_ctr, &spr_write_ctr,
441
                 &spr_read_ctr, &spr_write_ctr,
442
                 0x00000000);
443
    /* Interrupt processing */
444
    spr_register(env, SPR_SRR0, "SRR0",
445
                 SPR_NOACCESS, SPR_NOACCESS,
446
                 &spr_read_generic, &spr_write_generic,
447
                 0x00000000);
448
    spr_register(env, SPR_SRR1, "SRR1",
449
                 SPR_NOACCESS, SPR_NOACCESS,
450
                 &spr_read_generic, &spr_write_generic,
451
                 0x00000000);
452
    /* Processor control */
453
    spr_register(env, SPR_SPRG0, "SPRG0",
454
                 SPR_NOACCESS, SPR_NOACCESS,
455
                 &spr_read_generic, &spr_write_generic,
456
                 0x00000000);
457
    spr_register(env, SPR_SPRG1, "SPRG1",
458
                 SPR_NOACCESS, SPR_NOACCESS,
459
                 &spr_read_generic, &spr_write_generic,
460
                 0x00000000);
461
    spr_register(env, SPR_SPRG2, "SPRG2",
462
                 SPR_NOACCESS, SPR_NOACCESS,
463
                 &spr_read_generic, &spr_write_generic,
464
                 0x00000000);
465
    spr_register(env, SPR_SPRG3, "SPRG3",
466
                 SPR_NOACCESS, SPR_NOACCESS,
467
                 &spr_read_generic, &spr_write_generic,
468
                 0x00000000);
469
}
470

    
471
/* SPR common to all non-embedded PowerPC, including 601 */
472
static void gen_spr_ne_601 (CPUPPCState *env)
473
{
474
    /* Exception processing */
475
    spr_register(env, SPR_DSISR, "DSISR",
476
                 SPR_NOACCESS, SPR_NOACCESS,
477
                 &spr_read_generic, &spr_write_generic,
478
                 0x00000000);
479
    spr_register(env, SPR_DAR, "DAR",
480
                 SPR_NOACCESS, SPR_NOACCESS,
481
                 &spr_read_generic, &spr_write_generic,
482
                 0x00000000);
483
    /* Timer */
484
    spr_register(env, SPR_DECR, "DECR",
485
                 SPR_NOACCESS, SPR_NOACCESS,
486
                 &spr_read_decr, &spr_write_decr,
487
                 0x00000000);
488
    /* Memory management */
489
    spr_register(env, SPR_SDR1, "SDR1",
490
                 SPR_NOACCESS, SPR_NOACCESS,
491
                 &spr_read_sdr1, &spr_write_sdr1,
492
                 0x00000000);
493
}
494

    
495
/* BATs 0-3 */
496
static void gen_low_BATs (CPUPPCState *env)
497
{
498
    spr_register(env, SPR_IBAT0U, "IBAT0U",
499
                 SPR_NOACCESS, SPR_NOACCESS,
500
                 &spr_read_ibat, &spr_write_ibatu,
501
                 0x00000000);
502
    spr_register(env, SPR_IBAT0L, "IBAT0L",
503
                 SPR_NOACCESS, SPR_NOACCESS,
504
                 &spr_read_ibat, &spr_write_ibatl,
505
                 0x00000000);
506
    spr_register(env, SPR_IBAT1U, "IBAT1U",
507
                 SPR_NOACCESS, SPR_NOACCESS,
508
                 &spr_read_ibat, &spr_write_ibatu,
509
                 0x00000000);
510
    spr_register(env, SPR_IBAT1L, "IBAT1L",
511
                 SPR_NOACCESS, SPR_NOACCESS,
512
                 &spr_read_ibat, &spr_write_ibatl,
513
                 0x00000000);
514
    spr_register(env, SPR_IBAT2U, "IBAT2U",
515
                 SPR_NOACCESS, SPR_NOACCESS,
516
                 &spr_read_ibat, &spr_write_ibatu,
517
                 0x00000000);
518
    spr_register(env, SPR_IBAT2L, "IBAT2L",
519
                 SPR_NOACCESS, SPR_NOACCESS,
520
                 &spr_read_ibat, &spr_write_ibatl,
521
                 0x00000000);
522
    spr_register(env, SPR_IBAT3U, "IBAT3U",
523
                 SPR_NOACCESS, SPR_NOACCESS,
524
                 &spr_read_ibat, &spr_write_ibatu,
525
                 0x00000000);
526
    spr_register(env, SPR_IBAT3L, "IBAT3L",
527
                 SPR_NOACCESS, SPR_NOACCESS,
528
                 &spr_read_ibat, &spr_write_ibatl,
529
                 0x00000000);
530
    spr_register(env, SPR_DBAT0U, "DBAT0U",
531
                 SPR_NOACCESS, SPR_NOACCESS,
532
                 &spr_read_dbat, &spr_write_dbatu,
533
                 0x00000000);
534
    spr_register(env, SPR_DBAT0L, "DBAT0L",
535
                 SPR_NOACCESS, SPR_NOACCESS,
536
                 &spr_read_dbat, &spr_write_dbatl,
537
                 0x00000000);
538
    spr_register(env, SPR_DBAT1U, "DBAT1U",
539
                 SPR_NOACCESS, SPR_NOACCESS,
540
                 &spr_read_dbat, &spr_write_dbatu,
541
                 0x00000000);
542
    spr_register(env, SPR_DBAT1L, "DBAT1L",
543
                 SPR_NOACCESS, SPR_NOACCESS,
544
                 &spr_read_dbat, &spr_write_dbatl,
545
                 0x00000000);
546
    spr_register(env, SPR_DBAT2U, "DBAT2U",
547
                 SPR_NOACCESS, SPR_NOACCESS,
548
                 &spr_read_dbat, &spr_write_dbatu,
549
                 0x00000000);
550
    spr_register(env, SPR_DBAT2L, "DBAT2L",
551
                 SPR_NOACCESS, SPR_NOACCESS,
552
                 &spr_read_dbat, &spr_write_dbatl,
553
                 0x00000000);
554
    spr_register(env, SPR_DBAT3U, "DBAT3U",
555
                 SPR_NOACCESS, SPR_NOACCESS,
556
                 &spr_read_dbat, &spr_write_dbatu,
557
                 0x00000000);
558
    spr_register(env, SPR_DBAT3L, "DBAT3L",
559
                 SPR_NOACCESS, SPR_NOACCESS,
560
                 &spr_read_dbat, &spr_write_dbatl,
561
                 0x00000000);
562
    env->nb_BATs = 4;
563
}
564

    
565
/* BATs 4-7 */
566
static void gen_high_BATs (CPUPPCState *env)
567
{
568
    spr_register(env, SPR_IBAT4U, "IBAT4U",
569
                 SPR_NOACCESS, SPR_NOACCESS,
570
                 &spr_read_ibat_h, &spr_write_ibatu_h,
571
                 0x00000000);
572
    spr_register(env, SPR_IBAT4L, "IBAT4L",
573
                 SPR_NOACCESS, SPR_NOACCESS,
574
                 &spr_read_ibat_h, &spr_write_ibatl_h,
575
                 0x00000000);
576
    spr_register(env, SPR_IBAT5U, "IBAT5U",
577
                 SPR_NOACCESS, SPR_NOACCESS,
578
                 &spr_read_ibat_h, &spr_write_ibatu_h,
579
                 0x00000000);
580
    spr_register(env, SPR_IBAT5L, "IBAT5L",
581
                 SPR_NOACCESS, SPR_NOACCESS,
582
                 &spr_read_ibat_h, &spr_write_ibatl_h,
583
                 0x00000000);
584
    spr_register(env, SPR_IBAT6U, "IBAT6U",
585
                 SPR_NOACCESS, SPR_NOACCESS,
586
                 &spr_read_ibat_h, &spr_write_ibatu_h,
587
                 0x00000000);
588
    spr_register(env, SPR_IBAT6L, "IBAT6L",
589
                 SPR_NOACCESS, SPR_NOACCESS,
590
                 &spr_read_ibat_h, &spr_write_ibatl_h,
591
                 0x00000000);
592
    spr_register(env, SPR_IBAT7U, "IBAT7U",
593
                 SPR_NOACCESS, SPR_NOACCESS,
594
                 &spr_read_ibat_h, &spr_write_ibatu_h,
595
                 0x00000000);
596
    spr_register(env, SPR_IBAT7L, "IBAT7L",
597
                 SPR_NOACCESS, SPR_NOACCESS,
598
                 &spr_read_ibat_h, &spr_write_ibatl_h,
599
                 0x00000000);
600
    spr_register(env, SPR_DBAT4U, "DBAT4U",
601
                 SPR_NOACCESS, SPR_NOACCESS,
602
                 &spr_read_dbat_h, &spr_write_dbatu_h,
603
                 0x00000000);
604
    spr_register(env, SPR_DBAT4L, "DBAT4L",
605
                 SPR_NOACCESS, SPR_NOACCESS,
606
                 &spr_read_dbat_h, &spr_write_dbatl_h,
607
                 0x00000000);
608
    spr_register(env, SPR_DBAT5U, "DBAT5U",
609
                 SPR_NOACCESS, SPR_NOACCESS,
610
                 &spr_read_dbat_h, &spr_write_dbatu_h,
611
                 0x00000000);
612
    spr_register(env, SPR_DBAT5L, "DBAT5L",
613
                 SPR_NOACCESS, SPR_NOACCESS,
614
                 &spr_read_dbat_h, &spr_write_dbatl_h,
615
                 0x00000000);
616
    spr_register(env, SPR_DBAT6U, "DBAT6U",
617
                 SPR_NOACCESS, SPR_NOACCESS,
618
                 &spr_read_dbat_h, &spr_write_dbatu_h,
619
                 0x00000000);
620
    spr_register(env, SPR_DBAT6L, "DBAT6L",
621
                 SPR_NOACCESS, SPR_NOACCESS,
622
                 &spr_read_dbat_h, &spr_write_dbatl_h,
623
                 0x00000000);
624
    spr_register(env, SPR_DBAT7U, "DBAT7U",
625
                 SPR_NOACCESS, SPR_NOACCESS,
626
                 &spr_read_dbat_h, &spr_write_dbatu_h,
627
                 0x00000000);
628
    spr_register(env, SPR_DBAT7L, "DBAT7L",
629
                 SPR_NOACCESS, SPR_NOACCESS,
630
                 &spr_read_dbat_h, &spr_write_dbatl_h,
631
                 0x00000000);
632
    env->nb_BATs = 8;
633
}
634

    
635
/* Generic PowerPC time base */
636
static void gen_tbl (CPUPPCState *env)
637
{
638
    spr_register(env, SPR_VTBL,  "TBL",
639
                 &spr_read_tbl, SPR_NOACCESS,
640
                 &spr_read_tbl, SPR_NOACCESS,
641
                 0x00000000);
642
    spr_register(env, SPR_TBL,   "TBL",
643
                 SPR_NOACCESS, SPR_NOACCESS,
644
                 SPR_NOACCESS, &spr_write_tbl,
645
                 0x00000000);
646
    spr_register(env, SPR_VTBU,  "TBU",
647
                 &spr_read_tbu, SPR_NOACCESS,
648
                 &spr_read_tbu, SPR_NOACCESS,
649
                 0x00000000);
650
    spr_register(env, SPR_TBU,   "TBU",
651
                 SPR_NOACCESS, SPR_NOACCESS,
652
                 SPR_NOACCESS, &spr_write_tbu,
653
                 0x00000000);
654
}
655

    
656
/* Softare table search registers */
657
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
658
{
659
    env->nb_tlb = nb_tlbs;
660
    env->nb_ways = nb_ways;
661
    env->id_tlbs = 1;
662
    spr_register(env, SPR_DMISS, "DMISS",
663
                 SPR_NOACCESS, SPR_NOACCESS,
664
                 &spr_read_generic, SPR_NOACCESS,
665
                 0x00000000);
666
    spr_register(env, SPR_DCMP, "DCMP",
667
                 SPR_NOACCESS, SPR_NOACCESS,
668
                 &spr_read_generic, SPR_NOACCESS,
669
                 0x00000000);
670
    spr_register(env, SPR_HASH1, "HASH1",
671
                 SPR_NOACCESS, SPR_NOACCESS,
672
                 &spr_read_generic, SPR_NOACCESS,
673
                 0x00000000);
674
    spr_register(env, SPR_HASH2, "HASH2",
675
                 SPR_NOACCESS, SPR_NOACCESS,
676
                 &spr_read_generic, SPR_NOACCESS,
677
                 0x00000000);
678
    spr_register(env, SPR_IMISS, "IMISS",
679
                 SPR_NOACCESS, SPR_NOACCESS,
680
                 &spr_read_generic, SPR_NOACCESS,
681
                 0x00000000);
682
    spr_register(env, SPR_ICMP, "ICMP",
683
                 SPR_NOACCESS, SPR_NOACCESS,
684
                 &spr_read_generic, SPR_NOACCESS,
685
                 0x00000000);
686
    spr_register(env, SPR_RPA, "RPA",
687
                 SPR_NOACCESS, SPR_NOACCESS,
688
                 &spr_read_generic, &spr_write_generic,
689
                 0x00000000);
690
}
691

    
692
/* SPR common to MPC755 and G2 */
693
static void gen_spr_G2_755 (CPUPPCState *env)
694
{
695
    /* SGPRs */
696
    spr_register(env, SPR_SPRG4, "SPRG4",
697
                 SPR_NOACCESS, SPR_NOACCESS,
698
                 &spr_read_generic, &spr_write_generic,
699
                 0x00000000);
700
    spr_register(env, SPR_SPRG5, "SPRG5",
701
                 SPR_NOACCESS, SPR_NOACCESS,
702
                 &spr_read_generic, &spr_write_generic,
703
                 0x00000000);
704
    spr_register(env, SPR_SPRG6, "SPRG6",
705
                 SPR_NOACCESS, SPR_NOACCESS,
706
                 &spr_read_generic, &spr_write_generic,
707
                 0x00000000);
708
    spr_register(env, SPR_SPRG7, "SPRG7",
709
                 SPR_NOACCESS, SPR_NOACCESS,
710
                 &spr_read_generic, &spr_write_generic,
711
                 0x00000000);
712
    /* External access control */
713
    /* XXX : not implemented */
714
    spr_register(env, SPR_EAR, "EAR",
715
                 SPR_NOACCESS, SPR_NOACCESS,
716
                 &spr_read_generic, &spr_write_generic,
717
                 0x00000000);
718
}
719

    
720
/* SPR common to all 7xx PowerPC implementations */
721
static void gen_spr_7xx (CPUPPCState *env)
722
{
723
    /* Breakpoints */
724
    /* XXX : not implemented */
725
    spr_register(env, SPR_DABR, "DABR",
726
                 SPR_NOACCESS, SPR_NOACCESS,
727
                 &spr_read_generic, &spr_write_generic,
728
                 0x00000000);
729
    /* XXX : not implemented */
730
    spr_register(env, SPR_IABR, "IABR",
731
                 SPR_NOACCESS, SPR_NOACCESS,
732
                 &spr_read_generic, &spr_write_generic,
733
                 0x00000000);
734
    /* Cache management */
735
    /* XXX : not implemented */
736
    spr_register(env, SPR_ICTC, "ICTC",
737
                 SPR_NOACCESS, SPR_NOACCESS,
738
                 &spr_read_generic, &spr_write_generic,
739
                 0x00000000);
740
    /* XXX : not implemented */
741
    spr_register(env, SPR_L2CR, "L2CR",
742
                 SPR_NOACCESS, SPR_NOACCESS,
743
                 &spr_read_generic, &spr_write_generic,
744
                 0x00000000);
745
    /* Performance monitors */
746
    /* XXX : not implemented */
747
    spr_register(env, SPR_MMCR0, "MMCR0",
748
                 SPR_NOACCESS, SPR_NOACCESS,
749
                 &spr_read_generic, &spr_write_generic,
750
                 0x00000000);
751
    /* XXX : not implemented */
752
    spr_register(env, SPR_MMCR1, "MMCR1",
753
                 SPR_NOACCESS, SPR_NOACCESS,
754
                 &spr_read_generic, &spr_write_generic,
755
                 0x00000000);
756
    /* XXX : not implemented */
757
    spr_register(env, SPR_PMC1, "PMC1",
758
                 SPR_NOACCESS, SPR_NOACCESS,
759
                 &spr_read_generic, &spr_write_generic,
760
                 0x00000000);
761
    /* XXX : not implemented */
762
    spr_register(env, SPR_PMC2, "PMC2",
763
                 SPR_NOACCESS, SPR_NOACCESS,
764
                 &spr_read_generic, &spr_write_generic,
765
                 0x00000000);
766
    /* XXX : not implemented */
767
    spr_register(env, SPR_PMC3, "PMC3",
768
                 SPR_NOACCESS, SPR_NOACCESS,
769
                 &spr_read_generic, &spr_write_generic,
770
                 0x00000000);
771
    /* XXX : not implemented */
772
    spr_register(env, SPR_PMC4, "PMC4",
773
                 SPR_NOACCESS, SPR_NOACCESS,
774
                 &spr_read_generic, &spr_write_generic,
775
                 0x00000000);
776
    /* XXX : not implemented */
777
    spr_register(env, SPR_SIA, "SIA",
778
                 SPR_NOACCESS, SPR_NOACCESS,
779
                 &spr_read_generic, SPR_NOACCESS,
780
                 0x00000000);
781
    spr_register(env, SPR_UMMCR0, "UMMCR0",
782
                 &spr_read_ureg, SPR_NOACCESS,
783
                 &spr_read_ureg, SPR_NOACCESS,
784
                 0x00000000);
785
    spr_register(env, SPR_UMMCR1, "UMMCR1",
786
                 &spr_read_ureg, SPR_NOACCESS,
787
                 &spr_read_ureg, SPR_NOACCESS,
788
                 0x00000000);
789
    spr_register(env, SPR_UPMC1, "UPMC1",
790
                 &spr_read_ureg, SPR_NOACCESS,
791
                 &spr_read_ureg, SPR_NOACCESS,
792
                 0x00000000);
793
    spr_register(env, SPR_UPMC2, "UPMC2",
794
                 &spr_read_ureg, SPR_NOACCESS,
795
                 &spr_read_ureg, SPR_NOACCESS,
796
                 0x00000000);
797
    spr_register(env, SPR_UPMC3, "UPMC3",
798
                 &spr_read_ureg, SPR_NOACCESS,
799
                 &spr_read_ureg, SPR_NOACCESS,
800
                 0x00000000);
801
    spr_register(env, SPR_UPMC4, "UPMC4",
802
                 &spr_read_ureg, SPR_NOACCESS,
803
                 &spr_read_ureg, SPR_NOACCESS,
804
                 0x00000000);
805
    spr_register(env, SPR_USIA, "USIA",
806
                 &spr_read_ureg, SPR_NOACCESS,
807
                 &spr_read_ureg, SPR_NOACCESS,
808
                 0x00000000);
809
    /* Thermal management */
810
    /* XXX : not implemented */
811
    spr_register(env, SPR_THRM1, "THRM1",
812
                 SPR_NOACCESS, SPR_NOACCESS,
813
                 &spr_read_generic, &spr_write_generic,
814
                 0x00000000);
815
    /* XXX : not implemented */
816
    spr_register(env, SPR_THRM2, "THRM2",
817
                 SPR_NOACCESS, SPR_NOACCESS,
818
                 &spr_read_generic, &spr_write_generic,
819
                 0x00000000);
820
    /* XXX : not implemented */
821
    spr_register(env, SPR_THRM3, "THRM3",
822
                 SPR_NOACCESS, SPR_NOACCESS,
823
                 &spr_read_generic, &spr_write_generic,
824
                 0x00000000);
825
    /* External access control */
826
    /* XXX : not implemented */
827
    spr_register(env, SPR_EAR, "EAR",
828
                 SPR_NOACCESS, SPR_NOACCESS,
829
                 &spr_read_generic, &spr_write_generic,
830
                 0x00000000);
831
}
832

    
833
/* SPR specific to PowerPC 604 implementation */
834
static void gen_spr_604 (CPUPPCState *env)
835
{
836
    /* Processor identification */
837
    spr_register(env, SPR_PIR, "PIR",
838
                 SPR_NOACCESS, SPR_NOACCESS,
839
                 &spr_read_generic, &spr_write_pir,
840
                 0x00000000);
841
    /* Breakpoints */
842
    /* XXX : not implemented */
843
    spr_register(env, SPR_IABR, "IABR",
844
                 SPR_NOACCESS, SPR_NOACCESS,
845
                 &spr_read_generic, &spr_write_generic,
846
                 0x00000000);
847
    /* XXX : not implemented */
848
    spr_register(env, SPR_DABR, "DABR",
849
                 SPR_NOACCESS, SPR_NOACCESS,
850
                 &spr_read_generic, &spr_write_generic,
851
                 0x00000000);
852
    /* Performance counters */
853
    /* XXX : not implemented */
854
    spr_register(env, SPR_MMCR0, "MMCR0",
855
                 SPR_NOACCESS, SPR_NOACCESS,
856
                 &spr_read_generic, &spr_write_generic,
857
                 0x00000000);
858
    /* XXX : not implemented */
859
    spr_register(env, SPR_MMCR1, "MMCR1",
860
                 SPR_NOACCESS, SPR_NOACCESS,
861
                 &spr_read_generic, &spr_write_generic,
862
                 0x00000000);
863
    /* XXX : not implemented */
864
    spr_register(env, SPR_PMC1, "PMC1",
865
                 SPR_NOACCESS, SPR_NOACCESS,
866
                 &spr_read_generic, &spr_write_generic,
867
                 0x00000000);
868
    /* XXX : not implemented */
869
    spr_register(env, SPR_PMC2, "PMC2",
870
                 SPR_NOACCESS, SPR_NOACCESS,
871
                 &spr_read_generic, &spr_write_generic,
872
                 0x00000000);
873
    /* XXX : not implemented */
874
    spr_register(env, SPR_PMC3, "PMC3",
875
                 SPR_NOACCESS, SPR_NOACCESS,
876
                 &spr_read_generic, &spr_write_generic,
877
                 0x00000000);
878
    /* XXX : not implemented */
879
    spr_register(env, SPR_PMC4, "PMC4",
880
                 SPR_NOACCESS, SPR_NOACCESS,
881
                 &spr_read_generic, &spr_write_generic,
882
                 0x00000000);
883
    /* XXX : not implemented */
884
    spr_register(env, SPR_SIA, "SIA",
885
                 SPR_NOACCESS, SPR_NOACCESS,
886
                 &spr_read_generic, SPR_NOACCESS,
887
                 0x00000000);
888
    /* XXX : not implemented */
889
    spr_register(env, SPR_SDA, "SDA",
890
                 SPR_NOACCESS, SPR_NOACCESS,
891
                 &spr_read_generic, SPR_NOACCESS,
892
                 0x00000000);
893
    /* External access control */
894
    /* XXX : not implemented */
895
    spr_register(env, SPR_EAR, "EAR",
896
                 SPR_NOACCESS, SPR_NOACCESS,
897
                 &spr_read_generic, &spr_write_generic,
898
                 0x00000000);
899
}
900

    
901
/* SPR specific to PowerPC 603 implementation */
902
static void gen_spr_603 (CPUPPCState *env)
903
{
904
    /* External access control */
905
    /* XXX : not implemented */
906
    spr_register(env, SPR_EAR, "EAR",
907
                 SPR_NOACCESS, SPR_NOACCESS,
908
                 &spr_read_generic, &spr_write_generic,
909
                 0x00000000);
910
}
911

    
912
/* SPR specific to PowerPC G2 implementation */
913
static void gen_spr_G2 (CPUPPCState *env)
914
{
915
    /* Memory base address */
916
    /* MBAR */
917
    spr_register(env, SPR_MBAR, "MBAR",
918
                 SPR_NOACCESS, SPR_NOACCESS,
919
                 &spr_read_generic, &spr_write_generic,
920
                 0x00000000);
921
    /* System version register */
922
    /* SVR */
923
    spr_register(env, SPR_SVR, "SVR",
924
                 SPR_NOACCESS, SPR_NOACCESS,
925
                 &spr_read_generic, SPR_NOACCESS,
926
                 0x00000000);
927
    /* Exception processing */
928
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
929
                 SPR_NOACCESS, SPR_NOACCESS,
930
                 &spr_read_generic, &spr_write_generic,
931
                 0x00000000);
932
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
933
                 SPR_NOACCESS, SPR_NOACCESS,
934
                 &spr_read_generic, &spr_write_generic,
935
                 0x00000000);
936
    /* Breakpoints */
937
    /* XXX : not implemented */
938
    spr_register(env, SPR_DABR, "DABR",
939
                 SPR_NOACCESS, SPR_NOACCESS,
940
                 &spr_read_generic, &spr_write_generic,
941
                 0x00000000);
942
    /* XXX : not implemented */
943
    spr_register(env, SPR_DABR2, "DABR2",
944
                 SPR_NOACCESS, SPR_NOACCESS,
945
                 &spr_read_generic, &spr_write_generic,
946
                 0x00000000);
947
    /* XXX : not implemented */
948
    spr_register(env, SPR_IABR, "IABR",
949
                 SPR_NOACCESS, SPR_NOACCESS,
950
                 &spr_read_generic, &spr_write_generic,
951
                 0x00000000);
952
    /* XXX : not implemented */
953
    spr_register(env, SPR_IABR2, "IABR2",
954
                 SPR_NOACCESS, SPR_NOACCESS,
955
                 &spr_read_generic, &spr_write_generic,
956
                 0x00000000);
957
    /* XXX : not implemented */
958
    spr_register(env, SPR_IBCR, "IBCR",
959
                 SPR_NOACCESS, SPR_NOACCESS,
960
                 &spr_read_generic, &spr_write_generic,
961
                 0x00000000);
962
    /* XXX : not implemented */
963
    spr_register(env, SPR_DBCR, "DBCR",
964
                 SPR_NOACCESS, SPR_NOACCESS,
965
                 &spr_read_generic, &spr_write_generic,
966
                 0x00000000);
967
}
968

    
969
/* SPR specific to PowerPC 602 implementation */
970
static void gen_spr_602 (CPUPPCState *env)
971
{
972
    /* ESA registers */
973
    /* XXX : not implemented */
974
    spr_register(env, SPR_SER, "SER",
975
                 SPR_NOACCESS, SPR_NOACCESS,
976
                 &spr_read_generic, &spr_write_generic,
977
                 0x00000000);
978
    /* XXX : not implemented */
979
    spr_register(env, SPR_SEBR, "SEBR",
980
                 SPR_NOACCESS, SPR_NOACCESS,
981
                 &spr_read_generic, &spr_write_generic,
982
                 0x00000000);
983
    /* XXX : not implemented */
984
    spr_register(env, SPR_ESASR, "ESASR",
985
                 SPR_NOACCESS, SPR_NOACCESS,
986
                 &spr_read_generic, &spr_write_generic,
987
                 0x00000000);
988
    /* Floating point status */
989
    /* XXX : not implemented */
990
    spr_register(env, SPR_SP, "SP",
991
                 SPR_NOACCESS, SPR_NOACCESS,
992
                 &spr_read_generic, &spr_write_generic,
993
                 0x00000000);
994
    /* XXX : not implemented */
995
    spr_register(env, SPR_LT, "LT",
996
                 SPR_NOACCESS, SPR_NOACCESS,
997
                 &spr_read_generic, &spr_write_generic,
998
                 0x00000000);
999
    /* Watchdog timer */
1000
    /* XXX : not implemented */
1001
    spr_register(env, SPR_TCR, "TCR",
1002
                 SPR_NOACCESS, SPR_NOACCESS,
1003
                 &spr_read_generic, &spr_write_generic,
1004
                 0x00000000);
1005
    /* Interrupt base */
1006
    spr_register(env, SPR_IBR, "IBR",
1007
                 SPR_NOACCESS, SPR_NOACCESS,
1008
                 &spr_read_generic, &spr_write_generic,
1009
                 0x00000000);
1010
}
1011

    
1012
/* SPR specific to PowerPC 601 implementation */
1013
static void gen_spr_601 (CPUPPCState *env)
1014
{
1015
    /* Multiplication/division register */
1016
    /* MQ */
1017
    spr_register(env, SPR_MQ, "MQ",
1018
                 &spr_read_generic, &spr_write_generic,
1019
                 &spr_read_generic, &spr_write_generic,
1020
                 0x00000000);
1021
    /* RTC registers */
1022
    spr_register(env, SPR_601_RTCU, "RTCU",
1023
                 SPR_NOACCESS, SPR_NOACCESS,
1024
                 SPR_NOACCESS, &spr_write_601_rtcu,
1025
                 0x00000000);
1026
    spr_register(env, SPR_601_VRTCU, "RTCU",
1027
                 &spr_read_601_rtcu, SPR_NOACCESS,
1028
                 &spr_read_601_rtcu, SPR_NOACCESS,
1029
                 0x00000000);
1030
    spr_register(env, SPR_601_RTCL, "RTCL",
1031
                 SPR_NOACCESS, SPR_NOACCESS,
1032
                 SPR_NOACCESS, &spr_write_601_rtcl,
1033
                 0x00000000);
1034
    spr_register(env, SPR_601_VRTCL, "RTCL",
1035
                 &spr_read_601_rtcl, SPR_NOACCESS,
1036
                 &spr_read_601_rtcl, SPR_NOACCESS,
1037
                 0x00000000);
1038
    /* Timer */
1039
#if 0 /* ? */
1040
    spr_register(env, SPR_601_UDECR, "UDECR",
1041
                 &spr_read_decr, SPR_NOACCESS,
1042
                 &spr_read_decr, SPR_NOACCESS,
1043
                 0x00000000);
1044
#endif
1045
    /* External access control */
1046
    /* XXX : not implemented */
1047
    spr_register(env, SPR_EAR, "EAR",
1048
                 SPR_NOACCESS, SPR_NOACCESS,
1049
                 &spr_read_generic, &spr_write_generic,
1050
                 0x00000000);
1051
    /* Memory management */
1052
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1053
                 SPR_NOACCESS, SPR_NOACCESS,
1054
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1055
                 0x00000000);
1056
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1057
                 SPR_NOACCESS, SPR_NOACCESS,
1058
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1059
                 0x00000000);
1060
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1061
                 SPR_NOACCESS, SPR_NOACCESS,
1062
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1063
                 0x00000000);
1064
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1065
                 SPR_NOACCESS, SPR_NOACCESS,
1066
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1067
                 0x00000000);
1068
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1069
                 SPR_NOACCESS, SPR_NOACCESS,
1070
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1071
                 0x00000000);
1072
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1073
                 SPR_NOACCESS, SPR_NOACCESS,
1074
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1075
                 0x00000000);
1076
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1077
                 SPR_NOACCESS, SPR_NOACCESS,
1078
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1079
                 0x00000000);
1080
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1081
                 SPR_NOACCESS, SPR_NOACCESS,
1082
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1083
                 0x00000000);
1084
}
1085

    
1086
/* PowerPC BookE SPR */
1087
static void gen_spr_BookE (CPUPPCState *env)
1088
{
1089
    /* Processor identification */
1090
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1091
                 SPR_NOACCESS, SPR_NOACCESS,
1092
                 &spr_read_generic, &spr_write_pir,
1093
                 0x00000000);
1094
    /* Interrupt processing */
1095
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1096
                 SPR_NOACCESS, SPR_NOACCESS,
1097
                 &spr_read_generic, &spr_write_generic,
1098
                 0x00000000);
1099
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1100
                 SPR_NOACCESS, SPR_NOACCESS,
1101
                 &spr_read_generic, &spr_write_generic,
1102
                 0x00000000);
1103
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1104
                 SPR_NOACCESS, SPR_NOACCESS,
1105
                 &spr_read_generic, &spr_write_generic,
1106
                 0x00000000);
1107
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1108
                 SPR_NOACCESS, SPR_NOACCESS,
1109
                 &spr_read_generic, &spr_write_generic,
1110
                 0x00000000);
1111
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1112
                 SPR_NOACCESS, SPR_NOACCESS,
1113
                 &spr_read_generic, &spr_write_generic,
1114
                 0x00000000);
1115
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
1116
                 SPR_NOACCESS, SPR_NOACCESS,
1117
                 &spr_read_generic, &spr_write_generic,
1118
                 0x00000000);
1119
    /* Debug */
1120
    /* XXX : not implemented */
1121
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1122
                 SPR_NOACCESS, SPR_NOACCESS,
1123
                 &spr_read_generic, &spr_write_generic,
1124
                 0x00000000);
1125
    /* XXX : not implemented */
1126
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1127
                 SPR_NOACCESS, SPR_NOACCESS,
1128
                 &spr_read_generic, &spr_write_generic,
1129
                 0x00000000);
1130
    /* XXX : not implemented */
1131
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1132
                 SPR_NOACCESS, SPR_NOACCESS,
1133
                 &spr_read_generic, &spr_write_generic,
1134
                 0x00000000);
1135
    /* XXX : not implemented */
1136
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1137
                 SPR_NOACCESS, SPR_NOACCESS,
1138
                 &spr_read_generic, &spr_write_generic,
1139
                 0x00000000);
1140
    /* XXX : not implemented */
1141
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1142
                 SPR_NOACCESS, SPR_NOACCESS,
1143
                 &spr_read_generic, &spr_write_generic,
1144
                 0x00000000);
1145
    /* XXX : not implemented */
1146
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1147
                 SPR_NOACCESS, SPR_NOACCESS,
1148
                 &spr_read_generic, &spr_write_generic,
1149
                 0x00000000);
1150
    /* XXX : not implemented */
1151
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1152
                 SPR_NOACCESS, SPR_NOACCESS,
1153
                 &spr_read_generic, &spr_write_generic,
1154
                 0x00000000);
1155
    /* XXX : not implemented */
1156
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1157
                 SPR_NOACCESS, SPR_NOACCESS,
1158
                 &spr_read_generic, &spr_write_generic,
1159
                 0x00000000);
1160
    /* XXX : not implemented */
1161
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1162
                 SPR_NOACCESS, SPR_NOACCESS,
1163
                 &spr_read_generic, &spr_write_generic,
1164
                 0x00000000);
1165
    /* XXX : not implemented */
1166
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1167
                 SPR_NOACCESS, SPR_NOACCESS,
1168
                 &spr_read_generic, &spr_write_generic,
1169
                 0x00000000);
1170
    /* XXX : not implemented */
1171
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1172
                 SPR_NOACCESS, SPR_NOACCESS,
1173
                 &spr_read_generic, &spr_write_generic,
1174
                 0x00000000);
1175
    /* XXX : not implemented */
1176
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1177
                 SPR_NOACCESS, SPR_NOACCESS,
1178
                 &spr_read_generic, &spr_write_generic,
1179
                 0x00000000);
1180
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1181
                 SPR_NOACCESS, SPR_NOACCESS,
1182
                 &spr_read_generic, &spr_write_generic,
1183
                 0x00000000);
1184
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1185
                 SPR_NOACCESS, SPR_NOACCESS,
1186
                 &spr_read_generic, &spr_write_generic,
1187
                 0x00000000);
1188
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1189
                 SPR_NOACCESS, SPR_NOACCESS,
1190
                 &spr_read_generic, &spr_write_generic,
1191
                 0x00000000);
1192
    /* Exception vectors */
1193
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1194
                 SPR_NOACCESS, SPR_NOACCESS,
1195
                 &spr_read_generic, &spr_write_generic,
1196
                 0x00000000);
1197
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1198
                 SPR_NOACCESS, SPR_NOACCESS,
1199
                 &spr_read_generic, &spr_write_generic,
1200
                 0x00000000);
1201
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1202
                 SPR_NOACCESS, SPR_NOACCESS,
1203
                 &spr_read_generic, &spr_write_generic,
1204
                 0x00000000);
1205
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1206
                 SPR_NOACCESS, SPR_NOACCESS,
1207
                 &spr_read_generic, &spr_write_generic,
1208
                 0x00000000);
1209
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1210
                 SPR_NOACCESS, SPR_NOACCESS,
1211
                 &spr_read_generic, &spr_write_generic,
1212
                 0x00000000);
1213
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1214
                 SPR_NOACCESS, SPR_NOACCESS,
1215
                 &spr_read_generic, &spr_write_generic,
1216
                 0x00000000);
1217
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1218
                 SPR_NOACCESS, SPR_NOACCESS,
1219
                 &spr_read_generic, &spr_write_generic,
1220
                 0x00000000);
1221
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1222
                 SPR_NOACCESS, SPR_NOACCESS,
1223
                 &spr_read_generic, &spr_write_generic,
1224
                 0x00000000);
1225
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1226
                 SPR_NOACCESS, SPR_NOACCESS,
1227
                 &spr_read_generic, &spr_write_generic,
1228
                 0x00000000);
1229
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1230
                 SPR_NOACCESS, SPR_NOACCESS,
1231
                 &spr_read_generic, &spr_write_generic,
1232
                 0x00000000);
1233
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1234
                 SPR_NOACCESS, SPR_NOACCESS,
1235
                 &spr_read_generic, &spr_write_generic,
1236
                 0x00000000);
1237
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1238
                 SPR_NOACCESS, SPR_NOACCESS,
1239
                 &spr_read_generic, &spr_write_generic,
1240
                 0x00000000);
1241
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1242
                 SPR_NOACCESS, SPR_NOACCESS,
1243
                 &spr_read_generic, &spr_write_generic,
1244
                 0x00000000);
1245
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1246
                 SPR_NOACCESS, SPR_NOACCESS,
1247
                 &spr_read_generic, &spr_write_generic,
1248
                 0x00000000);
1249
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1250
                 SPR_NOACCESS, SPR_NOACCESS,
1251
                 &spr_read_generic, &spr_write_generic,
1252
                 0x00000000);
1253
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1254
                 SPR_NOACCESS, SPR_NOACCESS,
1255
                 &spr_read_generic, &spr_write_generic,
1256
                 0x00000000);
1257
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1258
                 SPR_NOACCESS, SPR_NOACCESS,
1259
                 &spr_read_generic, &spr_write_generic,
1260
                 0x00000000);
1261
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1262
                 SPR_NOACCESS, SPR_NOACCESS,
1263
                 &spr_read_generic, &spr_write_generic,
1264
                 0x00000000);
1265
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1266
                 SPR_NOACCESS, SPR_NOACCESS,
1267
                 &spr_read_generic, &spr_write_generic,
1268
                 0x00000000);
1269
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1270
                 SPR_NOACCESS, SPR_NOACCESS,
1271
                 &spr_read_generic, &spr_write_generic,
1272
                 0x00000000);
1273
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1274
                 SPR_NOACCESS, SPR_NOACCESS,
1275
                 &spr_read_generic, &spr_write_generic,
1276
                 0x00000000);
1277
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1278
                 SPR_NOACCESS, SPR_NOACCESS,
1279
                 &spr_read_generic, &spr_write_generic,
1280
                 0x00000000);
1281
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1282
                 SPR_NOACCESS, SPR_NOACCESS,
1283
                 &spr_read_generic, &spr_write_generic,
1284
                 0x00000000);
1285
    spr_register(env, SPR_BOOKE_PID, "PID",
1286
                 SPR_NOACCESS, SPR_NOACCESS,
1287
                 &spr_read_generic, &spr_write_generic,
1288
                 0x00000000);
1289
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1290
                 SPR_NOACCESS, SPR_NOACCESS,
1291
                 &spr_read_generic, &spr_write_booke_tcr,
1292
                 0x00000000);
1293
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1294
                 SPR_NOACCESS, SPR_NOACCESS,
1295
                 &spr_read_generic, &spr_write_booke_tsr,
1296
                 0x00000000);
1297
    /* Timer */
1298
    spr_register(env, SPR_DECR, "DECR",
1299
                 SPR_NOACCESS, SPR_NOACCESS,
1300
                 &spr_read_decr, &spr_write_decr,
1301
                 0x00000000);
1302
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1303
                 SPR_NOACCESS, SPR_NOACCESS,
1304
                 SPR_NOACCESS, &spr_write_generic,
1305
                 0x00000000);
1306
    /* SPRGs */
1307
    spr_register(env, SPR_USPRG0, "USPRG0",
1308
                 &spr_read_generic, &spr_write_generic,
1309
                 &spr_read_generic, &spr_write_generic,
1310
                 0x00000000);
1311
    spr_register(env, SPR_SPRG4, "SPRG4",
1312
                 SPR_NOACCESS, SPR_NOACCESS,
1313
                 &spr_read_generic, &spr_write_generic,
1314
                 0x00000000);
1315
    spr_register(env, SPR_USPRG4, "USPRG4",
1316
                 &spr_read_ureg, SPR_NOACCESS,
1317
                 &spr_read_ureg, SPR_NOACCESS,
1318
                 0x00000000);
1319
    spr_register(env, SPR_SPRG5, "SPRG5",
1320
                 SPR_NOACCESS, SPR_NOACCESS,
1321
                 &spr_read_generic, &spr_write_generic,
1322
                 0x00000000);
1323
    spr_register(env, SPR_USPRG5, "USPRG5",
1324
                 &spr_read_ureg, SPR_NOACCESS,
1325
                 &spr_read_ureg, SPR_NOACCESS,
1326
                 0x00000000);
1327
    spr_register(env, SPR_SPRG6, "SPRG6",
1328
                 SPR_NOACCESS, SPR_NOACCESS,
1329
                 &spr_read_generic, &spr_write_generic,
1330
                 0x00000000);
1331
    spr_register(env, SPR_USPRG6, "USPRG6",
1332
                 &spr_read_ureg, SPR_NOACCESS,
1333
                 &spr_read_ureg, SPR_NOACCESS,
1334
                 0x00000000);
1335
    spr_register(env, SPR_SPRG7, "SPRG7",
1336
                 SPR_NOACCESS, SPR_NOACCESS,
1337
                 &spr_read_generic, &spr_write_generic,
1338
                 0x00000000);
1339
    spr_register(env, SPR_USPRG7, "USPRG7",
1340
                 &spr_read_ureg, SPR_NOACCESS,
1341
                 &spr_read_ureg, SPR_NOACCESS,
1342
                 0x00000000);
1343
}
1344

    
1345
/* FSL storage control registers */
1346
static void gen_spr_BookE_FSL (CPUPPCState *env)
1347
{
1348
    /* TLB assist registers */
1349
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1350
                 SPR_NOACCESS, SPR_NOACCESS,
1351
                 &spr_read_generic, &spr_write_generic,
1352
                 0x00000000);
1353
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1354
                 SPR_NOACCESS, SPR_NOACCESS,
1355
                 &spr_read_generic, &spr_write_generic,
1356
                 0x00000000);
1357
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1358
                 SPR_NOACCESS, SPR_NOACCESS,
1359
                 &spr_read_generic, &spr_write_generic,
1360
                 0x00000000);
1361
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1362
                 SPR_NOACCESS, SPR_NOACCESS,
1363
                 &spr_read_generic, &spr_write_generic,
1364
                 0x00000000);
1365
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1366
                 SPR_NOACCESS, SPR_NOACCESS,
1367
                 &spr_read_generic, &spr_write_generic,
1368
                 0x00000000);
1369
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1370
                 SPR_NOACCESS, SPR_NOACCESS,
1371
                 &spr_read_generic, &spr_write_generic,
1372
                 0x00000000);
1373
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1374
                 SPR_NOACCESS, SPR_NOACCESS,
1375
                 &spr_read_generic, &spr_write_generic,
1376
                 0x00000000);
1377
    if (env->nb_pids > 1) {
1378
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1379
                     SPR_NOACCESS, SPR_NOACCESS,
1380
                     &spr_read_generic, &spr_write_generic,
1381
                     0x00000000);
1382
    }
1383
    if (env->nb_pids > 2) {
1384
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1385
                     SPR_NOACCESS, SPR_NOACCESS,
1386
                     &spr_read_generic, &spr_write_generic,
1387
                     0x00000000);
1388
    }
1389
    spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1390
                 SPR_NOACCESS, SPR_NOACCESS,
1391
                 &spr_read_generic, SPR_NOACCESS,
1392
                 0x00000000); /* TOFIX */
1393
    spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1394
                 SPR_NOACCESS, SPR_NOACCESS,
1395
                 &spr_read_generic, &spr_write_generic,
1396
                 0x00000000); /* TOFIX */
1397
    switch (env->nb_ways) {
1398
    case 4:
1399
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1400
                     SPR_NOACCESS, SPR_NOACCESS,
1401
                     &spr_read_generic, SPR_NOACCESS,
1402
                     0x00000000); /* TOFIX */
1403
        /* Fallthru */
1404
    case 3:
1405
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1406
                     SPR_NOACCESS, SPR_NOACCESS,
1407
                     &spr_read_generic, SPR_NOACCESS,
1408
                     0x00000000); /* TOFIX */
1409
        /* Fallthru */
1410
    case 2:
1411
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1412
                     SPR_NOACCESS, SPR_NOACCESS,
1413
                     &spr_read_generic, SPR_NOACCESS,
1414
                     0x00000000); /* TOFIX */
1415
        /* Fallthru */
1416
    case 1:
1417
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1418
                     SPR_NOACCESS, SPR_NOACCESS,
1419
                     &spr_read_generic, SPR_NOACCESS,
1420
                     0x00000000); /* TOFIX */
1421
        /* Fallthru */
1422
    case 0:
1423
    default:
1424
        break;
1425
    }
1426
}
1427

    
1428
/* SPR specific to PowerPC 440 implementation */
1429
static void gen_spr_440 (CPUPPCState *env)
1430
{
1431
    /* Cache control */
1432
    /* XXX : not implemented */
1433
    spr_register(env, SPR_440_DNV0, "DNV0",
1434
                 SPR_NOACCESS, SPR_NOACCESS,
1435
                 &spr_read_generic, &spr_write_generic,
1436
                 0x00000000);
1437
    /* XXX : not implemented */
1438
    spr_register(env, SPR_440_DNV1, "DNV1",
1439
                 SPR_NOACCESS, SPR_NOACCESS,
1440
                 &spr_read_generic, &spr_write_generic,
1441
                 0x00000000);
1442
    /* XXX : not implemented */
1443
    spr_register(env, SPR_440_DNV2, "DNV2",
1444
                 SPR_NOACCESS, SPR_NOACCESS,
1445
                 &spr_read_generic, &spr_write_generic,
1446
                 0x00000000);
1447
    /* XXX : not implemented */
1448
    spr_register(env, SPR_440_DNV3, "DNV3",
1449
                 SPR_NOACCESS, SPR_NOACCESS,
1450
                 &spr_read_generic, &spr_write_generic,
1451
                 0x00000000);
1452
    /* XXX : not implemented */
1453
    spr_register(env, SPR_440_DVT0, "DVT0",
1454
                 SPR_NOACCESS, SPR_NOACCESS,
1455
                 &spr_read_generic, &spr_write_generic,
1456
                 0x00000000);
1457
    /* XXX : not implemented */
1458
    spr_register(env, SPR_440_DVT1, "DVT1",
1459
                 SPR_NOACCESS, SPR_NOACCESS,
1460
                 &spr_read_generic, &spr_write_generic,
1461
                 0x00000000);
1462
    /* XXX : not implemented */
1463
    spr_register(env, SPR_440_DVT2, "DVT2",
1464
                 SPR_NOACCESS, SPR_NOACCESS,
1465
                 &spr_read_generic, &spr_write_generic,
1466
                 0x00000000);
1467
    /* XXX : not implemented */
1468
    spr_register(env, SPR_440_DVT3, "DVT3",
1469
                 SPR_NOACCESS, SPR_NOACCESS,
1470
                 &spr_read_generic, &spr_write_generic,
1471
                 0x00000000);
1472
    /* XXX : not implemented */
1473
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1474
                 SPR_NOACCESS, SPR_NOACCESS,
1475
                 &spr_read_generic, &spr_write_generic,
1476
                 0x00000000);
1477
    /* XXX : not implemented */
1478
    spr_register(env, SPR_440_INV0, "INV0",
1479
                 SPR_NOACCESS, SPR_NOACCESS,
1480
                 &spr_read_generic, &spr_write_generic,
1481
                 0x00000000);
1482
    /* XXX : not implemented */
1483
    spr_register(env, SPR_440_INV1, "INV1",
1484
                 SPR_NOACCESS, SPR_NOACCESS,
1485
                 &spr_read_generic, &spr_write_generic,
1486
                 0x00000000);
1487
    /* XXX : not implemented */
1488
    spr_register(env, SPR_440_INV2, "INV2",
1489
                 SPR_NOACCESS, SPR_NOACCESS,
1490
                 &spr_read_generic, &spr_write_generic,
1491
                 0x00000000);
1492
    /* XXX : not implemented */
1493
    spr_register(env, SPR_440_INV3, "INV3",
1494
                 SPR_NOACCESS, SPR_NOACCESS,
1495
                 &spr_read_generic, &spr_write_generic,
1496
                 0x00000000);
1497
    /* XXX : not implemented */
1498
    spr_register(env, SPR_440_IVT0, "IVT0",
1499
                 SPR_NOACCESS, SPR_NOACCESS,
1500
                 &spr_read_generic, &spr_write_generic,
1501
                 0x00000000);
1502
    /* XXX : not implemented */
1503
    spr_register(env, SPR_440_IVT1, "IVT1",
1504
                 SPR_NOACCESS, SPR_NOACCESS,
1505
                 &spr_read_generic, &spr_write_generic,
1506
                 0x00000000);
1507
    /* XXX : not implemented */
1508
    spr_register(env, SPR_440_IVT2, "IVT2",
1509
                 SPR_NOACCESS, SPR_NOACCESS,
1510
                 &spr_read_generic, &spr_write_generic,
1511
                 0x00000000);
1512
    /* XXX : not implemented */
1513
    spr_register(env, SPR_440_IVT3, "IVT3",
1514
                 SPR_NOACCESS, SPR_NOACCESS,
1515
                 &spr_read_generic, &spr_write_generic,
1516
                 0x00000000);
1517
    /* XXX : not implemented */
1518
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1519
                 SPR_NOACCESS, SPR_NOACCESS,
1520
                 &spr_read_generic, &spr_write_generic,
1521
                 0x00000000);
1522
    /* Cache debug */
1523
    /* XXX : not implemented */
1524
    spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
1525
                 SPR_NOACCESS, SPR_NOACCESS,
1526
                 &spr_read_generic, SPR_NOACCESS,
1527
                 0x00000000);
1528
    /* XXX : not implemented */
1529
    spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
1530
                 SPR_NOACCESS, SPR_NOACCESS,
1531
                 &spr_read_generic, SPR_NOACCESS,
1532
                 0x00000000);
1533
    /* XXX : not implemented */
1534
    spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1535
                 SPR_NOACCESS, SPR_NOACCESS,
1536
                 &spr_read_generic, SPR_NOACCESS,
1537
                 0x00000000);
1538
    /* XXX : not implemented */
1539
    spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
1540
                 SPR_NOACCESS, SPR_NOACCESS,
1541
                 &spr_read_generic, SPR_NOACCESS,
1542
                 0x00000000);
1543
    /* XXX : not implemented */
1544
    spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
1545
                 SPR_NOACCESS, SPR_NOACCESS,
1546
                 &spr_read_generic, SPR_NOACCESS,
1547
                 0x00000000);
1548
    /* XXX : not implemented */
1549
    spr_register(env, SPR_440_DBDR, "DBDR",
1550
                 SPR_NOACCESS, SPR_NOACCESS,
1551
                 &spr_read_generic, &spr_write_generic,
1552
                 0x00000000);
1553
    /* Processor control */
1554
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1555
                 SPR_NOACCESS, SPR_NOACCESS,
1556
                 &spr_read_generic, &spr_write_generic,
1557
                 0x00000000);
1558
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1559
                 SPR_NOACCESS, SPR_NOACCESS,
1560
                 &spr_read_generic, SPR_NOACCESS,
1561
                 0x00000000);
1562
    /* Storage control */
1563
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1564
                 SPR_NOACCESS, SPR_NOACCESS,
1565
                 &spr_read_generic, &spr_write_generic,
1566
                 0x00000000);
1567
}
1568

    
1569
/* SPR shared between PowerPC 40x implementations */
1570
static void gen_spr_40x (CPUPPCState *env)
1571
{
1572
    /* Cache */
1573
    /* XXX : not implemented */
1574
    spr_register(env, SPR_40x_DCCR, "DCCR",
1575
                 SPR_NOACCESS, SPR_NOACCESS,
1576
                 &spr_read_generic, &spr_write_generic,
1577
                 0x00000000);
1578
    /* XXX : not implemented */
1579
    spr_register(env, SPR_40x_DCWR, "DCWR",
1580
                 SPR_NOACCESS, SPR_NOACCESS,
1581
                 &spr_read_generic, &spr_write_generic,
1582
                 0x00000000);
1583
    /* XXX : not implemented */
1584
    spr_register(env, SPR_40x_ICCR, "ICCR",
1585
                 SPR_NOACCESS, SPR_NOACCESS,
1586
                 &spr_read_generic, &spr_write_generic,
1587
                 0x00000000);
1588
    /* XXX : not implemented */
1589
    spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1590
                 SPR_NOACCESS, SPR_NOACCESS,
1591
                 &spr_read_generic, SPR_NOACCESS,
1592
                 0x00000000);
1593
    /* Bus access control */
1594
    spr_register(env, SPR_40x_SGR, "SGR",
1595
                 SPR_NOACCESS, SPR_NOACCESS,
1596
                 &spr_read_generic, &spr_write_generic,
1597
                 0xFFFFFFFF);
1598
    spr_register(env, SPR_40x_ZPR, "ZPR",
1599
                 SPR_NOACCESS, SPR_NOACCESS,
1600
                 &spr_read_generic, &spr_write_generic,
1601
                 0x00000000);
1602
    /* MMU */
1603
    spr_register(env, SPR_40x_PID, "PID",
1604
                 SPR_NOACCESS, SPR_NOACCESS,
1605
                 &spr_read_generic, &spr_write_generic,
1606
                 0x00000000);
1607
    /* Exception */
1608
    spr_register(env, SPR_40x_DEAR, "DEAR",
1609
                 SPR_NOACCESS, SPR_NOACCESS,
1610
                 &spr_read_generic, &spr_write_generic,
1611
                 0x00000000);
1612
    spr_register(env, SPR_40x_ESR, "ESR",
1613
                 SPR_NOACCESS, SPR_NOACCESS,
1614
                 &spr_read_generic, &spr_write_generic,
1615
                 0x00000000);
1616
    spr_register(env, SPR_40x_EVPR, "EVPR",
1617
                 SPR_NOACCESS, SPR_NOACCESS,
1618
                 &spr_read_generic, &spr_write_generic,
1619
                 0x00000000);
1620
    spr_register(env, SPR_40x_SRR2, "SRR2",
1621
                 &spr_read_generic, &spr_write_generic,
1622
                 &spr_read_generic, &spr_write_generic,
1623
                 0x00000000);
1624
    spr_register(env, SPR_40x_SRR3, "SRR3",
1625
                 &spr_read_generic, &spr_write_generic,
1626
                 &spr_read_generic, &spr_write_generic,
1627
                 0x00000000);
1628
    /* Timers */
1629
    spr_register(env, SPR_40x_PIT, "PIT",
1630
                 SPR_NOACCESS, SPR_NOACCESS,
1631
                 &spr_read_40x_pit, &spr_write_40x_pit,
1632
                 0x00000000);
1633
    spr_register(env, SPR_40x_TCR, "TCR",
1634
                 SPR_NOACCESS, SPR_NOACCESS,
1635
                 &spr_read_generic, &spr_write_booke_tcr,
1636
                 0x00000000);
1637
    spr_register(env, SPR_40x_TSR, "TSR",
1638
                 SPR_NOACCESS, SPR_NOACCESS,
1639
                 &spr_read_generic, &spr_write_booke_tsr,
1640
                 0x00000000);
1641
    /* Debug interface */
1642
    /* XXX : not implemented */
1643
    spr_register(env, SPR_40x_DAC1, "DAC1",
1644
                 SPR_NOACCESS, SPR_NOACCESS,
1645
                 &spr_read_generic, &spr_write_generic,
1646
                 0x00000000);
1647
    spr_register(env, SPR_40x_DAC2, "DAC2",
1648
                 SPR_NOACCESS, SPR_NOACCESS,
1649
                 &spr_read_generic, &spr_write_generic,
1650
                 0x00000000);
1651
    /* XXX : not implemented */
1652
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1653
                 SPR_NOACCESS, SPR_NOACCESS,
1654
                 &spr_read_generic, &spr_write_generic,
1655
                 0x00000000);
1656
    /* XXX : not implemented */
1657
    spr_register(env, SPR_40x_DBSR, "DBSR",
1658
                 SPR_NOACCESS, SPR_NOACCESS,
1659
                 &spr_read_generic, &spr_write_generic,
1660
                 /* Last reset was system reset (system boot */
1661
                 0x00000300);
1662
    /* XXX : not implemented */
1663
    spr_register(env, SPR_40x_IAC1, "IAC1",
1664
                 SPR_NOACCESS, SPR_NOACCESS,
1665
                 &spr_read_generic, &spr_write_generic,
1666
                 0x00000000);
1667
    spr_register(env, SPR_40x_IAC2, "IAC2",
1668
                 SPR_NOACCESS, SPR_NOACCESS,
1669
                 &spr_read_generic, &spr_write_generic,
1670
                 0x00000000);
1671
}
1672

    
1673
/* SPR specific to PowerPC 405 implementation */
1674
static void gen_spr_405 (CPUPPCState *env)
1675
{
1676
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1677
                 SPR_NOACCESS, SPR_NOACCESS,
1678
                 &spr_read_generic, &spr_write_generic,
1679
                 0x00700000);
1680
    /* Debug */
1681
    /* XXX : not implemented */
1682
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1683
                 SPR_NOACCESS, SPR_NOACCESS,
1684
                 &spr_read_generic, &spr_write_generic,
1685
                 0x00000000);
1686
    /* XXX : not implemented */
1687
    spr_register(env, SPR_405_DVC1, "DVC1",
1688
                 SPR_NOACCESS, SPR_NOACCESS,
1689
                 &spr_read_generic, &spr_write_generic,
1690
                 0x00000000);
1691
    /* XXX : not implemented */
1692
    spr_register(env, SPR_405_DVC2, "DVC2",
1693
                 SPR_NOACCESS, SPR_NOACCESS,
1694
                 &spr_read_generic, &spr_write_generic,
1695
                 0x00000000);
1696
    /* XXX : not implemented */
1697
    spr_register(env, SPR_405_IAC3, "IAC3",
1698
                 SPR_NOACCESS, SPR_NOACCESS,
1699
                 &spr_read_generic, &spr_write_generic,
1700
                 0x00000000);
1701
    /* XXX : not implemented */
1702
    spr_register(env, SPR_405_IAC4, "IAC4",
1703
                 SPR_NOACCESS, SPR_NOACCESS,
1704
                 &spr_read_generic, &spr_write_generic,
1705
                 0x00000000);
1706
    /* Storage control */
1707
    /* XXX : not implemented */
1708
    spr_register(env, SPR_405_SLER, "SLER",
1709
                 SPR_NOACCESS, SPR_NOACCESS,
1710
                 &spr_read_generic, &spr_write_generic,
1711
                 0x00000000);
1712
    /* XXX : not implemented */
1713
    spr_register(env, SPR_405_SU0R, "SU0R",
1714
                 SPR_NOACCESS, SPR_NOACCESS,
1715
                 &spr_read_generic, &spr_write_generic,
1716
                 0x00000000);
1717
    /* SPRG */
1718
    spr_register(env, SPR_USPRG0, "USPRG0",
1719
                 &spr_read_ureg, SPR_NOACCESS,
1720
                 &spr_read_ureg, SPR_NOACCESS,
1721
                 0x00000000);
1722
    spr_register(env, SPR_SPRG4, "SPRG4",
1723
                 SPR_NOACCESS, SPR_NOACCESS,
1724
                 SPR_NOACCESS, &spr_write_generic,
1725
                 0x00000000);
1726
    spr_register(env, SPR_USPRG4, "USPRG4",
1727
                 &spr_read_ureg, SPR_NOACCESS,
1728
                 &spr_read_ureg, SPR_NOACCESS,
1729
                 0x00000000);
1730
    spr_register(env, SPR_SPRG5, "SPRG5",
1731
                 SPR_NOACCESS, SPR_NOACCESS,
1732
                 SPR_NOACCESS, &spr_write_generic,
1733
                 0x00000000);
1734
    spr_register(env, SPR_USPRG5, "USPRG5",
1735
                 &spr_read_ureg, SPR_NOACCESS,
1736
                 &spr_read_ureg, SPR_NOACCESS,
1737
                 0x00000000);
1738
    spr_register(env, SPR_SPRG6, "SPRG6",
1739
                 SPR_NOACCESS, SPR_NOACCESS,
1740
                 SPR_NOACCESS, &spr_write_generic,
1741
                 0x00000000);
1742
    spr_register(env, SPR_USPRG6, "USPRG6",
1743
                 &spr_read_ureg, SPR_NOACCESS,
1744
                 &spr_read_ureg, SPR_NOACCESS,
1745
                 0x00000000);
1746
    spr_register(env, SPR_SPRG7, "SPRG7",
1747
                 SPR_NOACCESS, SPR_NOACCESS,
1748
                 SPR_NOACCESS, &spr_write_generic,
1749
                 0x00000000);
1750
    spr_register(env, SPR_USPRG7, "USPRG7",
1751
                 &spr_read_ureg, SPR_NOACCESS,
1752
                 &spr_read_ureg, SPR_NOACCESS,
1753
                 0x00000000);
1754
    /* Debug */
1755
    /* XXX : not implemented */
1756
    spr_register(env, SPR_40x_DAC2, "DAC2",
1757
                 SPR_NOACCESS, SPR_NOACCESS,
1758
                 &spr_read_generic, &spr_write_generic,
1759
                 0x00000000);
1760
    /* XXX : not implemented */
1761
    spr_register(env, SPR_40x_IAC2, "IAC2",
1762
                 SPR_NOACCESS, SPR_NOACCESS,
1763
                 &spr_read_generic, &spr_write_generic,
1764
                 0x00000000);
1765
}
1766

    
1767
/* SPR shared between PowerPC 401 & 403 implementations */
1768
static void gen_spr_401_403 (CPUPPCState *env)
1769
{
1770
    /* Time base */
1771
    spr_register(env, SPR_403_VTBL,  "TBL",
1772
                 &spr_read_tbl, SPR_NOACCESS,
1773
                 &spr_read_tbl, SPR_NOACCESS,
1774
                 0x00000000);
1775
    spr_register(env, SPR_403_TBL,   "TBL",
1776
                 SPR_NOACCESS, SPR_NOACCESS,
1777
                 SPR_NOACCESS, &spr_write_tbl,
1778
                 0x00000000);
1779
    spr_register(env, SPR_403_VTBU,  "TBU",
1780
                 &spr_read_tbu, SPR_NOACCESS,
1781
                 &spr_read_tbu, SPR_NOACCESS,
1782
                 0x00000000);
1783
    spr_register(env, SPR_403_TBU,   "TBU",
1784
                 SPR_NOACCESS, SPR_NOACCESS,
1785
                 SPR_NOACCESS, &spr_write_tbu,
1786
                 0x00000000);
1787
    /* Debug */
1788
    /* XXX: not implemented */
1789
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1790
                 SPR_NOACCESS, SPR_NOACCESS,
1791
                 &spr_read_generic, &spr_write_generic,
1792
                 0x00000000);
1793
}
1794

    
1795
/* SPR specific to PowerPC 403 implementation */
1796
static void gen_spr_403 (CPUPPCState *env)
1797
{
1798
    /* MMU */
1799
    spr_register(env, SPR_403_PBL1,  "PBL1",
1800
                 SPR_NOACCESS, SPR_NOACCESS,
1801
                 &spr_read_403_pbr, &spr_write_403_pbr,
1802
                 0x00000000);
1803
    spr_register(env, SPR_403_PBU1,  "PBU1",
1804
                 SPR_NOACCESS, SPR_NOACCESS,
1805
                 &spr_read_403_pbr, &spr_write_403_pbr,
1806
                 0x00000000);
1807
    spr_register(env, SPR_403_PBL2,  "PBL2",
1808
                 SPR_NOACCESS, SPR_NOACCESS,
1809
                 &spr_read_403_pbr, &spr_write_403_pbr,
1810
                 0x00000000);
1811
    spr_register(env, SPR_403_PBU2,  "PBU2",
1812
                 SPR_NOACCESS, SPR_NOACCESS,
1813
                 &spr_read_403_pbr, &spr_write_403_pbr,
1814
                 0x00000000);
1815
    /* Debug */
1816
    /* XXX : not implemented */
1817
    spr_register(env, SPR_40x_DAC2, "DAC2",
1818
                 SPR_NOACCESS, SPR_NOACCESS,
1819
                 &spr_read_generic, &spr_write_generic,
1820
                 0x00000000);
1821
    /* XXX : not implemented */
1822
    spr_register(env, SPR_40x_IAC2, "IAC2",
1823
                 SPR_NOACCESS, SPR_NOACCESS,
1824
                 &spr_read_generic, &spr_write_generic,
1825
                 0x00000000);
1826
}
1827

    
1828
/* SPR specific to PowerPC compression coprocessor extension */
1829
#if defined (TODO)
1830
static void gen_spr_compress (CPUPPCState *env)
1831
{
1832
    spr_register(env, SPR_401_SKR, "SKR",
1833
                 SPR_NOACCESS, SPR_NOACCESS,
1834
                 &spr_read_generic, &spr_write_generic,
1835
                 0x00000000);
1836
}
1837
#endif
1838

    
1839
// XXX: TODO (64 bits PowerPC SPRs)
1840
/*
1841
 * ASR => SPR 280 (64 bits)
1842
 * FPECR => SPR 1022 (?)
1843
 * VRSAVE => SPR 256 (Altivec)
1844
 * SCOMC => SPR 276 (64 bits ?)
1845
 * SCOMD => SPR 277 (64 bits ?)
1846
 * HSPRG0 => SPR 304 (hypervisor)
1847
 * HSPRG1 => SPR 305 (hypervisor)
1848
 * HDEC => SPR 310 (hypervisor)
1849
 * HIOR => SPR 311 (hypervisor)
1850
 * RMOR => SPR 312 (970)
1851
 * HRMOR => SPR 313 (hypervisor)
1852
 * HSRR0 => SPR 314 (hypervisor)
1853
 * HSRR1 => SPR 315 (hypervisor)
1854
 * LPCR => SPR 316 (970)
1855
 * LPIDR => SPR 317 (970)
1856
 * ... and more (thermal management, performance counters, ...)
1857
 */
1858

    
1859
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1860
{
1861
    env->reserve = -1;
1862
    /* Default MMU definitions */
1863
    env->nb_BATs = -1;
1864
    env->nb_tlb = 0;
1865
    env->nb_ways = 0;
1866
    /* XXX: missing:
1867
     * 32 bits PowerPC:
1868
     * - MPC5xx(x)
1869
     * - MPC8xx(x)
1870
     * - RCPU (same as MPC5xx ?)
1871
     */
1872
    spr_register(env, SPR_PVR, "PVR",
1873
                 SPR_NOACCESS, SPR_NOACCESS,
1874
                 &spr_read_generic, SPR_NOACCESS,
1875
                 def->pvr);
1876
    printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1877
           def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
1878
    switch (def->pvr) {
1879
    /* Embedded PowerPC from IBM                           */
1880
    case CPU_PPC_401A1:   /* 401 A1 family                 */
1881
    case CPU_PPC_401B2:   /* 401 B2 family                 */
1882
    case CPU_PPC_401C2:   /* 401 C2 family                 */
1883
    case CPU_PPC_401D2:   /* 401 D2 family                 */
1884
    case CPU_PPC_401E2:   /* 401 E2 family                 */
1885
    case CPU_PPC_401F2:   /* 401 F2 family                 */
1886
    case CPU_PPC_401G2:   /* 401 G2 family                 */
1887
    case CPU_PPC_IOP480:  /* IOP 480 family                */
1888
    case CPU_PPC_COBRA:   /* IBM Processor for Network Resources */
1889
        gen_spr_generic(env);
1890
        gen_spr_40x(env);
1891
        gen_spr_401_403(env);
1892
#if defined (TODO)
1893
        /* XXX: optional ? */
1894
        gen_spr_compress(env);
1895
#endif
1896
        env->nb_BATs = 0;
1897
        env->nb_tlb = 64;
1898
        env->nb_ways = 1;
1899
        env->id_tlbs = 0;
1900
        /* XXX: TODO: allocate internal IRQ controller */
1901
        break;
1902

    
1903
    case CPU_PPC_403GA:   /* 403 GA family                 */
1904
    case CPU_PPC_403GB:   /* 403 GB family                 */
1905
    case CPU_PPC_403GC:   /* 403 GC family                 */
1906
    case CPU_PPC_403GCX:  /* 403 GCX family                */
1907
        gen_spr_generic(env);
1908
        gen_spr_40x(env);
1909
        gen_spr_401_403(env);
1910
        gen_spr_403(env);
1911
        env->nb_BATs = 0;
1912
        env->nb_tlb = 64;
1913
        env->nb_ways = 1;
1914
        env->id_tlbs = 0;
1915
        /* XXX: TODO: allocate internal IRQ controller */
1916
        break;
1917

    
1918
    case CPU_PPC_405CR:   /* 405 GP/CR family              */
1919
    case CPU_PPC_405EP:   /* 405 EP family                 */
1920
    case CPU_PPC_405GPR:  /* 405 GPR family                */
1921
    case CPU_PPC_405D2:   /* 405 D2 family                 */
1922
    case CPU_PPC_405D4:   /* 405 D4 family                 */
1923
        gen_spr_generic(env);
1924
        /* Time base */
1925
        gen_tbl(env);
1926
        gen_spr_40x(env);
1927
        gen_spr_405(env);
1928
        env->nb_BATs = 0;
1929
        env->nb_tlb = 64;
1930
        env->nb_ways = 1;
1931
        env->id_tlbs = 0;
1932
        /* Allocate hardware IRQ controller */
1933
        ppc405_irq_init(env);
1934
        break;
1935

    
1936
    case CPU_PPC_NPE405H: /* NPe405 H family               */
1937
    case CPU_PPC_NPE405H2:
1938
    case CPU_PPC_NPE405L: /* Npe405 L family               */
1939
        gen_spr_generic(env);
1940
        /* Time base */
1941
        gen_tbl(env);
1942
        gen_spr_40x(env);
1943
        gen_spr_405(env);
1944
        env->nb_BATs = 0;
1945
        env->nb_tlb = 64;
1946
        env->nb_ways = 1;
1947
        env->id_tlbs = 0;
1948
        /* Allocate hardware IRQ controller */
1949
        ppc405_irq_init(env);
1950
        break;
1951

    
1952
#if defined (TODO)
1953
    case CPU_PPC_STB01000:
1954
#endif
1955
#if defined (TODO)
1956
    case CPU_PPC_STB01010:
1957
#endif
1958
#if defined (TODO)
1959
    case CPU_PPC_STB0210:
1960
#endif
1961
    case CPU_PPC_STB03:   /* STB03 family                  */
1962
#if defined (TODO)
1963
    case CPU_PPC_STB043:  /* STB043 family                  */
1964
#endif
1965
#if defined (TODO)
1966
    case CPU_PPC_STB045:  /* STB045 family                  */
1967
#endif
1968
    case CPU_PPC_STB25:   /* STB25 family                  */
1969
#if defined (TODO)
1970
    case CPU_PPC_STB130:  /* STB130 family                 */
1971
#endif
1972
        gen_spr_generic(env);
1973
        /* Time base */
1974
        gen_tbl(env);
1975
        gen_spr_40x(env);
1976
        gen_spr_405(env);
1977
        env->nb_BATs = 0;
1978
        env->nb_tlb = 64;
1979
        env->nb_ways = 1;
1980
        env->id_tlbs = 0;
1981
        /* Allocate hardware IRQ controller */
1982
        ppc405_irq_init(env);
1983
        break;
1984

    
1985
    case CPU_PPC_440EP:   /* 440 EP family                 */
1986
    case CPU_PPC_440GP:   /* 440 GP family                 */
1987
    case CPU_PPC_440GX:   /* 440 GX family                 */
1988
    case CPU_PPC_440GXc:  /* 440 GXc family                */
1989
    case CPU_PPC_440GXf:  /* 440 GXf family                */
1990
    case CPU_PPC_440SP:   /* 440 SP family                 */
1991
    case CPU_PPC_440SP2:
1992
    case CPU_PPC_440SPE:  /* 440 SPE family                */
1993
        gen_spr_generic(env);
1994
        /* Time base */
1995
        gen_tbl(env);
1996
        gen_spr_BookE(env);
1997
        gen_spr_440(env);
1998
        env->nb_BATs = 0;
1999
        env->nb_tlb = 64;
2000
        env->nb_ways = 1;
2001
        env->id_tlbs = 0;
2002
        /* XXX: TODO: allocate internal IRQ controller */
2003
        break;
2004

    
2005
    /* Embedded PowerPC from Freescale                     */
2006
#if defined (TODO)
2007
    case CPU_PPC_5xx:
2008
        break;
2009
#endif
2010
#if defined (TODO)
2011
    case CPU_PPC_8xx:     /* MPC821 / 823 / 850 / 860      */
2012
        break;
2013
#endif
2014
#if defined (TODO)
2015
    case CPU_PPC_82xx_HIP3:    /* MPC8240 / 8260                */
2016
    case CPU_PPC_82xx_HIP4:    /* MPC8240 / 8260                */
2017
        break;
2018
#endif
2019
#if defined (TODO)
2020
    case CPU_PPC_827x:    /* MPC 827x / 828x               */
2021
        break;
2022
#endif
2023

    
2024
    /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
2025
    case CPU_PPC_e500v110:
2026
    case CPU_PPC_e500v120:
2027
    case CPU_PPC_e500v210:
2028
    case CPU_PPC_e500v220:
2029
        gen_spr_generic(env);
2030
        /* Time base */
2031
        gen_tbl(env);
2032
        gen_spr_BookE(env);
2033
        gen_spr_BookE_FSL(env);
2034
        env->nb_BATs = 0;
2035
        env->nb_tlb = 64;
2036
        env->nb_ways = 1;
2037
        env->id_tlbs = 0;
2038
        /* XXX: TODO: allocate internal IRQ controller */
2039
        break;
2040

    
2041
#if defined (TODO)
2042
    case CPU_PPC_e600:
2043
        break;
2044
#endif
2045

    
2046
    /* 32 bits PowerPC                                     */
2047
    case CPU_PPC_601:     /* PowerPC 601                   */
2048
        gen_spr_generic(env);
2049
        gen_spr_ne_601(env);
2050
        gen_spr_601(env);
2051
        /* Hardware implementation registers */
2052
        /* XXX : not implemented */
2053
        spr_register(env, SPR_HID0, "HID0",
2054
                     SPR_NOACCESS, SPR_NOACCESS,
2055
                     &spr_read_generic, &spr_write_generic,
2056
                     0x00000000);
2057
        /* XXX : not implemented */
2058
        spr_register(env, SPR_HID1, "HID1",
2059
                     SPR_NOACCESS, SPR_NOACCESS,
2060
                     &spr_read_generic, &spr_write_generic,
2061
                     0x00000000);
2062
        /* XXX : not implemented */
2063
        spr_register(env, SPR_601_HID2, "HID2",
2064
                     SPR_NOACCESS, SPR_NOACCESS,
2065
                     &spr_read_generic, &spr_write_generic,
2066
                     0x00000000);
2067
        /* XXX : not implemented */
2068
        spr_register(env, SPR_601_HID5, "HID5",
2069
                     SPR_NOACCESS, SPR_NOACCESS,
2070
                     &spr_read_generic, &spr_write_generic,
2071
                     0x00000000);
2072
        /* XXX : not implemented */
2073
#if 0 /* ? */
2074
        spr_register(env, SPR_601_HID15, "HID15",
2075
                     SPR_NOACCESS, SPR_NOACCESS,
2076
                     &spr_read_generic, &spr_write_generic,
2077
                     0x00000000);
2078
#endif
2079
        env->nb_tlb = 64;
2080
        env->nb_ways = 2;
2081
        env->id_tlbs = 0;
2082
        env->id_tlbs = 0;
2083
        /* XXX: TODO: allocate internal IRQ controller */
2084
        break;
2085

    
2086
    case CPU_PPC_602:     /* PowerPC 602                   */
2087
        gen_spr_generic(env);
2088
        gen_spr_ne_601(env);
2089
        /* Memory management */
2090
        gen_low_BATs(env);
2091
        /* Time base */
2092
        gen_tbl(env);
2093
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2094
        gen_spr_602(env);
2095
        /* hardware implementation registers */
2096
        /* XXX : not implemented */
2097
        spr_register(env, SPR_HID0, "HID0",
2098
                     SPR_NOACCESS, SPR_NOACCESS,
2099
                     &spr_read_generic, &spr_write_generic,
2100
                     0x00000000);
2101
        /* XXX : not implemented */
2102
        spr_register(env, SPR_HID1, "HID1",
2103
                     SPR_NOACCESS, SPR_NOACCESS,
2104
                     &spr_read_generic, &spr_write_generic,
2105
                     0x00000000);
2106
        /* Allocate hardware IRQ controller */
2107
        ppc6xx_irq_init(env);
2108
        break;
2109

    
2110
    case CPU_PPC_603:     /* PowerPC 603                   */
2111
    case CPU_PPC_603E:    /* PowerPC 603e                  */
2112
    case CPU_PPC_603E7v:
2113
    case CPU_PPC_603E7v2:
2114
    case CPU_PPC_603P:    /* PowerPC 603p                  */
2115
    case CPU_PPC_603R:    /* PowerPC 603r                  */
2116
        gen_spr_generic(env);
2117
        gen_spr_ne_601(env);
2118
        /* Memory management */
2119
        gen_low_BATs(env);
2120
        /* Time base */
2121
        gen_tbl(env);
2122
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2123
        gen_spr_603(env);
2124
        /* hardware implementation registers */
2125
        /* XXX : not implemented */
2126
        spr_register(env, SPR_HID0, "HID0",
2127
                     SPR_NOACCESS, SPR_NOACCESS,
2128
                     &spr_read_generic, &spr_write_generic,
2129
                     0x00000000);
2130
        /* XXX : not implemented */
2131
        spr_register(env, SPR_HID1, "HID1",
2132
                     SPR_NOACCESS, SPR_NOACCESS,
2133
                     &spr_read_generic, &spr_write_generic,
2134
                     0x00000000);
2135
        /* Allocate hardware IRQ controller */
2136
        ppc6xx_irq_init(env);
2137
        break;
2138
        
2139
    case CPU_PPC_G2:      /* PowerPC G2 family             */
2140
    case CPU_PPC_G2H4:
2141
    case CPU_PPC_G2gp:
2142
    case CPU_PPC_G2ls:
2143
    case CPU_PPC_G2LE:    /* PowerPC G2LE family           */
2144
    case CPU_PPC_G2LEgp:
2145
    case CPU_PPC_G2LEls:
2146
        gen_spr_generic(env);
2147
        gen_spr_ne_601(env);
2148
        /* Memory management */
2149
        gen_low_BATs(env);
2150
        /* Time base */
2151
        gen_tbl(env);
2152
        /* Memory management */
2153
        gen_high_BATs(env);
2154
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2155
        gen_spr_G2_755(env);
2156
        gen_spr_G2(env);
2157
        /* Hardware implementation register */
2158
        /* XXX : not implemented */
2159
        spr_register(env, SPR_HID0, "HID0",
2160
                     SPR_NOACCESS, SPR_NOACCESS,
2161
                     &spr_read_generic, &spr_write_generic,
2162
                     0x00000000);
2163
        /* XXX : not implemented */
2164
        spr_register(env, SPR_HID1, "HID1",
2165
                     SPR_NOACCESS, SPR_NOACCESS,
2166
                     &spr_read_generic, &spr_write_generic,
2167
                     0x00000000);
2168
        /* XXX : not implemented */
2169
        spr_register(env, SPR_HID2, "HID2",
2170
                     SPR_NOACCESS, SPR_NOACCESS,
2171
                     &spr_read_generic, &spr_write_generic,
2172
                     0x00000000);
2173
        /* Allocate hardware IRQ controller */
2174
        ppc6xx_irq_init(env);
2175
        break;
2176

    
2177
    case CPU_PPC_604:     /* PowerPC 604                   */
2178
    case CPU_PPC_604E:    /* PowerPC 604e                  */
2179
    case CPU_PPC_604R:    /* PowerPC 604r                  */
2180
        gen_spr_generic(env);
2181
        gen_spr_ne_601(env);
2182
        /* Memory management */
2183
        gen_low_BATs(env);
2184
        /* Time base */
2185
        gen_tbl(env);
2186
        gen_spr_604(env);
2187
        /* Hardware implementation registers */
2188
        /* XXX : not implemented */
2189
        spr_register(env, SPR_HID0, "HID0",
2190
                     SPR_NOACCESS, SPR_NOACCESS,
2191
                     &spr_read_generic, &spr_write_generic,
2192
                     0x00000000);
2193
        /* XXX : not implemented */
2194
        spr_register(env, SPR_HID1, "HID1",
2195
                     SPR_NOACCESS, SPR_NOACCESS,
2196
                     &spr_read_generic, &spr_write_generic,
2197
                     0x00000000);
2198
        /* Allocate hardware IRQ controller */
2199
        ppc6xx_irq_init(env);
2200
        break;
2201

    
2202
    case CPU_PPC_74x:     /* PowerPC 740 / 750             */
2203
    case CPU_PPC_740E:
2204
    case CPU_PPC_750E:
2205
    case CPU_PPC_74xP:    /* PowerPC 740P / 750P           */
2206
    case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe            */
2207
    case CPU_PPC_750CXE22:
2208
    case CPU_PPC_750CXE23:
2209
    case CPU_PPC_750CXE24:
2210
    case CPU_PPC_750CXE24b:
2211
    case CPU_PPC_750CXE31:
2212
    case CPU_PPC_750CXE31b:
2213
    case CPU_PPC_750CXR:
2214
        gen_spr_generic(env);
2215
        gen_spr_ne_601(env);
2216
        /* Memory management */
2217
        gen_low_BATs(env);
2218
        /* Time base */
2219
        gen_tbl(env);
2220
        gen_spr_7xx(env);
2221
        /* Hardware implementation registers */
2222
        /* XXX : not implemented */
2223
        spr_register(env, SPR_HID0, "HID0",
2224
                     SPR_NOACCESS, SPR_NOACCESS,
2225
                     &spr_read_generic, &spr_write_generic,
2226
                     0x00000000);
2227
        /* XXX : not implemented */
2228
        spr_register(env, SPR_HID1, "HID1",
2229
                     SPR_NOACCESS, SPR_NOACCESS,
2230
                     &spr_read_generic, &spr_write_generic,
2231
                     0x00000000);
2232
        /* Allocate hardware IRQ controller */
2233
        ppc6xx_irq_init(env);
2234
        break;
2235

    
2236
    case CPU_PPC_750FX10: /* IBM PowerPC 750 FX            */
2237
    case CPU_PPC_750FX20:
2238
    case CPU_PPC_750FX21:
2239
    case CPU_PPC_750FX22:
2240
    case CPU_PPC_750FX23:
2241
    case CPU_PPC_750GX10: /* IBM PowerPC 750 GX            */
2242
    case CPU_PPC_750GX11:
2243
    case CPU_PPC_750GX12:
2244
        gen_spr_generic(env);
2245
        gen_spr_ne_601(env);
2246
        /* Memory management */
2247
        gen_low_BATs(env);
2248
        /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2249
        gen_high_BATs(env);
2250
        /* Time base */
2251
        gen_tbl(env);
2252
        gen_spr_7xx(env);
2253
        /* Hardware implementation registers */
2254
        /* XXX : not implemented */
2255
        spr_register(env, SPR_HID0, "HID0",
2256
                     SPR_NOACCESS, SPR_NOACCESS,
2257
                     &spr_read_generic, &spr_write_generic,
2258
                     0x00000000);
2259
        /* XXX : not implemented */
2260
        spr_register(env, SPR_HID1, "HID1",
2261
                     SPR_NOACCESS, SPR_NOACCESS,
2262
                     &spr_read_generic, &spr_write_generic,
2263
                     0x00000000);
2264
        /* XXX : not implemented */
2265
        spr_register(env, SPR_750_HID2, "HID2",
2266
                     SPR_NOACCESS, SPR_NOACCESS,
2267
                     &spr_read_generic, &spr_write_generic,
2268
                     0x00000000);
2269
        /* Allocate hardware IRQ controller */
2270
        ppc6xx_irq_init(env);
2271
        break;
2272

    
2273
    case CPU_PPC_755_10:  /* PowerPC 755                   */
2274
    case CPU_PPC_755_11:
2275
    case CPU_PPC_755_20:
2276
    case CPU_PPC_755D:
2277
    case CPU_PPC_755E:
2278
        gen_spr_generic(env);
2279
        gen_spr_ne_601(env);
2280
        /* Memory management */
2281
        gen_low_BATs(env);
2282
        /* Time base */
2283
        gen_tbl(env);
2284
        /* Memory management */
2285
        gen_high_BATs(env);
2286
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2287
        gen_spr_G2_755(env);
2288
        /* L2 cache control */
2289
        /* XXX : not implemented */
2290
        spr_register(env, SPR_ICTC, "ICTC",
2291
                     SPR_NOACCESS, SPR_NOACCESS,
2292
                     &spr_read_generic, &spr_write_generic,
2293
                     0x00000000);
2294
        /* XXX : not implemented */
2295
        spr_register(env, SPR_L2PM, "L2PM",
2296
                     SPR_NOACCESS, SPR_NOACCESS,
2297
                     &spr_read_generic, &spr_write_generic,
2298
                     0x00000000);
2299
        /* Hardware implementation registers */
2300
        /* XXX : not implemented */
2301
        spr_register(env, SPR_HID0, "HID0",
2302
                     SPR_NOACCESS, SPR_NOACCESS,
2303
                     &spr_read_generic, &spr_write_generic,
2304
                     0x00000000);
2305
        /* XXX : not implemented */
2306
        spr_register(env, SPR_HID1, "HID1",
2307
                     SPR_NOACCESS, SPR_NOACCESS,
2308
                     &spr_read_generic, &spr_write_generic,
2309
                     0x00000000);
2310
        /* XXX : not implemented */
2311
        spr_register(env, SPR_HID2, "HID2",
2312
                     SPR_NOACCESS, SPR_NOACCESS,
2313
                     &spr_read_generic, &spr_write_generic,
2314
                     0x00000000);
2315
        /* Allocate hardware IRQ controller */
2316
        ppc6xx_irq_init(env);
2317
        break;
2318

    
2319
#if defined (TODO)
2320
    /* G4 family */
2321
    case CPU_PPC_7400:    /* PowerPC 7400                  */
2322
    case CPU_PPC_7410C:   /* PowerPC 7410                  */
2323
    case CPU_PPC_7410D:
2324
    case CPU_PPC_7410E:
2325
    case CPU_PPC_7441:    /* PowerPC 7441                  */
2326
    case CPU_PPC_7445:    /* PowerPC 7445                  */
2327
    case CPU_PPC_7447:    /* PowerPC 7447                  */
2328
    case CPU_PPC_7447A:   /* PowerPC 7447A                 */
2329
    case CPU_PPC_7448:    /* PowerPC 7448                  */
2330
    case CPU_PPC_7450:    /* PowerPC 7450                  */
2331
    case CPU_PPC_7450b:
2332
    case CPU_PPC_7451:    /* PowerPC 7451                  */
2333
    case CPU_PPC_7451G:
2334
    case CPU_PPC_7455:    /* PowerPC 7455                  */
2335
    case CPU_PPC_7455F:
2336
    case CPU_PPC_7455G:
2337
    case CPU_PPC_7457:    /* PowerPC 7457                  */
2338
    case CPU_PPC_7457C:
2339
    case CPU_PPC_7457A:   /* PowerPC 7457A                 */
2340
        break;
2341
#endif
2342

    
2343
    /* 64 bits PowerPC                                     */
2344
#if defined (TARGET_PPC64)
2345
#if defined (TODO)
2346
    case CPU_PPC_620:     /* PowerPC 620                   */
2347
    case CPU_PPC_630:     /* PowerPC 630 (Power 3)         */
2348
    case CPU_PPC_631:     /* PowerPC 631 (Power 3+)        */
2349
    case CPU_PPC_POWER4:  /* Power 4                       */
2350
    case CPU_PPC_POWER4P: /* Power 4+                      */
2351
    case CPU_PPC_POWER5:  /* Power 5                       */
2352
    case CPU_PPC_POWER5P: /* Power 5+                      */
2353
#endif
2354
        break;
2355

    
2356
    case CPU_PPC_970:     /* PowerPC 970                   */
2357
    case CPU_PPC_970FX10: /* PowerPC 970 FX                */
2358
    case CPU_PPC_970FX20:
2359
    case CPU_PPC_970FX21:
2360
    case CPU_PPC_970FX30:
2361
    case CPU_PPC_970FX31:
2362
    case CPU_PPC_970MP10: /* PowerPC 970 MP                */
2363
    case CPU_PPC_970MP11:
2364
        gen_spr_generic(env);
2365
        gen_spr_ne_601(env);
2366
        /* XXX: not correct */
2367
        gen_low_BATs(env);
2368
        /* Time base */
2369
        gen_tbl(env);
2370
        gen_spr_7xx(env);
2371
        /* Hardware implementation registers */
2372
        /* XXX : not implemented */
2373
        spr_register(env, SPR_HID0, "HID0",
2374
                     SPR_NOACCESS, SPR_NOACCESS,
2375
                     &spr_read_generic, &spr_write_generic,
2376
                     0x00000000);
2377
        /* XXX : not implemented */
2378
        spr_register(env, SPR_HID1, "HID1",
2379
                     SPR_NOACCESS, SPR_NOACCESS,
2380
                     &spr_read_generic, &spr_write_generic,
2381
                     0x00000000);
2382
        /* XXX : not implemented */
2383
        spr_register(env, SPR_750_HID2, "HID2",
2384
                     SPR_NOACCESS, SPR_NOACCESS,
2385
                     &spr_read_generic, &spr_write_generic,
2386
                     0x00000000);
2387
        /* Allocate hardware IRQ controller */
2388
        ppc970_irq_init(env);
2389
        break;
2390

    
2391
#if defined (TODO)
2392
    case CPU_PPC_CELL10:  /* Cell family                   */
2393
    case CPU_PPC_CELL20:
2394
    case CPU_PPC_CELL30:
2395
    case CPU_PPC_CELL31:
2396
#endif
2397
        break;
2398

    
2399
#if defined (TODO)
2400
    case CPU_PPC_RS64:    /* Apache (RS64/A35)             */
2401
    case CPU_PPC_RS64II:  /* NorthStar (RS64-II/A50)       */
2402
    case CPU_PPC_RS64III: /* Pulsar (RS64-III)             */
2403
    case CPU_PPC_RS64IV:  /* IceStar/IStar/SStar (RS64-IV) */
2404
#endif
2405
        break;
2406
#endif /* defined (TARGET_PPC64) */
2407

    
2408
#if defined (TODO)
2409
        /* POWER                                               */
2410
    case CPU_POWER:       /* POWER                         */
2411
    case CPU_POWER2:      /* POWER2                        */
2412
        break;
2413
#endif
2414

    
2415
    default:
2416
        gen_spr_generic(env);
2417
        /* XXX: TODO: allocate internal IRQ controller */
2418
        break;
2419
    }
2420
    if (env->nb_BATs == -1)
2421
        env->nb_BATs = 4;
2422
    /* Allocate TLBs buffer when needed */
2423
    if (env->nb_tlb != 0) {
2424
        int nb_tlb = env->nb_tlb;
2425
        if (env->id_tlbs != 0)
2426
            nb_tlb *= 2;
2427
        env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2428
        /* Pre-compute some useful values */
2429
        env->tlb_per_way = env->nb_tlb / env->nb_ways;
2430
    }
2431
}
2432

    
2433
#if defined(PPC_DUMP_CPU)
2434
static void dump_sprs (CPUPPCState *env)
2435
{
2436
    ppc_spr_t *spr;
2437
    uint32_t pvr = env->spr[SPR_PVR];
2438
    uint32_t sr, sw, ur, uw;
2439
    int i, j, n;
2440

    
2441
    printf("* SPRs for PVR=%08x\n", pvr);
2442
    for (i = 0; i < 32; i++) {
2443
        for (j = 0; j < 32; j++) {
2444
            n = (i << 5) | j;
2445
            spr = &env->spr_cb[n];
2446
#if !defined(CONFIG_USER_ONLY)
2447
            sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2448
            sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
2449
#else
2450
            sw = 0;
2451
            sr = 0;
2452
#endif
2453
            uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2454
            ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2455
            if (sw || sr || uw || ur) {
2456
                printf("%4d (%03x) %8s s%c%c u%c%c\n",
2457
                       (i << 5) | j, (i << 5) | j, spr->name,
2458
                       sw ? 'w' : '-', sr ? 'r' : '-',
2459
                       uw ? 'w' : '-', ur ? 'r' : '-');
2460
            }
2461
        }
2462
    }
2463
    fflush(stdout);
2464
    fflush(stderr);
2465
}
2466
#endif
2467

    
2468
/*****************************************************************************/
2469
#include <stdlib.h>
2470
#include <string.h>
2471

    
2472
int fflush (FILE *stream);
2473

    
2474
/* Opcode types */
2475
enum {
2476
    PPC_DIRECT   = 0, /* Opcode routine        */
2477
    PPC_INDIRECT = 1, /* Indirect opcode table */
2478
};
2479

    
2480
static inline int is_indirect_opcode (void *handler)
2481
{
2482
    return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2483
}
2484

    
2485
static inline opc_handler_t **ind_table(void *handler)
2486
{
2487
    return (opc_handler_t **)((unsigned long)handler & ~3);
2488
}
2489

    
2490
/* Instruction table creation */
2491
/* Opcodes tables creation */
2492
static void fill_new_table (opc_handler_t **table, int len)
2493
{
2494
    int i;
2495

    
2496
    for (i = 0; i < len; i++)
2497
        table[i] = &invalid_handler;
2498
}
2499

    
2500
static int create_new_table (opc_handler_t **table, unsigned char idx)
2501
{
2502
    opc_handler_t **tmp;
2503

    
2504
    tmp = malloc(0x20 * sizeof(opc_handler_t));
2505
    if (tmp == NULL)
2506
        return -1;
2507
    fill_new_table(tmp, 0x20);
2508
    table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2509

    
2510
    return 0;
2511
}
2512

    
2513
static int insert_in_table (opc_handler_t **table, unsigned char idx,
2514
                            opc_handler_t *handler)
2515
{
2516
    if (table[idx] != &invalid_handler)
2517
        return -1;
2518
    table[idx] = handler;
2519

    
2520
    return 0;
2521
}
2522

    
2523
static int register_direct_insn (opc_handler_t **ppc_opcodes,
2524
                                 unsigned char idx, opc_handler_t *handler)
2525
{
2526
    if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2527
        printf("*** ERROR: opcode %02x already assigned in main "
2528
               "opcode table\n", idx);
2529
        return -1;
2530
    }
2531

    
2532
    return 0;
2533
}
2534

    
2535
static int register_ind_in_table (opc_handler_t **table,
2536
                                  unsigned char idx1, unsigned char idx2,
2537
                                  opc_handler_t *handler)
2538
{
2539
    if (table[idx1] == &invalid_handler) {
2540
        if (create_new_table(table, idx1) < 0) {
2541
            printf("*** ERROR: unable to create indirect table "
2542
                   "idx=%02x\n", idx1);
2543
            return -1;
2544
        }
2545
    } else {
2546
        if (!is_indirect_opcode(table[idx1])) {
2547
            printf("*** ERROR: idx %02x already assigned to a direct "
2548
                   "opcode\n", idx1);
2549
            return -1;
2550
        }
2551
    }
2552
    if (handler != NULL &&
2553
        insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2554
        printf("*** ERROR: opcode %02x already assigned in "
2555
               "opcode table %02x\n", idx2, idx1);
2556
        return -1;
2557
    }
2558

    
2559
    return 0;
2560
}
2561

    
2562
static int register_ind_insn (opc_handler_t **ppc_opcodes,
2563
                              unsigned char idx1, unsigned char idx2,
2564
                              opc_handler_t *handler)
2565
{
2566
    int ret;
2567

    
2568
    ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2569

    
2570
    return ret;
2571
}
2572

    
2573
static int register_dblind_insn (opc_handler_t **ppc_opcodes, 
2574
                                 unsigned char idx1, unsigned char idx2,
2575
                                 unsigned char idx3, opc_handler_t *handler)
2576
{
2577
    if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2578
        printf("*** ERROR: unable to join indirect table idx "
2579
               "[%02x-%02x]\n", idx1, idx2);
2580
        return -1;
2581
    }
2582
    if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2583
                              handler) < 0) {
2584
        printf("*** ERROR: unable to insert opcode "
2585
               "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2586
        return -1;
2587
    }
2588

    
2589
    return 0;
2590
}
2591

    
2592
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2593
{
2594
    if (insn->opc2 != 0xFF) {
2595
        if (insn->opc3 != 0xFF) {
2596
            if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2597
                                     insn->opc3, &insn->handler) < 0)
2598
                return -1;
2599
        } else {
2600
            if (register_ind_insn(ppc_opcodes, insn->opc1,
2601
                                  insn->opc2, &insn->handler) < 0)
2602
                return -1;
2603
        }
2604
    } else {
2605
        if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2606
            return -1;
2607
    }
2608

    
2609
    return 0;
2610
}
2611

    
2612
static int test_opcode_table (opc_handler_t **table, int len)
2613
{
2614
    int i, count, tmp;
2615

    
2616
    for (i = 0, count = 0; i < len; i++) {
2617
        /* Consistency fixup */
2618
        if (table[i] == NULL)
2619
            table[i] = &invalid_handler;
2620
        if (table[i] != &invalid_handler) {
2621
            if (is_indirect_opcode(table[i])) {
2622
                tmp = test_opcode_table(ind_table(table[i]), 0x20);
2623
                if (tmp == 0) {
2624
                    free(table[i]);
2625
                    table[i] = &invalid_handler;
2626
                } else {
2627
                    count++;
2628
                }
2629
            } else {
2630
                count++;
2631
            }
2632
        }
2633
    }
2634

    
2635
    return count;
2636
}
2637

    
2638
static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2639
{
2640
    if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2641
        printf("*** WARNING: no opcode defined !\n");
2642
}
2643

    
2644
/*****************************************************************************/
2645
static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2646
{
2647
    opcode_t *opc, *start, *end;
2648

    
2649
    fill_new_table(env->opcodes, 0x40);
2650
#if defined(PPC_DUMP_CPU)
2651
    printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
2652
           " %08x\n",
2653
           def->pvr, def->name, def->insns_flags, def->flags);
2654
#endif
2655
    if (&opc_start < &opc_end) {
2656
        start = &opc_start;
2657
        end = &opc_end;
2658
    } else {
2659
        start = &opc_end;
2660
        end = &opc_start;
2661
    }
2662
    for (opc = start + 1; opc != end; opc++) {
2663
        if ((opc->handler.type & def->insns_flags) != 0) {
2664
            if (register_insn(env->opcodes, opc) < 0) {
2665
                printf("*** ERROR initializing PowerPC instruction "
2666
                       "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2667
                       opc->opc3);
2668
                return -1;
2669
            }
2670
#if defined(PPC_DUMP_CPU)
2671
            if (opc1 != 0x00) {
2672
                if (opc->opc3 == 0xFF) {
2673
                    if (opc->opc2 == 0xFF) {
2674
                        printf(" %02x -- -- (%2d ----) : %s\n",
2675
                               opc->opc1, opc->opc1, opc->oname);
2676
                    } else {
2677
                        printf(" %02x %02x -- (%2d %4d) : %s\n",
2678
                               opc->opc1, opc->opc2, opc->opc1, opc->opc2,
2679
                               opc->oname);
2680
                    }
2681
                } else {
2682
                    printf(" %02x %02x %02x (%2d %4d) : %s\n",
2683
                           opc->opc1, opc->opc2, opc->opc3,
2684
                           opc->opc1, (opc->opc3 << 5) | opc->opc2,
2685
                           opc->oname);
2686
                }
2687
            }
2688
#endif
2689
        }
2690
    }
2691
    fix_opcode_tables(env->opcodes);
2692
    fflush(stdout);
2693
    fflush(stderr);
2694

    
2695
    return 0;
2696
}
2697

    
2698
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2699
{
2700
    env->msr_mask = def->msr_mask;
2701
    env->flags = def->flags;
2702
    if (create_ppc_opcodes(env, def) < 0)
2703
        return -1;
2704
    init_ppc_proc(env, def);
2705
#if defined(PPC_DUMP_CPU)
2706
    dump_sprs(env);
2707
    if (env->tlb != NULL) {
2708
        printf("%d %s TLB in %d ways\n", env->nb_tlb,
2709
               env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2710
    }
2711
#endif
2712

    
2713
    return 0;
2714
}
2715

    
2716
/*****************************************************************************/
2717
/* PowerPC CPU definitions */
2718
static ppc_def_t ppc_defs[] = {
2719
    /* Embedded PowerPC */
2720
#if defined (TODO)
2721
    /* PowerPC 401 */
2722
    {
2723
        .name        = "401",
2724
        .pvr         = CPU_PPC_401,
2725
        .pvr_mask    = 0xFFFF0000,
2726
        .insns_flags = PPC_INSNS_401,
2727
        .flags       = PPC_FLAGS_401,
2728
        .msr_mask    = xxx,
2729
    },
2730
#endif
2731
#if defined (TODO)
2732
    /* IOP480 (401 microcontroler) */
2733
    {
2734
        .name        = "iop480",
2735
        .pvr         = CPU_PPC_IOP480,
2736
        .pvr_mask    = 0xFFFF0000,
2737
        .insns_flags = PPC_INSNS_401,
2738
        .flags       = PPC_FLAGS_401,
2739
        .msr_mask    = xxx,
2740
    },
2741
#endif
2742
#if defined (TODO)
2743
    /* IBM Processor for Network Resources */
2744
    {
2745
        .name        = "Cobra",
2746
        .pvr         = CPU_PPC_COBRA,
2747
        .pvr_mask    = 0xFFFF0000,
2748
        .insns_flags = PPC_INSNS_401,
2749
        .flags       = PPC_FLAGS_401,
2750
        .msr_mask    = xxx,
2751
    },
2752
#endif
2753
#if defined (TODO)
2754
    /* Generic PowerPC 403 */
2755
    {
2756
        .name        = "403",
2757
        .pvr         = CPU_PPC_403,
2758
        .pvr_mask    = 0xFFFFFF00,
2759
        .insns_flags = PPC_INSNS_403,
2760
        .flags       = PPC_FLAGS_403,
2761
        .msr_mask    = 0x000000000007D23D,
2762
    },
2763
#endif
2764
#if defined (TODO)
2765
    /* PowerPC 403 GA */
2766
    {
2767
        .name        = "403ga",
2768
        .pvr         = CPU_PPC_403GA,
2769
        .pvr_mask    = 0xFFFFFF00,
2770
        .insns_flags = PPC_INSNS_403,
2771
        .flags       = PPC_FLAGS_403,
2772
        .msr_mask    = 0x000000000007D23D,
2773
    },
2774
#endif
2775
#if defined (TODO)
2776
    /* PowerPC 403 GB */
2777
    {
2778
        .name        = "403gb",
2779
        .pvr         = CPU_PPC_403GB,
2780
        .pvr_mask    = 0xFFFFFF00,
2781
        .insns_flags = PPC_INSNS_403,
2782
        .flags       = PPC_FLAGS_403,
2783
        .msr_mask    = 0x000000000007D23D,
2784
    },
2785
#endif
2786
#if defined (TODO)
2787
    /* PowerPC 403 GC */
2788
    {
2789
        .name        = "403gc",
2790
        .pvr         = CPU_PPC_403GC,
2791
        .pvr_mask    = 0xFFFFFF00,
2792
        .insns_flags = PPC_INSNS_403,
2793
        .flags       = PPC_FLAGS_403,
2794
        .msr_mask    = 0x000000000007D23D,
2795
    },
2796
#endif
2797
#if defined (TODO)
2798
    /* PowerPC 403 GCX */
2799
    {
2800
        .name        = "403gcx",
2801
        .pvr         = CPU_PPC_403GCX,
2802
        .pvr_mask    = 0xFFFFFF00,
2803
        .insns_flags = PPC_INSNS_403,
2804
        .flags       = PPC_FLAGS_403,
2805
        .msr_mask    = 0x000000000007D23D,
2806
    },
2807
#endif
2808
    /* Generic PowerPC 405 */
2809
    {
2810
        .name        = "405",
2811
        .pvr         = CPU_PPC_405,
2812
        .pvr_mask    = 0xFFFF0000,
2813
        .insns_flags = PPC_INSNS_405,
2814
        .flags       = PPC_FLAGS_405,
2815
        .msr_mask    = 0x00000000020EFF30,
2816
    },
2817
    /* PowerPC 405 CR */
2818
    {
2819
        .name        = "405cr",
2820
        .pvr         = CPU_PPC_405,
2821
        .pvr_mask    = 0xFFFFFFFF,
2822
        .insns_flags = PPC_INSNS_405,
2823
        .flags       = PPC_FLAGS_405,
2824
        .msr_mask    = 0x00000000020EFF30,
2825
    },
2826
#if defined (TODO)
2827
    /* PowerPC 405 GP */
2828
    {
2829
        .name        = "405gp",
2830
        .pvr         = CPU_PPC_405,
2831
        .pvr_mask    = 0xFFFFFFFF,
2832
        .insns_flags = PPC_INSNS_405,
2833
        .flags       = PPC_FLAGS_405,
2834
        .msr_mask    = 0x00000000020EFF30,
2835
    },
2836
#endif
2837
    /* PowerPC 405 EP */
2838
    {
2839
        .name        = "405ep",
2840
        .pvr         = CPU_PPC_405EP,
2841
        .pvr_mask    = 0xFFFFFFFF,
2842
        .insns_flags = PPC_INSNS_405,
2843
        .flags       = PPC_FLAGS_405,
2844
        .msr_mask    = 0x00000000020EFF30,
2845
    },
2846
#if defined (TODO)
2847
    /* PowerPC 405 EZ */
2848
    {
2849
        .name        = "405ez",
2850
        .pvr         = CPU_PPC_405EZ,
2851
        .pvr_mask    = 0xFFFFFFFF,
2852
        .insns_flags = PPC_INSNS_405,
2853
        .flags       = PPC_FLAGS_405,
2854
        .msr_mask    = 0x00000000020EFF30,
2855
    },
2856
#endif
2857
#if defined (TODO)
2858
    /* PowerPC 405 GPR */
2859
    {
2860
        .name        = "405gpr",
2861
        .pvr         = CPU_PPC_405GPR,
2862
        .pvr_mask    = 0xFFFFFFFF,
2863
        .insns_flags = PPC_INSNS_405,
2864
        .flags       = PPC_FLAGS_405,
2865
        .msr_mask    = 0x00000000020EFF30,
2866
    },
2867
#endif
2868
#if defined (TODO)
2869
    /* PowerPC 405 D2 */
2870
    {
2871
        .name        = "405d2",
2872
        .pvr         = CPU_PPC_405D2,
2873
        .pvr_mask    = 0xFFFFFFFF,
2874
        .insns_flags = PPC_INSNS_405,
2875
        .flags       = PPC_FLAGS_405,
2876
        .msr_mask    = 0x00000000020EFF30,
2877
    },
2878
#endif
2879
#if defined (TODO)
2880
    /* PowerPC 405 D4 */
2881
    {
2882
        .name        = "405d4",
2883
        .pvr         = CPU_PPC_405D4,
2884
        .pvr_mask    = 0xFFFFFFFF,
2885
        .insns_flags = PPC_INSNS_405,
2886
        .flags       = PPC_FLAGS_405,
2887
        .msr_mask    = 0x00000000020EFF30,
2888
    },
2889
#endif
2890
#if defined (TODO)
2891
    /* Npe405 H */
2892
    {
2893
        .name        = "Npe405H",
2894
        .pvr         = CPU_PPC_NPE405H,
2895
        .pvr_mask    = 0xFFFFFFFF,
2896
            .insns_flags = PPC_INSNS_405,
2897
        .flags       = PPC_FLAGS_405,
2898
        .msr_mask    = 0x00000000020EFF30,
2899
    },
2900
#endif
2901
#if defined (TODO)
2902
    /* Npe405 L */
2903
    {
2904
        .name        = "Npe405L",
2905
        .pvr         = CPU_PPC_NPE405L,
2906
        .pvr_mask    = 0xFFFFFFFF,
2907
        .insns_flags = PPC_INSNS_405,
2908
        .flags       = PPC_FLAGS_405,
2909
        .msr_mask    = 0x00000000020EFF30,
2910
    },
2911
#endif
2912
#if defined (TODO)
2913
    /* STB010000 */
2914
    {
2915
        .name        = "STB01000",
2916
        .pvr         = CPU_PPC_STB01000,
2917
        .pvr_mask    = 0xFFFFFFFF,
2918
        .insns_flags = PPC_INSNS_405,
2919
        .flags       = PPC_FLAGS_405,
2920
        .msr_mask    = 0x00000000020EFF30,
2921
    },
2922
#endif
2923
#if defined (TODO)
2924
    /* STB01010 */
2925
    {
2926
        .name        = "STB01010",
2927
        .pvr         = CPU_PPC_STB01010,
2928
        .pvr_mask    = 0xFFFFFFFF,
2929
        .insns_flags = PPC_INSNS_405,
2930
        .flags       = PPC_FLAGS_405,
2931
        .msr_mask    = 0x00000000020EFF30,
2932
    },
2933
#endif
2934
#if defined (TODO)
2935
    /* STB0210 */
2936
    {
2937
        .name        = "STB0210",
2938
        .pvr         = CPU_PPC_STB0210,
2939
        .pvr_mask    = 0xFFFFFFFF,
2940
        .insns_flags = PPC_INSNS_405,
2941
        .flags       = PPC_FLAGS_405,
2942
        .msr_mask    = 0x00000000020EFF30,
2943
    },
2944
#endif
2945
#if defined (TODO) || 1
2946
    /* STB03xx */
2947
    {
2948
        .name        = "STB03",
2949
        .pvr         = CPU_PPC_STB03,
2950
        .pvr_mask    = 0xFFFFFFFF,
2951
        .insns_flags = PPC_INSNS_405,
2952
        .flags       = PPC_FLAGS_405,
2953
        .msr_mask    = 0x00000000020EFF30,
2954
    },
2955
#endif
2956
#if defined (TODO)
2957
    /* STB043x */
2958
    {
2959
        .name        = "STB043",
2960
        .pvr         = CPU_PPC_STB043,
2961
        .pvr_mask    = 0xFFFFFFFF,
2962
        .insns_flags = PPC_INSNS_405,
2963
        .flags       = PPC_FLAGS_405,
2964
        .msr_mask    = 0x00000000020EFF30,
2965
    },
2966
#endif
2967
#if defined (TODO)
2968
    /* STB045x */
2969
    {
2970
        .name        = "STB045",
2971
        .pvr         = CPU_PPC_STB045,
2972
        .pvr_mask    = 0xFFFFFFFF,
2973
        .insns_flags = PPC_INSNS_405,
2974
        .flags       = PPC_FLAGS_405,
2975
        .msr_mask    = 0x00000000020EFF30,
2976
    },
2977
#endif
2978
#if defined (TODO) || 1
2979
    /* STB25xx */
2980
    {
2981
        .name        = "STB25",
2982
        .pvr         = CPU_PPC_STB25,
2983
        .pvr_mask    = 0xFFFFFFFF,
2984
        .insns_flags = PPC_INSNS_405,
2985
        .flags       = PPC_FLAGS_405,
2986
        .msr_mask    = 0x00000000020EFF30,
2987
    },
2988
#endif
2989
#if defined (TODO)
2990
    /* STB130 */
2991
    {
2992
        .name        = "STB130",
2993
        .pvr         = CPU_PPC_STB130,
2994
        .pvr_mask    = 0xFFFFFFFF,
2995
        .insns_flags = PPC_INSNS_405,
2996
        .flags       = PPC_FLAGS_405,
2997
        .msr_mask    = 0x00000000020EFF30,
2998
    },
2999
#endif
3000
        /* Xilinx PowerPC 405 cores */
3001
#if defined (TODO)
3002
    {
3003
        .name        = "x2vp4",
3004
        .pvr         = CPU_PPC_X2VP4,
3005
        .pvr_mask    = 0xFFFFFFFF,
3006
        .insns_flags = PPC_INSNS_405,
3007
        .flags       = PPC_FLAGS_405,
3008
        .msr_mask    = 0x00000000020EFF30,
3009
    },
3010
    {
3011
        .name        = "x2vp7",
3012
        .pvr         = CPU_PPC_X2VP7,
3013
        .pvr_mask    = 0xFFFFFFFF,
3014
        .insns_flags = PPC_INSNS_405,
3015
        .flags       = PPC_FLAGS_405,
3016
        .msr_mask    = 0x00000000020EFF30,
3017
    },
3018
    {
3019
        .name        = "x2vp20",
3020
        .pvr         = CPU_PPC_X2VP20,
3021
        .pvr_mask    = 0xFFFFFFFF,
3022
        .insns_flags = PPC_INSNS_405,
3023
        .flags       = PPC_FLAGS_405,
3024
        .msr_mask    = 0x00000000020EFF30,
3025
    },
3026
    {
3027
        .name        = "x2vp50",
3028
        .pvr         = CPU_PPC_X2VP50,
3029
        .pvr_mask    = 0xFFFFFFFF,
3030
        .insns_flags = PPC_INSNS_405,
3031
        .flags       = PPC_FLAGS_405,
3032
        .msr_mask    = 0x00000000020EFF30,
3033
    },
3034
#endif
3035
#if defined (TODO)
3036
    /* PowerPC 440 EP */
3037
    {
3038
        .name        = "440ep",
3039
        .pvr         = CPU_PPC_440EP,
3040
        .pvr_mask    = 0xFFFF0000,
3041
        .insns_flags = PPC_INSNS_440,
3042
        .flags       = PPC_FLAGS_440,
3043
        .msr_mask    = 0x000000000006D630,
3044
    },
3045
#endif
3046
#if defined (TODO)
3047
    /* PowerPC 440 GR */
3048
    {
3049
        .name        = "440gr",
3050
        .pvr         = CPU_PPC_440GR,
3051
        .pvr_mask    = 0xFFFF0000,
3052
        .insns_flags = PPC_INSNS_440,
3053
        .flags       = PPC_FLAGS_440,
3054
        .msr_mask    = 0x000000000006D630,
3055
    },
3056
#endif
3057
#if defined (TODO)
3058
    /* PowerPC 440 GP */
3059
    {
3060
        .name        = "440gp",
3061
        .pvr         = CPU_PPC_440GP,
3062
        .pvr_mask    = 0xFFFFFF00,
3063
        .insns_flags = PPC_INSNS_440,
3064
        .flags       = PPC_FLAGS_440,
3065
        .msr_mask    = 0x000000000006D630,
3066
    },
3067
#endif
3068
#if defined (TODO)
3069
    /* PowerPC 440 GX */
3070
    {
3071
        .name        = "440gx",
3072
        .pvr         = CPU_PPC_440GX,
3073
        .pvr_mask    = 0xFFFF0000,
3074
        .insns_flags = PPC_INSNS_405,
3075
        .flags       = PPC_FLAGS_440,
3076
        .msr_mask    = 0x000000000006D630,
3077
    },
3078
#endif
3079
#if defined (TODO)
3080
    /* PowerPC 440 GXc */
3081
    {
3082
        .name        = "440gxc",
3083
        .pvr         = CPU_PPC_440GXC,
3084
        .pvr_mask    = 0xFFFF0000,
3085
        .insns_flags = PPC_INSNS_405,
3086
        .flags       = PPC_FLAGS_440,
3087
        .msr_mask    = 0x000000000006D630,
3088
    },
3089
#endif
3090
#if defined (TODO)
3091
    /* PowerPC 440 GXf */
3092
    {
3093
        .name        = "440gxf",
3094
        .pvr         = CPU_PPC_440GXF,
3095
        .pvr_mask    = 0xFFFF0000,
3096
        .insns_flags = PPC_INSNS_405,
3097
        .flags       = PPC_FLAGS_440,
3098
        .msr_mask    = 0x000000000006D630,
3099
    },
3100
#endif
3101
#if defined (TODO)
3102
    /* PowerPC 440 SP */
3103
    {
3104
        .name        = "440sp",
3105
        .pvr         = CPU_PPC_440SP,
3106
        .pvr_mask    = 0xFFFF0000,
3107
        .insns_flags = PPC_INSNS_405,
3108
        .flags       = PPC_FLAGS_440,
3109
        .msr_mask    = 0x000000000006D630,
3110
    },
3111
#endif
3112
#if defined (TODO)
3113
    /* PowerPC 440 SP2 */
3114
    {
3115
        .name        = "440sp2",
3116
        .pvr         = CPU_PPC_440SP2,
3117
        .pvr_mask    = 0xFFFF0000,
3118
        .insns_flags = PPC_INSNS_405,
3119
        .flags       = PPC_FLAGS_440,
3120
        .msr_mask    = 0x000000000006D630,
3121
    },
3122
#endif
3123
#if defined (TODO)
3124
    /* PowerPC 440 SPE */
3125
    {
3126
        .name        = "440spe",
3127
        .pvr         = CPU_PPC_440SPE,
3128
        .pvr_mask    = 0xFFFF0000,
3129
        .insns_flags = PPC_INSNS_405,
3130
        .flags       = PPC_FLAGS_440,
3131
        .msr_mask    = 0x000000000006D630,
3132
    },
3133
#endif
3134
    /* Fake generic BookE PowerPC */
3135
    {
3136
        .name        = "BookE",
3137
        .pvr         = CPU_PPC_e500,
3138
        .pvr_mask    = 0xFFFFFFFF,
3139
        .insns_flags = PPC_INSNS_BOOKE,
3140
        .flags       = PPC_FLAGS_BOOKE,
3141
        .msr_mask    = 0x000000000006D630,
3142
    },
3143
    /* PowerPC 460 cores - TODO */
3144
    /* PowerPC MPC 5xx cores - TODO */
3145
    /* PowerPC MPC 8xx cores - TODO */
3146
    /* PowerPC MPC 8xxx cores - TODO */
3147
    /* e200 cores - TODO */
3148
    /* e500 cores - TODO */
3149
    /* e600 cores - TODO */
3150

    
3151
    /* 32 bits "classic" PowerPC */
3152
#if defined (TODO)
3153
    /* PowerPC 601 */
3154
    {
3155
        .name        = "601",
3156
        .pvr         = CPU_PPC_601,
3157
        .pvr_mask    = 0xFFFF0000,
3158
        .insns_flags = PPC_INSNS_601,
3159
        .flags       = PPC_FLAGS_601,
3160
        .msr_mask    = 0x000000000000FD70,
3161
    },
3162
#endif
3163
#if defined (TODO)
3164
    /* PowerPC 602 */
3165
    {
3166
        .name        = "602",
3167
        .pvr         = CPU_PPC_602,
3168
        .pvr_mask    = 0xFFFF0000,
3169
        .insns_flags = PPC_INSNS_602,
3170
        .flags       = PPC_FLAGS_602,
3171
        .msr_mask    = 0x0000000000C7FF73,
3172
    },
3173
#endif
3174
    /* PowerPC 603 */
3175
    {
3176
        .name        = "603",
3177
        .pvr         = CPU_PPC_603,
3178
        .pvr_mask    = 0xFFFFFFFF,
3179
        .insns_flags = PPC_INSNS_603,
3180
        .flags       = PPC_FLAGS_603,
3181
        .msr_mask    = 0x000000000007FF73,
3182
    },
3183
    /* PowerPC 603e */
3184
    {
3185
        .name        = "603e",
3186
        .pvr         = CPU_PPC_603E,
3187
        .pvr_mask    = 0xFFFFFFFF,
3188
        .insns_flags = PPC_INSNS_603,
3189
        .flags       = PPC_FLAGS_603,
3190
        .msr_mask    = 0x000000000007FF73,
3191
    },
3192
    {
3193
        .name        = "Stretch",
3194
        .pvr         = CPU_PPC_603E,
3195
        .pvr_mask    = 0xFFFFFFFF,
3196
        .insns_flags = PPC_INSNS_603,
3197
        .flags       = PPC_FLAGS_603,
3198
        .msr_mask    = 0x000000000007FF73,
3199
    },
3200
    /* PowerPC 603p */
3201
    {
3202
        .name        = "603p",
3203
        .pvr         = CPU_PPC_603P,
3204
        .pvr_mask    = 0xFFFFFFFF,
3205
        .insns_flags = PPC_INSNS_603,
3206
        .flags       = PPC_FLAGS_603,
3207
        .msr_mask    = 0x000000000007FF73,
3208
    },
3209
    /* PowerPC 603e7 */
3210
    {
3211
        .name        = "603e7",
3212
        .pvr         = CPU_PPC_603E7,
3213
        .pvr_mask    = 0xFFFFFFFF,
3214
        .insns_flags = PPC_INSNS_603,
3215
        .flags       = PPC_FLAGS_603,
3216
        .msr_mask    = 0x000000000007FF73,
3217
    },
3218
    /* PowerPC 603e7v */
3219
    {
3220
        .name        = "603e7v",
3221
        .pvr         = CPU_PPC_603E7v,
3222
        .pvr_mask    = 0xFFFFFFFF,
3223
        .insns_flags = PPC_INSNS_603,
3224
        .flags       = PPC_FLAGS_603,
3225
        .msr_mask    = 0x000000000007FF73,
3226
    },
3227
    /* PowerPC 603e7v2 */
3228
    {
3229
        .name        = "603e7v2",
3230
        .pvr         = CPU_PPC_603E7v2,
3231
        .pvr_mask    = 0xFFFFFFFF,
3232
        .insns_flags = PPC_INSNS_603,
3233
        .flags       = PPC_FLAGS_603,
3234
        .msr_mask    = 0x000000000007FF73,
3235
    },
3236
    /* PowerPC 603r */
3237
    {
3238
        .name        = "603r",
3239
        .pvr         = CPU_PPC_603R,
3240
        .pvr_mask    = 0xFFFFFFFF,
3241
        .insns_flags = PPC_INSNS_603,
3242
        .flags       = PPC_FLAGS_603,
3243
        .msr_mask    = 0x000000000007FF73,
3244
    },
3245
    {
3246
        .name        = "Goldeneye",
3247
        .pvr         = CPU_PPC_603R,
3248
        .pvr_mask    = 0xFFFFFFFF,
3249
        .insns_flags = PPC_INSNS_603,
3250
        .flags       = PPC_FLAGS_603,
3251
        .msr_mask    = 0x000000000007FF73,
3252
    },
3253
#if defined (TODO)
3254
    /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3255
    {
3256
        .name        = "G2",
3257
        .pvr         = CPU_PPC_G2,
3258
        .pvr_mask    = 0xFFFF0000,
3259
        .insns_flags = PPC_INSNS_G2,
3260
        .flags       = PPC_FLAGS_G2,
3261
        .msr_mask    = 0x000000000006FFF2,
3262
    },
3263
    {
3264
        .name        = "G2h4",
3265
        .pvr         = CPU_PPC_G2H4,
3266
        .pvr_mask    = 0xFFFF0000,
3267
        .insns_flags = PPC_INSNS_G2,
3268
        .flags       = PPC_FLAGS_G2,
3269
        .msr_mask    = 0x000000000006FFF2,
3270
    },
3271
    {
3272
        .name        = "G2gp",
3273
        .pvr         = CPU_PPC_G2gp,
3274
        .pvr_mask    = 0xFFFF0000,
3275
        .insns_flags = PPC_INSNS_G2,
3276
        .flags       = PPC_FLAGS_G2,
3277
        .msr_mask    = 0x000000000006FFF2,
3278
    },
3279
    {
3280
        .name        = "G2ls",
3281
        .pvr         = CPU_PPC_G2ls,
3282
        .pvr_mask    = 0xFFFF0000,
3283
        .insns_flags = PPC_INSNS_G2,
3284
        .flags       = PPC_FLAGS_G2,
3285
        .msr_mask    = 0x000000000006FFF2,
3286
    },
3287
    { /* Same as G2, with LE mode support */
3288
        .name        = "G2le",
3289
        .pvr         = CPU_PPC_G2LE,
3290
        .pvr_mask    = 0xFFFF0000,
3291
        .insns_flags = PPC_INSNS_G2,
3292
        .flags       = PPC_FLAGS_G2,
3293
        .msr_mask    = 0x000000000007FFF3,
3294
    },
3295
    {
3296
        .name        = "G2legp",
3297
        .pvr         = CPU_PPC_G2LEgp,
3298
        .pvr_mask    = 0xFFFF0000,
3299
        .insns_flags = PPC_INSNS_G2,
3300
        .flags       = PPC_FLAGS_G2,
3301
        .msr_mask    = 0x000000000007FFF3,
3302
    },
3303
    {
3304
        .name        = "G2lels",
3305
        .pvr         = CPU_PPC_G2LEls,
3306
        .pvr_mask    = 0xFFFF0000,
3307
        .insns_flags = PPC_INSNS_G2,
3308
        .flags       = PPC_FLAGS_G2,
3309
        .msr_mask    = 0x000000000007FFF3,
3310
    },
3311
#endif
3312
    /* PowerPC 604 */
3313
    {
3314
        .name        = "604",
3315
        .pvr         = CPU_PPC_604,
3316
        .pvr_mask    = 0xFFFFFFFF,
3317
        .insns_flags = PPC_INSNS_604,
3318
        .flags       = PPC_FLAGS_604,
3319
        .msr_mask    = 0x000000000005FF77,
3320
    },
3321
    /* PowerPC 604e */
3322
    {
3323
        .name        = "604e",
3324
        .pvr         = CPU_PPC_604E,
3325
        .pvr_mask    = 0xFFFFFFFF,
3326
        .insns_flags = PPC_INSNS_604,
3327
        .flags       = PPC_FLAGS_604,
3328
        .msr_mask    = 0x000000000005FF77,
3329
    },
3330
    /* PowerPC 604r */
3331
    {
3332
        .name        = "604r",
3333
        .pvr         = CPU_PPC_604R,
3334
        .pvr_mask    = 0xFFFFFFFF,
3335
        .insns_flags = PPC_INSNS_604,
3336
        .flags       = PPC_FLAGS_604,
3337
        .msr_mask    = 0x000000000005FF77,
3338
    },
3339
    /* generic G3 */
3340
    {
3341
        .name        = "G3",
3342
        .pvr         = CPU_PPC_74x,
3343
        .pvr_mask    = 0xFFFFFFFF,
3344
        .insns_flags = PPC_INSNS_7x0,
3345
        .flags       = PPC_FLAGS_7x0,
3346
        .msr_mask    = 0x000000000007FF77,
3347
    },
3348
    /* MPC740 (G3) */
3349
    {
3350
        .name        = "740",
3351
        .pvr         = CPU_PPC_74x,
3352
        .pvr_mask    = 0xFFFFFFFF,
3353
        .insns_flags = PPC_INSNS_7x0,
3354
        .flags       = PPC_FLAGS_7x0,
3355
        .msr_mask    = 0x000000000007FF77,
3356
    },
3357
    {
3358
        .name        = "Arthur",
3359
        .pvr         = CPU_PPC_74x,
3360
        .pvr_mask    = 0xFFFFFFFF,
3361
        .insns_flags = PPC_INSNS_7x0,
3362
        .flags       = PPC_FLAGS_7x0,
3363
        .msr_mask    = 0x000000000007FF77,
3364
    },
3365
#if defined (TODO)
3366
    /* MPC745 (G3) */
3367
    {
3368
        .name        = "745",
3369
        .pvr         = CPU_PPC_74x,
3370
        .pvr_mask    = 0xFFFFF000,
3371
        .insns_flags = PPC_INSNS_7x5,
3372
        .flags       = PPC_FLAGS_7x5,
3373
        .msr_mask    = 0x000000000007FF77,
3374
    },
3375
    {
3376
        .name        = "Goldfinger",
3377
        .pvr         = CPU_PPC_74x,
3378
        .pvr_mask    = 0xFFFFF000,
3379
        .insns_flags = PPC_INSNS_7x5,
3380
        .flags       = PPC_FLAGS_7x5,
3381
        .msr_mask    = 0x000000000007FF77,
3382
    },
3383
#endif
3384
    /* MPC750 (G3) */
3385
    {
3386
        .name        = "750",
3387
        .pvr         = CPU_PPC_74x,
3388
        .pvr_mask    = 0xFFFFFFFF,
3389
        .insns_flags = PPC_INSNS_7x0,
3390
        .flags       = PPC_FLAGS_7x0,
3391
        .msr_mask    = 0x000000000007FF77,
3392
    },
3393
#if defined (TODO)
3394
    /* MPC755 (G3) */
3395
    {
3396
        .name        = "755",
3397
        .pvr         = CPU_PPC_755,
3398
        .pvr_mask    = 0xFFFFF000,
3399
        .insns_flags = PPC_INSNS_7x5,
3400
        .flags       = PPC_FLAGS_7x5,
3401
        .msr_mask    = 0x000000000007FF77,
3402
    },
3403
#endif
3404
    /* MPC740P (G3) */
3405
    {
3406
        .name        = "740p",
3407
        .pvr         = CPU_PPC_74xP,
3408
        .pvr_mask    = 0xFFFFFFFF,
3409
        .insns_flags = PPC_INSNS_7x0,
3410
        .flags       = PPC_FLAGS_7x0,
3411
        .msr_mask    = 0x000000000007FF77,
3412
    },
3413
    {
3414
        .name        = "Conan/Doyle",
3415
        .pvr         = CPU_PPC_74xP,
3416
        .pvr_mask    = 0xFFFFFFFF,
3417
        .insns_flags = PPC_INSNS_7x0,
3418
        .flags       = PPC_FLAGS_7x0,
3419
        .msr_mask    = 0x000000000007FF77,
3420
    },
3421
#if defined (TODO)
3422
    /* MPC745P (G3) */
3423
    {
3424
        .name        = "745p",
3425
        .pvr         = CPU_PPC_74xP,
3426
        .pvr_mask    = 0xFFFFF000,
3427
        .insns_flags = PPC_INSNS_7x5,
3428
        .flags       = PPC_FLAGS_7x5,
3429
        .msr_mask    = 0x000000000007FF77,
3430
    },
3431
#endif
3432
    /* MPC750P (G3) */
3433
    {
3434
        .name        = "750p",
3435
        .pvr         = CPU_PPC_74xP,
3436
        .pvr_mask    = 0xFFFFFFFF,
3437
        .insns_flags = PPC_INSNS_7x0,
3438
        .flags       = PPC_FLAGS_7x0,
3439
        .msr_mask    = 0x000000000007FF77,
3440
    },
3441
#if defined (TODO)
3442
    /* MPC755P (G3) */
3443
    {
3444
        .name        = "755p",
3445
        .pvr         = CPU_PPC_74xP,
3446
        .pvr_mask    = 0xFFFFF000,
3447
        .insns_flags = PPC_INSNS_7x5,
3448
        .flags       = PPC_FLAGS_7x5,
3449
        .msr_mask    = 0x000000000007FF77,
3450
    },
3451
#endif
3452
    /* IBM 750CXe (G3 embedded) */
3453
    {
3454
        .name        = "750cxe",
3455
        .pvr         = CPU_PPC_750CXE,
3456
        .pvr_mask    = 0xFFFFFFFF,
3457
        .insns_flags = PPC_INSNS_7x0,
3458
        .flags       = PPC_FLAGS_7x0,
3459
        .msr_mask    = 0x000000000007FF77,
3460
    },
3461
    /* IBM 750FX (G3 embedded) */
3462
    {
3463
        .name        = "750fx",
3464
        .pvr         = CPU_PPC_750FX,
3465
        .pvr_mask    = 0xFFFFFFFF,
3466
        .insns_flags = PPC_INSNS_7x0,
3467
        .flags       = PPC_FLAGS_7x0,
3468
        .msr_mask    = 0x000000000007FF77,
3469
    },
3470
    /* IBM 750GX (G3 embedded) */
3471
    {
3472
        .name        = "750gx",
3473
        .pvr         = CPU_PPC_750GX,
3474
        .pvr_mask    = 0xFFFFFFFF,
3475
        .insns_flags = PPC_INSNS_7x0,
3476
        .flags       = PPC_FLAGS_7x0,
3477
        .msr_mask    = 0x000000000007FF77,
3478
    },
3479
#if defined (TODO)
3480
    /* generic G4 */
3481
    {
3482
        .name        = "G4",
3483
        .pvr         = CPU_PPC_7400,
3484
        .pvr_mask    = 0xFFFF0000,
3485
        .insns_flags = PPC_INSNS_74xx,
3486
        .flags       = PPC_FLAGS_74xx,
3487
        .msr_mask    = 0x000000000205FF77,
3488
    },
3489
#endif
3490
#if defined (TODO)
3491
    /* PowerPC 7400 (G4) */
3492
    {
3493
        .name        = "7400",
3494
        .pvr         = CPU_PPC_7400,
3495
        .pvr_mask    = 0xFFFF0000,
3496
        .insns_flags = PPC_INSNS_74xx,
3497
        .flags       = PPC_FLAGS_74xx,
3498
        .msr_mask    = 0x000000000205FF77,
3499
    },
3500
    {
3501
        .name        = "Max",
3502
        .pvr         = CPU_PPC_7400,
3503
        .pvr_mask    = 0xFFFF0000,
3504
        .insns_flags = PPC_INSNS_74xx,
3505
        .flags       = PPC_FLAGS_74xx,
3506
        .msr_mask    = 0x000000000205FF77,
3507
    },
3508
#endif
3509
#if defined (TODO)
3510
    /* PowerPC 7410 (G4) */
3511
    {
3512
        .name        = "7410",
3513
        .pvr         = CPU_PPC_7410,
3514
        .pvr_mask    = 0xFFFF0000,
3515
        .insns_flags = PPC_INSNS_74xx,
3516
        .flags       = PPC_FLAGS_74xx,
3517
        .msr_mask    = 0x000000000205FF77,
3518
    },
3519
    {
3520
        .name        = "Nitro",
3521
        .pvr         = CPU_PPC_7410,
3522
        .pvr_mask    = 0xFFFF0000,
3523
        .insns_flags = PPC_INSNS_74xx,
3524
        .flags       = PPC_FLAGS_74xx,
3525
        .msr_mask    = 0x000000000205FF77,
3526
    },
3527
#endif
3528
    /* XXX: 7441 */
3529
    /* XXX: 7445 */
3530
    /* XXX: 7447 */
3531
    /* XXX: 7447A */
3532
#if defined (TODO)
3533
    /* PowerPC 7450 (G4) */
3534
    {
3535
        .name        = "7450",
3536
        .pvr         = CPU_PPC_7450,
3537
        .pvr_mask    = 0xFFFF0000,
3538
        .insns_flags = PPC_INSNS_74xx,
3539
        .flags       = PPC_FLAGS_74xx,
3540
        .msr_mask    = 0x000000000205FF77,
3541
    },
3542
    {
3543
        .name        = "Vger",
3544
        .pvr         = CPU_PPC_7450,
3545
        .pvr_mask    = 0xFFFF0000,
3546
        .insns_flags = PPC_INSNS_74xx,
3547
        .flags       = PPC_FLAGS_74xx,
3548
        .msr_mask    = 0x000000000205FF77,
3549
    },
3550
#endif
3551
    /* XXX: 7451 */
3552
#if defined (TODO)
3553
    /* PowerPC 7455 (G4) */
3554
    {
3555
        .name        = "7455",
3556
        .pvr         = CPU_PPC_7455,
3557
        .pvr_mask    = 0xFFFF0000,
3558
        .insns_flags = PPC_INSNS_74xx,
3559
        .flags       = PPC_FLAGS_74xx,
3560
        .msr_mask    = 0x000000000205FF77,
3561
    },
3562
    {
3563
        .name        = "Apollo 6",
3564
        .pvr         = CPU_PPC_7455,
3565
        .pvr_mask    = 0xFFFF0000,
3566
        .insns_flags = PPC_INSNS_74xx,
3567
        .flags       = PPC_FLAGS_74xx,
3568
        .msr_mask    = 0x000000000205FF77,
3569
    },
3570
#endif
3571
#if defined (TODO)
3572
    /* PowerPC 7457 (G4) */
3573
    {
3574
        .name        = "7457",
3575
        .pvr         = CPU_PPC_7457,
3576
        .pvr_mask    = 0xFFFF0000,
3577
        .insns_flags = PPC_INSNS_74xx,
3578
        .flags       = PPC_FLAGS_74xx,
3579
        .msr_mask    = 0x000000000205FF77,
3580
    },
3581
    {
3582
        .name        = "Apollo 7",
3583
        .pvr         = CPU_PPC_7457,
3584
        .pvr_mask    = 0xFFFF0000,
3585
        .insns_flags = PPC_INSNS_74xx,
3586
        .flags       = PPC_FLAGS_74xx,
3587
        .msr_mask    = 0x000000000205FF77,
3588
    },
3589
#endif
3590
#if defined (TODO)
3591
    /* PowerPC 7457A (G4) */
3592
    {
3593
        .name        = "7457A",
3594
        .pvr         = CPU_PPC_7457A,
3595
        .pvr_mask    = 0xFFFF0000,
3596
        .insns_flags = PPC_INSNS_74xx,
3597
        .flags       = PPC_FLAGS_74xx,
3598
        .msr_mask    = 0x000000000205FF77,
3599
    },
3600
    {
3601
        .name        = "Apollo 7 PM",
3602
        .pvr         = CPU_PPC_7457A,
3603
        .pvr_mask    = 0xFFFF0000,
3604
        .insns_flags = PPC_INSNS_74xx,
3605
        .flags       = PPC_FLAGS_74xx,
3606
        .msr_mask    = 0x000000000205FF77,
3607
    },
3608
#endif
3609
    /* 64 bits PowerPC */
3610
#if defined (TARGET_PPC64)
3611
#if defined (TODO)
3612
    /* PowerPC 620 */
3613
    {
3614
        .name        = "620",
3615
        .pvr         = CPU_PPC_620,
3616
        .pvr_mask    = 0xFFFF0000,
3617
        .insns_flags = PPC_INSNS_620,
3618
        .flags       = PPC_FLAGS_620,
3619
        .msr_mask    = 0x800000000005FF73,
3620
    },
3621
#endif
3622
#if defined (TODO)
3623
    /* PowerPC 630 (POWER3) */
3624
    {
3625
        .name        = "630",
3626
        .pvr         = CPU_PPC_630,
3627
        .pvr_mask    = 0xFFFF0000,
3628
        .insns_flags = PPC_INSNS_630,
3629
        .flags       = PPC_FLAGS_630,
3630
        .msr_mask    = xxx,
3631
    }
3632
    {
3633
        .name        = "POWER3",
3634
        .pvr         = CPU_PPC_630,
3635
        .pvr_mask    = 0xFFFF0000,
3636
        .insns_flags = PPC_INSNS_630,
3637
        .flags       = PPC_FLAGS_630,
3638
        .msr_mask    = xxx,
3639
    }
3640
#endif
3641
#if defined (TODO)
3642
    /* PowerPC 631 (Power 3+)*/
3643
    {
3644
        .name        = "631",
3645
        .pvr         = CPU_PPC_631,
3646
        .pvr_mask    = 0xFFFF0000,
3647
        .insns_flags = PPC_INSNS_631,
3648
        .flags       = PPC_FLAGS_631,
3649
        .msr_mask    = xxx,
3650
    },
3651
    {
3652
        .name        = "POWER3+",
3653
        .pvr         = CPU_PPC_631,
3654
        .pvr_mask    = 0xFFFF0000,
3655
        .insns_flags = PPC_INSNS_631,
3656
        .flags       = PPC_FLAGS_631,
3657
        .msr_mask    = xxx,
3658
    },
3659
#endif
3660
#if defined (TODO)
3661
    /* POWER4 */
3662
    {
3663
        .name        = "POWER4",
3664
        .pvr         = CPU_PPC_POWER4,
3665
        .pvr_mask    = 0xFFFF0000,
3666
        .insns_flags = PPC_INSNS_POWER4,
3667
        .flags       = PPC_FLAGS_POWER4,
3668
        .msr_mask    = xxx,
3669
    },
3670
#endif
3671
#if defined (TODO)
3672
    /* POWER4p */
3673
    {
3674
        .name        = "POWER4+",
3675
        .pvr         = CPU_PPC_POWER4P,
3676
        .pvr_mask    = 0xFFFF0000,
3677
        .insns_flags = PPC_INSNS_POWER4,
3678
        .flags       = PPC_FLAGS_POWER4,
3679
        .msr_mask    = xxx,
3680
    },
3681
#endif
3682
#if defined (TODO)
3683
    /* POWER5 */
3684
    {
3685
        .name        = "POWER5",
3686
        .pvr         = CPU_PPC_POWER5,
3687
        .pvr_mask    = 0xFFFF0000,
3688
        .insns_flags = PPC_INSNS_POWER5,
3689
        .flags       = PPC_FLAGS_POWER5,
3690
        .msr_mask    = xxx,
3691
    },
3692
#endif
3693
#if defined (TODO)
3694
    /* POWER5+ */
3695
    {
3696
        .name        = "POWER5+",
3697
        .pvr         = CPU_PPC_POWER5P,
3698
        .pvr_mask    = 0xFFFF0000,
3699
        .insns_flags = PPC_INSNS_POWER5,
3700
        .flags       = PPC_FLAGS_POWER5,
3701
        .msr_mask    = xxx,
3702
    },
3703
#endif
3704
#if defined (TODO) || 1
3705
    /* PowerPC 970 */
3706
    {
3707
        .name        = "970",
3708
        .pvr         = CPU_PPC_970,
3709
        .pvr_mask    = 0xFFFF0000,
3710
        .insns_flags = PPC_INSNS_970,
3711
        .flags       = PPC_FLAGS_970,
3712
        .msr_mask    = 0x900000000204FF36,
3713
    },
3714
#endif
3715
#if defined (TODO)
3716
    /* PowerPC 970FX (G5) */
3717
    {
3718
        .name        = "970fx",
3719
        .pvr         = CPU_PPC_970FX,
3720
        .pvr_mask    = 0xFFFF0000,
3721
        .insns_flags = PPC_INSNS_970FX,
3722
        .flags       = PPC_FLAGS_970FX,
3723
        .msr_mask    = 0x800000000204FF36,
3724
    },
3725
#endif
3726
#if defined (TODO)
3727
    /* RS64 (Apache/A35) */
3728
    /* This one seems to support the whole POWER2 instruction set
3729
     * and the PowerPC 64 one.
3730
     */
3731
    {
3732
        .name        = "RS64",
3733
        .pvr         = CPU_PPC_RS64,
3734
        .pvr_mask    = 0xFFFF0000,
3735
        .insns_flags = PPC_INSNS_RS64,
3736
        .flags       = PPC_FLAGS_RS64,
3737
        .msr_mask    = xxx,
3738
    },
3739
    {
3740
        .name        = "Apache",
3741
        .pvr         = CPU_PPC_RS64,
3742
        .pvr_mask    = 0xFFFF0000,
3743
        .insns_flags = PPC_INSNS_RS64,
3744
        .flags       = PPC_FLAGS_RS64,
3745
        .msr_mask    = xxx,
3746
    },
3747
    {
3748
        .name        = "A35",
3749
        .pvr         = CPU_PPC_RS64,
3750
        .pvr_mask    = 0xFFFF0000,
3751
        .insns_flags = PPC_INSNS_RS64,
3752
        .flags       = PPC_FLAGS_RS64,
3753
        .msr_mask    = xxx,
3754
    },
3755
#endif
3756
#if defined (TODO)
3757
    /* RS64-II (NorthStar/A50) */
3758
    {
3759
        .name        = "RS64-II",
3760
        .pvr         = CPU_PPC_RS64II,
3761
        .pvr_mask    = 0xFFFF0000,
3762
        .insns_flags = PPC_INSNS_RS64,
3763
        .flags       = PPC_FLAGS_RS64,
3764
        .msr_mask    = xxx,
3765
    },
3766
    {
3767
        .name        = "NortStar",
3768
        .pvr         = CPU_PPC_RS64II,
3769
        .pvr_mask    = 0xFFFF0000,
3770
        .insns_flags = PPC_INSNS_RS64,
3771
        .flags       = PPC_FLAGS_RS64,
3772
        .msr_mask    = xxx,
3773
    },
3774
    {
3775
        .name        = "A50",
3776
        .pvr         = CPU_PPC_RS64II,
3777
        .pvr_mask    = 0xFFFF0000,
3778
        .insns_flags = PPC_INSNS_RS64,
3779
        .flags       = PPC_FLAGS_RS64,
3780
        .msr_mask    = xxx,
3781
    },
3782
#endif
3783
#if defined (TODO)
3784
    /* RS64-III (Pulsar) */
3785
    {
3786
        .name        = "RS64-III",
3787
        .pvr         = CPU_PPC_RS64III,
3788
        .pvr_mask    = 0xFFFF0000,
3789
        .insns_flags = PPC_INSNS_RS64,
3790
        .flags       = PPC_FLAGS_RS64,
3791
        .msr_mask    = xxx,
3792
    },
3793
    {
3794
        .name        = "Pulsar",
3795
        .pvr         = CPU_PPC_RS64III,
3796
        .pvr_mask    = 0xFFFF0000,
3797
        .insns_flags = PPC_INSNS_RS64,
3798
        .flags       = PPC_FLAGS_RS64,
3799
        .msr_mask    = xxx,
3800
    },
3801
#endif
3802
#if defined (TODO)
3803
    /* RS64-IV (IceStar/IStar/SStar) */
3804
    {
3805
        .name        = "RS64-IV",
3806
        .pvr         = CPU_PPC_RS64IV,
3807
        .pvr_mask    = 0xFFFF0000,
3808
        .insns_flags = PPC_INSNS_RS64,
3809
        .flags       = PPC_FLAGS_RS64,
3810
        .msr_mask    = xxx,
3811
    },
3812
    {
3813
        .name        = "IceStar",
3814
        .pvr         = CPU_PPC_RS64IV,
3815
        .pvr_mask    = 0xFFFF0000,
3816
        .insns_flags = PPC_INSNS_RS64,
3817
        .flags       = PPC_FLAGS_RS64,
3818
        .msr_mask    = xxx,
3819
    },
3820
    {
3821
        .name        = "IStar",
3822
        .pvr         = CPU_PPC_RS64IV,
3823
        .pvr_mask    = 0xFFFF0000,
3824
        .insns_flags = PPC_INSNS_RS64,
3825
        .flags       = PPC_FLAGS_RS64,
3826
        .msr_mask    = xxx,
3827
    },
3828
    {
3829
        .name        = "SStar",
3830
        .pvr         = CPU_PPC_RS64IV,
3831
        .pvr_mask    = 0xFFFF0000,
3832
        .insns_flags = PPC_INSNS_RS64,
3833
        .flags       = PPC_FLAGS_RS64,
3834
        .msr_mask    = xxx,
3835
    },
3836
#endif
3837
    /* POWER */
3838
#if defined (TODO)
3839
    /* Original POWER */
3840
    {
3841
        .name        = "POWER",
3842
        .pvr         = CPU_POWER,
3843
        .pvr_mask    = 0xFFFF0000,
3844
        .insns_flags = PPC_INSNS_POWER,
3845
        .flags       = PPC_FLAGS_POWER,
3846
        .msr_mask    = xxx,
3847
    },
3848
#endif
3849
#endif /* defined (TARGET_PPC64) */
3850
#if defined (TODO)
3851
    /* POWER2 */
3852
    {
3853
        .name        = "POWER2",
3854
        .pvr         = CPU_POWER2,
3855
        .pvr_mask    = 0xFFFF0000,
3856
        .insns_flags = PPC_INSNS_POWER,
3857
        .flags       = PPC_FLAGS_POWER,
3858
        .msr_mask    = xxx,
3859
    },
3860
#endif
3861
    /* Generic PowerPCs */
3862
#if defined (TODO) || 1
3863
    {
3864
        .name        = "ppc64",
3865
        .pvr         = CPU_PPC_970,
3866
        .pvr_mask    = 0xFFFF0000,
3867
        .insns_flags = PPC_INSNS_PPC64,
3868
        .flags       = PPC_FLAGS_PPC64,
3869
        .msr_mask    = 0xA00000000204FF36,
3870
    },
3871
#endif
3872
    {
3873
        .name        = "ppc32",
3874
        .pvr         = CPU_PPC_604,
3875
        .pvr_mask    = 0xFFFFFFFF,
3876
        .insns_flags = PPC_INSNS_PPC32,
3877
        .flags       = PPC_FLAGS_PPC32,
3878
        .msr_mask    = 0x000000000005FF77,
3879
    },
3880
    /* Fallback */
3881
    {
3882
        .name        = "ppc",
3883
        .pvr         = CPU_PPC_604,
3884
        .pvr_mask    = 0xFFFFFFFF,
3885
        .insns_flags = PPC_INSNS_PPC32,
3886
        .flags       = PPC_FLAGS_PPC32,
3887
        .msr_mask    = 0x000000000005FF77,
3888
    },
3889
};
3890

    
3891
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
3892
{
3893
    int i, ret;
3894

    
3895
    ret = -1;
3896
    *def = NULL;
3897
    for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
3898
        if (strcasecmp(name, ppc_defs[i].name) == 0) {
3899
            *def = &ppc_defs[i];
3900
            ret = 0;
3901
            break;
3902
        }
3903
    }
3904

    
3905
    return ret;
3906
}
3907

    
3908
int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
3909
{
3910
    int i, ret;
3911

    
3912
    ret = -1;
3913
    *def = NULL;
3914
    for (i = 0; ppc_defs[i].name != NULL; i++) {
3915
        if ((pvr & ppc_defs[i].pvr_mask) ==
3916
            (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
3917
            *def = &ppc_defs[i];
3918
            ret = 0;
3919
            break;
3920
        }
3921
    }
3922

    
3923
    return ret;
3924
}
3925

    
3926
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3927
{
3928
    int i;
3929

    
3930
    for (i = 0; ; i++) {
3931
        (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
3932
                       ppc_defs[i].name,
3933
                       ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
3934
        if (strcmp(ppc_defs[i].name, "ppc") == 0)
3935
            break;
3936
    }
3937
}