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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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|
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static inline void set_t(void) |
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{ |
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env->sr |= SR_T; |
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} |
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|
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static inline void clr_t(void) |
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{ |
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env->sr &= ~SR_T; |
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} |
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|
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static inline void cond_t(int cond) |
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{ |
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if (cond)
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set_t(); |
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else
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clr_t(); |
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} |
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|
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void OPPROTO op_cmp_eq_imm_T0(void) |
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{ |
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cond_t((int32_t) T0 == (int32_t) PARAM1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_bf_s(void) |
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{ |
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env->delayed_pc = PARAM1; |
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if (!(env->sr & SR_T)) {
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env->flags |= DELAY_SLOT_TRUE; |
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} |
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RETURN(); |
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} |
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void OPPROTO op_bt_s(void) |
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{ |
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env->delayed_pc = PARAM1; |
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if (env->sr & SR_T) {
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env->flags |= DELAY_SLOT_TRUE; |
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} |
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RETURN(); |
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} |
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|
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void OPPROTO op_store_flags(void) |
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{ |
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env->flags &= DELAY_SLOT_TRUE; |
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env->flags |= PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bra(void) |
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{ |
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env->delayed_pc = PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_braf_T0(void) |
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{ |
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env->delayed_pc = PARAM1 + T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bsr(void) |
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{ |
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env->pr = PARAM1; |
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env->delayed_pc = PARAM2; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bsrf_T0(void) |
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{ |
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env->pr = PARAM1; |
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env->delayed_pc = PARAM1 + T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_jsr_T0(void) |
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{ |
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env->pr = PARAM1; |
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env->delayed_pc = T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_rts(void) |
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{ |
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env->delayed_pc = env->pr; |
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RETURN(); |
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} |
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|
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void OPPROTO op_ldtlb(void) |
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{ |
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helper_ldtlb(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_frchg(void) |
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{ |
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env->fpscr ^= FPSCR_FR; |
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RETURN(); |
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} |
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|
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void OPPROTO op_fschg(void) |
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{ |
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env->fpscr ^= FPSCR_SZ; |
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RETURN(); |
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} |
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|
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void OPPROTO op_rte(void) |
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{ |
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env->sr = env->ssr; |
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env->delayed_pc = env->spc; |
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RETURN(); |
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} |
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void OPPROTO op_addc_T0_T1(void) |
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{ |
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helper_addc_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_addv_T0_T1(void) |
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{ |
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helper_addv_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmp_eq_T0_T1(void) |
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{ |
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cond_t(T1 == T0); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmp_ge_T0_T1(void) |
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{ |
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cond_t((int32_t) T1 >= (int32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_gt_T0_T1(void) |
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{ |
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cond_t((int32_t) T1 > (int32_t) T0); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmp_hi_T0_T1(void) |
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{ |
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cond_t((uint32_t) T1 > (uint32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_hs_T0_T1(void) |
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{ |
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cond_t((uint32_t) T1 >= (uint32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_str_T0_T1(void) |
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{ |
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cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || |
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(T0 & 0x0000ff00) == (T1 & 0x0000ff00) || |
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(T0 & 0x00ff0000) == (T1 & 0x00ff0000) || |
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(T0 & 0xff000000) == (T1 & 0xff000000)); |
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RETURN(); |
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} |
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void OPPROTO op_tst_T0_T1(void) |
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{ |
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cond_t((T1 & T0) == 0);
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RETURN(); |
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} |
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void OPPROTO op_div0s_T0_T1(void) |
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{ |
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if (T1 & 0x80000000) |
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env->sr |= SR_Q; |
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else
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env->sr &= ~SR_Q; |
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if (T0 & 0x80000000) |
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env->sr |= SR_M; |
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else
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env->sr &= ~SR_M; |
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cond_t((T1 ^ T0) & 0x80000000);
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RETURN(); |
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} |
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void OPPROTO op_div1_T0_T1(void) |
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{ |
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helper_div1_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_dmulsl_T0_T1(void) |
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{ |
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helper_dmulsl_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_dmulul_T0_T1(void) |
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{ |
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helper_dmulul_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_macl_T0_T1(void) |
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{ |
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helper_macl_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_macw_T0_T1(void) |
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{ |
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helper_macw_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_mull_T0_T1(void) |
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{ |
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env->macl = (T0 * T1) & 0xffffffff;
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RETURN(); |
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} |
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void OPPROTO op_mulsw_T0_T1(void) |
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{ |
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env->macl = (int32_t)(int16_t) T0 *(int32_t)(int16_t) T1; |
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RETURN(); |
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} |
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void OPPROTO op_muluw_T0_T1(void) |
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{ |
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env->macl = (uint32_t)(uint16_t) T0 *(uint32_t)(uint16_t) T1; |
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RETURN(); |
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} |
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void OPPROTO op_negc_T0(void) |
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{ |
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helper_negc_T0(); |
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RETURN(); |
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} |
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void OPPROTO op_shad_T0_T1(void) |
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{ |
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if ((T0 & 0x80000000) == 0) |
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T1 <<= (T0 & 0x1f);
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else if ((T0 & 0x1f) == 0) |
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T1 = (T1 & 0x80000000)? 0xffffffff : 0; |
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else
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T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); |
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RETURN(); |
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} |
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void OPPROTO op_shld_T0_T1(void) |
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{ |
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if ((T0 & 0x80000000) == 0) |
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T1 <<= (T0 & 0x1f);
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else if ((T0 & 0x1f) == 0) |
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T1 = 0;
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else
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T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); |
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RETURN(); |
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} |
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void OPPROTO op_subc_T0_T1(void) |
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{ |
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helper_subc_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_subv_T0_T1(void) |
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{ |
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helper_subv_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_trapa(void) |
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{ |
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env->tra = PARAM1 << 2;
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env->exception_index = 0x160;
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do_raise_exception(); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_pl_T0(void) |
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{ |
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cond_t((int32_t) T0 > 0);
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RETURN(); |
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} |
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void OPPROTO op_cmp_pz_T0(void) |
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{ |
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cond_t((int32_t) T0 >= 0);
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RETURN(); |
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} |
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|
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void OPPROTO op_jmp_T0(void) |
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{ |
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env->delayed_pc = T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_ldcl_rMplus_rN_bank(void) |
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{ |
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env->gregs[PARAM2] = env->gregs[PARAM1]; |
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env->gregs[PARAM1] += 4;
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RETURN(); |
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} |
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|
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void OPPROTO op_ldc_T0_sr(void) |
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{ |
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env->sr = T0 & 0x700083f3;
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RETURN(); |
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} |
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|
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void OPPROTO op_stc_sr_T0(void) |
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{ |
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T0 = env->sr; |
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RETURN(); |
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} |
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|
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#define LDSTOPS(target,load,store) \
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void OPPROTO op_##load##_T0_##target (void) \ |
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{ env ->target = T0; RETURN(); \ |
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} \ |
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void OPPROTO op_##store##_##target##_T0 (void) \ |
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{ T0 = env->target; RETURN(); \ |
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} \ |
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|
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LDSTOPS(gbr, ldc, stc) |
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LDSTOPS(vbr, ldc, stc) |
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LDSTOPS(ssr, ldc, stc) |
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LDSTOPS(spc, ldc, stc) |
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LDSTOPS(sgr, ldc, stc) |
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LDSTOPS(dbr, ldc, stc) |
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LDSTOPS(mach, lds, sts) |
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LDSTOPS(macl, lds, sts) |
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LDSTOPS(pr, lds, sts) |
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LDSTOPS(fpul, lds, sts) |
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void OPPROTO op_lds_T0_fpscr(void) |
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{ |
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env->fpscr = T0 & 0x003fffff;
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env->fp_status.float_rounding_mode = T0 & 0x01 ?
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float_round_to_zero : float_round_nearest_even; |
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|
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RETURN(); |
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} |
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|
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void OPPROTO op_sts_fpscr_T0(void) |
368 |
{ |
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T0 = env->fpscr & 0x003fffff;
|
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RETURN(); |
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} |
372 |
|
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void OPPROTO op_rotcl_Rn(void) |
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{ |
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helper_rotcl(&env->gregs[PARAM1]); |
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RETURN(); |
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} |
378 |
|
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void OPPROTO op_rotcr_Rn(void) |
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{ |
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helper_rotcr(&env->gregs[PARAM1]); |
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RETURN(); |
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} |
384 |
|
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void OPPROTO op_rotl_Rn(void) |
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{ |
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cond_t(env->gregs[PARAM1] & 0x80000000);
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env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
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RETURN(); |
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} |
391 |
|
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void OPPROTO op_rotr_Rn(void) |
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{ |
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cond_t(env->gregs[PARAM1] & 1);
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env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
|
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((env->sr & SR_T) ? 0x80000000 : 0); |
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RETURN(); |
398 |
} |
399 |
|
400 |
void OPPROTO op_shal_Rn(void) |
401 |
{ |
402 |
cond_t(env->gregs[PARAM1] & 0x80000000);
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403 |
env->gregs[PARAM1] <<= 1;
|
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RETURN(); |
405 |
} |
406 |
|
407 |
void OPPROTO op_shar_Rn(void) |
408 |
{ |
409 |
cond_t(env->gregs[PARAM1] & 1);
|
410 |
*(int32_t *)&env->gregs[PARAM1] >>= 1;
|
411 |
RETURN(); |
412 |
} |
413 |
|
414 |
void OPPROTO op_shlr_Rn(void) |
415 |
{ |
416 |
cond_t(env->gregs[PARAM1] & 1);
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417 |
env->gregs[PARAM1] >>= 1;
|
418 |
RETURN(); |
419 |
} |
420 |
|
421 |
void OPPROTO op_fmov_frN_FT0(void) |
422 |
{ |
423 |
FT0 = env->fregs[PARAM1]; |
424 |
RETURN(); |
425 |
} |
426 |
|
427 |
void OPPROTO op_fmov_drN_DT0(void) |
428 |
{ |
429 |
CPU_DoubleU d; |
430 |
|
431 |
d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
432 |
d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
433 |
DT0 = d.d; |
434 |
RETURN(); |
435 |
} |
436 |
|
437 |
void OPPROTO op_fmov_frN_FT1(void) |
438 |
{ |
439 |
FT1 = env->fregs[PARAM1]; |
440 |
RETURN(); |
441 |
} |
442 |
|
443 |
void OPPROTO op_fmov_drN_DT1(void) |
444 |
{ |
445 |
CPU_DoubleU d; |
446 |
|
447 |
d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
448 |
d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
449 |
DT1 = d.d; |
450 |
RETURN(); |
451 |
} |
452 |
|
453 |
void OPPROTO op_fmov_FT0_frN(void) |
454 |
{ |
455 |
env->fregs[PARAM1] = FT0; |
456 |
RETURN(); |
457 |
} |
458 |
|
459 |
void OPPROTO op_fmov_DT0_drN(void) |
460 |
{ |
461 |
CPU_DoubleU d; |
462 |
|
463 |
d.d = DT0; |
464 |
*(uint32_t *)&env->fregs[PARAM1] = d.l.upper; |
465 |
*(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
|
466 |
RETURN(); |
467 |
} |
468 |
|
469 |
void OPPROTO op_fadd_FT(void) |
470 |
{ |
471 |
FT0 = float32_add(FT0, FT1, &env->fp_status); |
472 |
RETURN(); |
473 |
} |
474 |
|
475 |
void OPPROTO op_fadd_DT(void) |
476 |
{ |
477 |
DT0 = float64_add(DT0, DT1, &env->fp_status); |
478 |
RETURN(); |
479 |
} |
480 |
|
481 |
void OPPROTO op_fsub_FT(void) |
482 |
{ |
483 |
FT0 = float32_sub(FT0, FT1, &env->fp_status); |
484 |
RETURN(); |
485 |
} |
486 |
|
487 |
void OPPROTO op_fsub_DT(void) |
488 |
{ |
489 |
DT0 = float64_sub(DT0, DT1, &env->fp_status); |
490 |
RETURN(); |
491 |
} |
492 |
|
493 |
void OPPROTO op_fmul_FT(void) |
494 |
{ |
495 |
FT0 = float32_mul(FT0, FT1, &env->fp_status); |
496 |
RETURN(); |
497 |
} |
498 |
|
499 |
void OPPROTO op_fmul_DT(void) |
500 |
{ |
501 |
DT0 = float64_mul(DT0, DT1, &env->fp_status); |
502 |
RETURN(); |
503 |
} |
504 |
|
505 |
void OPPROTO op_fdiv_FT(void) |
506 |
{ |
507 |
FT0 = float32_div(FT0, FT1, &env->fp_status); |
508 |
RETURN(); |
509 |
} |
510 |
|
511 |
void OPPROTO op_fdiv_DT(void) |
512 |
{ |
513 |
DT0 = float64_div(DT0, DT1, &env->fp_status); |
514 |
RETURN(); |
515 |
} |
516 |
|
517 |
void OPPROTO op_fcmp_eq_FT(void) |
518 |
{ |
519 |
cond_t(float32_compare(FT0, FT1, &env->fp_status) == 0);
|
520 |
RETURN(); |
521 |
} |
522 |
|
523 |
void OPPROTO op_fcmp_eq_DT(void) |
524 |
{ |
525 |
cond_t(float64_compare(DT0, DT1, &env->fp_status) == 0);
|
526 |
RETURN(); |
527 |
} |
528 |
|
529 |
void OPPROTO op_fcmp_gt_FT(void) |
530 |
{ |
531 |
cond_t(float32_compare(FT0, FT1, &env->fp_status) == 1);
|
532 |
RETURN(); |
533 |
} |
534 |
|
535 |
void OPPROTO op_fcmp_gt_DT(void) |
536 |
{ |
537 |
cond_t(float64_compare(DT0, DT1, &env->fp_status) == 1);
|
538 |
RETURN(); |
539 |
} |
540 |
|
541 |
void OPPROTO op_float_FT(void) |
542 |
{ |
543 |
FT0 = int32_to_float32(env->fpul, &env->fp_status); |
544 |
RETURN(); |
545 |
} |
546 |
|
547 |
void OPPROTO op_float_DT(void) |
548 |
{ |
549 |
DT0 = int32_to_float64(env->fpul, &env->fp_status); |
550 |
RETURN(); |
551 |
} |
552 |
|
553 |
void OPPROTO op_ftrc_FT(void) |
554 |
{ |
555 |
env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status); |
556 |
RETURN(); |
557 |
} |
558 |
|
559 |
void OPPROTO op_ftrc_DT(void) |
560 |
{ |
561 |
env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status); |
562 |
RETURN(); |
563 |
} |
564 |
|
565 |
void OPPROTO op_fneg_frN(void) |
566 |
{ |
567 |
env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]); |
568 |
RETURN(); |
569 |
} |
570 |
|
571 |
void OPPROTO op_fabs_FT(void) |
572 |
{ |
573 |
FT0 = float32_abs(FT0); |
574 |
RETURN(); |
575 |
} |
576 |
|
577 |
void OPPROTO op_fabs_DT(void) |
578 |
{ |
579 |
DT0 = float64_abs(DT0); |
580 |
RETURN(); |
581 |
} |
582 |
|
583 |
void OPPROTO op_fcnvsd_FT_DT(void) |
584 |
{ |
585 |
DT0 = float32_to_float64(FT0, &env->fp_status); |
586 |
RETURN(); |
587 |
} |
588 |
|
589 |
void OPPROTO op_fcnvds_DT_FT(void) |
590 |
{ |
591 |
FT0 = float64_to_float32(DT0, &env->fp_status); |
592 |
RETURN(); |
593 |
} |
594 |
|
595 |
void OPPROTO op_fsqrt_FT(void) |
596 |
{ |
597 |
FT0 = float32_sqrt(FT0, &env->fp_status); |
598 |
RETURN(); |
599 |
} |
600 |
|
601 |
void OPPROTO op_fsqrt_DT(void) |
602 |
{ |
603 |
DT0 = float64_sqrt(DT0, &env->fp_status); |
604 |
RETURN(); |
605 |
} |
606 |
|
607 |
void OPPROTO op_fmov_T0_frN(void) |
608 |
{ |
609 |
*(uint32_t *)&env->fregs[PARAM1] = T0; |
610 |
RETURN(); |
611 |
} |
612 |
|
613 |
void OPPROTO op_dt_rN(void) |
614 |
{ |
615 |
cond_t((--env->gregs[PARAM1]) == 0);
|
616 |
RETURN(); |
617 |
} |
618 |
|
619 |
void OPPROTO op_tst_imm_rN(void) |
620 |
{ |
621 |
cond_t((env->gregs[PARAM2] & PARAM1) == 0);
|
622 |
RETURN(); |
623 |
} |
624 |
|
625 |
void OPPROTO op_movl_fpul_FT0(void) |
626 |
{ |
627 |
FT0 = *(float32 *)&env->fpul; |
628 |
RETURN(); |
629 |
} |
630 |
|
631 |
void OPPROTO op_movl_FT0_fpul(void) |
632 |
{ |
633 |
*(float32 *)&env->fpul = FT0; |
634 |
RETURN(); |
635 |
} |
636 |
|
637 |
void OPPROTO op_jT(void) |
638 |
{ |
639 |
if (env->sr & SR_T)
|
640 |
GOTO_LABEL_PARAM(1);
|
641 |
RETURN(); |
642 |
} |
643 |
|
644 |
void OPPROTO op_jdelayed(void) |
645 |
{ |
646 |
if (env->flags & DELAY_SLOT_TRUE) {
|
647 |
env->flags &= ~DELAY_SLOT_TRUE; |
648 |
GOTO_LABEL_PARAM(1);
|
649 |
} |
650 |
RETURN(); |
651 |
} |
652 |
|
653 |
void OPPROTO op_movl_delayed_pc_PC(void) |
654 |
{ |
655 |
env->pc = env->delayed_pc; |
656 |
RETURN(); |
657 |
} |
658 |
|
659 |
void OPPROTO op_tst_imm_T0(void) |
660 |
{ |
661 |
cond_t((T0 & PARAM1) == 0);
|
662 |
RETURN(); |
663 |
} |
664 |
|
665 |
void OPPROTO op_raise_illegal_instruction(void) |
666 |
{ |
667 |
env->exception_index = 0x180;
|
668 |
do_raise_exception(); |
669 |
RETURN(); |
670 |
} |
671 |
|
672 |
void OPPROTO op_raise_slot_illegal_instruction(void) |
673 |
{ |
674 |
env->exception_index = 0x1a0;
|
675 |
do_raise_exception(); |
676 |
RETURN(); |
677 |
} |
678 |
|
679 |
void OPPROTO op_debug(void) |
680 |
{ |
681 |
env->exception_index = EXCP_DEBUG; |
682 |
cpu_loop_exit(); |
683 |
} |
684 |
|
685 |
void OPPROTO op_sleep(void) |
686 |
{ |
687 |
env->halted = 1;
|
688 |
env->exception_index = EXCP_HLT; |
689 |
cpu_loop_exit(); |
690 |
} |
691 |
|
692 |
/* Load and store */
|
693 |
#define MEMSUFFIX _raw
|
694 |
#include "op_mem.c" |
695 |
#undef MEMSUFFIX
|
696 |
#if !defined(CONFIG_USER_ONLY)
|
697 |
#define MEMSUFFIX _user
|
698 |
#include "op_mem.c" |
699 |
#undef MEMSUFFIX
|
700 |
|
701 |
#define MEMSUFFIX _kernel
|
702 |
#include "op_mem.c" |
703 |
#undef MEMSUFFIX
|
704 |
#endif
|