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/*
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 * QEMU i440FX/PIIX3 PCI Bridge Emulation
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 *
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 * Copyright (c) 2006 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "pci_host.h"
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#include "isa.h"
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#include "sysbus.h"
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#include "range.h"
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/*
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 * I440FX chipset data sheet.
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 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
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 */
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typedef PCIHostState I440FXState;
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#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
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#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
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#define PIIX_PIRQC              0x60
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typedef struct PIIX3State {
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    PCIDevice dev;
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    /*
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     * bitmap to track pic levels.
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     * The pic level is the logical OR of all the PCI irqs mapped to it
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     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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     *
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     * PIRQ is mapped to PIC pins, we track it by
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     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
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     * pic_irq * PIIX_NUM_PIRQS + pirq
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     */
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#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
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#error "unable to encode pic state in 64bit in pic_levels."
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#endif
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    uint64_t pic_levels;
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    qemu_irq *pic;
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    /* This member isn't used. Just for save/load compatibility */
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    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
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} PIIX3State;
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struct PCII440FXState {
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    PCIDevice dev;
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    target_phys_addr_t isa_page_descs[384 / 4];
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    uint8_t smm_enabled;
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    PIIX3State *piix3;
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};
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#define I440FX_PAM      0x59
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#define I440FX_PAM_SIZE 7
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#define I440FX_SMRAM    0x72
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static void piix3_set_irq(void *opaque, int pirq, int level);
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/* return the global irq number corresponding to a given device irq
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   pin. We could also use the bus number to have a more precise
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   mapping. */
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static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
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{
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    int slot_addend;
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    slot_addend = (pci_dev->devfn >> 3) - 1;
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    return (pci_intx + slot_addend) & 3;
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}
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static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
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{
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    uint32_t addr;
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    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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    switch(r) {
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    case 3:
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        /* RAM */
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        cpu_register_physical_memory(start, end - start,
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                                     start);
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        break;
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    case 1:
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        /* ROM (XXX: not quite correct) */
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        cpu_register_physical_memory(start, end - start,
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                                     start | IO_MEM_ROM);
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        break;
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    case 2:
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    case 0:
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        /* XXX: should distinguish read/write cases */
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        for(addr = start; addr < end; addr += 4096) {
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            cpu_register_physical_memory(addr, 4096,
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                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
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        }
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        break;
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    }
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}
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static void i440fx_update_memory_mappings(PCII440FXState *d)
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{
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    int i, r;
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    uint32_t smram, addr;
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    update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
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    for(i = 0; i < 12; i++) {
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        r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
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        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
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    }
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    smram = d->dev.config[I440FX_SMRAM];
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    if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
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        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
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    } else {
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        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
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            cpu_register_physical_memory(addr, 4096,
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                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
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        }
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    }
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}
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static void i440fx_set_smm(int val, void *arg)
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{
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    PCII440FXState *d = arg;
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    val = (val != 0);
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    if (d->smm_enabled != val) {
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        d->smm_enabled = val;
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        i440fx_update_memory_mappings(d);
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    }
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}
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/* XXX: suppress when better memory API. We make the assumption that
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   no device (in particular the VGA) changes the memory mappings in
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   the 0xa0000-0x100000 range */
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void i440fx_init_memory_mappings(PCII440FXState *d)
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{
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    int i;
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    for(i = 0; i < 96; i++) {
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        d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
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    }
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}
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static void i440fx_write_config(PCIDevice *dev,
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                                uint32_t address, uint32_t val, int len)
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{
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    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
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    /* XXX: implement SMRAM.D_LOCK */
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    pci_default_write_config(dev, address, val, len);
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    if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
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        range_covers_byte(address, len, I440FX_SMRAM)) {
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        i440fx_update_memory_mappings(d);
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    }
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}
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static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
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{
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    PCII440FXState *d = opaque;
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    int ret, i;
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    ret = pci_device_load(&d->dev, f);
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    if (ret < 0)
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        return ret;
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    i440fx_update_memory_mappings(d);
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    qemu_get_8s(f, &d->smm_enabled);
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    if (version_id == 2) {
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        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
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            qemu_get_be32(f); /* dummy load for compatibility */
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        }
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    }
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    return 0;
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}
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static int i440fx_post_load(void *opaque, int version_id)
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{
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    PCII440FXState *d = opaque;
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    i440fx_update_memory_mappings(d);
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    return 0;
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}
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static const VMStateDescription vmstate_i440fx = {
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    .name = "I440FX",
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    .version_id = 3,
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    .minimum_version_id = 3,
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    .minimum_version_id_old = 1,
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    .load_state_old = i440fx_load_old,
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    .post_load = i440fx_post_load,
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    .fields      = (VMStateField []) {
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        VMSTATE_PCI_DEVICE(dev, PCII440FXState),
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        VMSTATE_UINT8(smm_enabled, PCII440FXState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static int i440fx_pcihost_initfn(SysBusDevice *dev)
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{
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    I440FXState *s = FROM_SYSBUS(I440FXState, dev);
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    pci_host_conf_register_ioport(0xcf8, s);
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    pci_host_data_register_ioport(0xcfc, s);
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    return 0;
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}
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static int i440fx_initfn(PCIDevice *dev)
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{
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    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
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    d->dev.config[I440FX_SMRAM] = 0x02;
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    cpu_smm_register(&i440fx_set_smm, d);
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    return 0;
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}
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PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
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{
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    DeviceState *dev;
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    PCIBus *b;
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    PCIDevice *d;
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    I440FXState *s;
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    PIIX3State *piix3;
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    dev = qdev_create(NULL, "i440FX-pcihost");
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    s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
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    b = pci_bus_new(&s->busdev.qdev, NULL, 0);
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    s->bus = b;
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    qdev_init_nofail(dev);
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    d = pci_create_simple(b, 0, "i440FX");
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    *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
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    piix3 = DO_UPCAST(PIIX3State, dev,
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                      pci_create_simple_multifunction(b, -1, true, "PIIX3"));
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    piix3->pic = pic;
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    pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS);
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    (*pi440fx_state)->piix3 = piix3;
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    *piix3_devfn = piix3->dev.devfn;
261 85a750ca Juan Quintela
262 ec5f92ce Bernhard M. Wiedemann
    ram_size = ram_size / 8 / 1024 / 1024;
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    if (ram_size > 255)
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        ram_size = 255;
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    (*pi440fx_state)->dev.config[0x57]=ram_size;
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    return b;
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}
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/* PIIX3 PCI to ISA bridge */
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static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
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{
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    qemu_set_irq(piix3->pic[pic_irq],
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                 !!(piix3->pic_levels &
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                    (((1UL << PIIX_NUM_PIRQS) - 1) <<
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                     (pic_irq * PIIX_NUM_PIRQS))));
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}
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static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
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{
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    int pic_irq;
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    uint64_t mask;
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    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
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    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
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        return;
287 ab431c28 Isaku Yamahata
    }
288 ab431c28 Isaku Yamahata
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    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
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    piix3->pic_levels &= ~mask;
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    piix3->pic_levels |= mask * !!level;
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    piix3_set_irq_pic(piix3, pic_irq);
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}
295 ab431c28 Isaku Yamahata
296 ab431c28 Isaku Yamahata
static void piix3_set_irq(void *opaque, int pirq, int level)
297 502a5395 pbrook
{
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    PIIX3State *piix3 = opaque;
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    piix3_set_irq_level(piix3, pirq, level);
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}
301 502a5395 pbrook
302 ab431c28 Isaku Yamahata
/* irq routing is changed. so rebuild bitmap */
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static void piix3_update_irq_levels(PIIX3State *piix3)
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{
305 ab431c28 Isaku Yamahata
    int pirq;
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307 ab431c28 Isaku Yamahata
    piix3->pic_levels = 0;
308 ab431c28 Isaku Yamahata
    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
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        piix3_set_irq_level(piix3, pirq,
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                            pci_bus_get_irq_level(piix3->dev.bus, pirq));
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    }
312 ab431c28 Isaku Yamahata
}
313 ab431c28 Isaku Yamahata
314 ab431c28 Isaku Yamahata
static void piix3_write_config(PCIDevice *dev,
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                               uint32_t address, uint32_t val, int len)
316 ab431c28 Isaku Yamahata
{
317 ab431c28 Isaku Yamahata
    pci_default_write_config(dev, address, val, len);
318 ab431c28 Isaku Yamahata
    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
319 ab431c28 Isaku Yamahata
        PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
320 ab431c28 Isaku Yamahata
        int pic_irq;
321 ab431c28 Isaku Yamahata
        piix3_update_irq_levels(piix3);
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        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
323 ab431c28 Isaku Yamahata
            piix3_set_irq_pic(piix3, pic_irq);
324 d2b59317 pbrook
        }
325 502a5395 pbrook
    }
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}
327 502a5395 pbrook
328 15a1956a Gleb Natapov
static void piix3_reset(void *opaque)
329 502a5395 pbrook
{
330 fd37d881 Juan Quintela
    PIIX3State *d = opaque;
331 fd37d881 Juan Quintela
    uint8_t *pci_conf = d->dev.config;
332 502a5395 pbrook
333 502a5395 pbrook
    pci_conf[0x04] = 0x07; // master, memory and I/O
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    pci_conf[0x05] = 0x00;
335 502a5395 pbrook
    pci_conf[0x06] = 0x00;
336 502a5395 pbrook
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
337 502a5395 pbrook
    pci_conf[0x4c] = 0x4d;
338 502a5395 pbrook
    pci_conf[0x4e] = 0x03;
339 502a5395 pbrook
    pci_conf[0x4f] = 0x00;
340 502a5395 pbrook
    pci_conf[0x60] = 0x80;
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    pci_conf[0x61] = 0x80;
342 477afee3 aurel32
    pci_conf[0x62] = 0x80;
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    pci_conf[0x63] = 0x80;
344 502a5395 pbrook
    pci_conf[0x69] = 0x02;
345 502a5395 pbrook
    pci_conf[0x70] = 0x80;
346 502a5395 pbrook
    pci_conf[0x76] = 0x0c;
347 502a5395 pbrook
    pci_conf[0x77] = 0x0c;
348 502a5395 pbrook
    pci_conf[0x78] = 0x02;
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    pci_conf[0x79] = 0x00;
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    pci_conf[0x80] = 0x00;
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    pci_conf[0x82] = 0x00;
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    pci_conf[0xa0] = 0x08;
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    pci_conf[0xa2] = 0x00;
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    pci_conf[0xa3] = 0x00;
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    pci_conf[0xa4] = 0x00;
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    pci_conf[0xa5] = 0x00;
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    pci_conf[0xa6] = 0x00;
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    pci_conf[0xa7] = 0x00;
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    pci_conf[0xa8] = 0x0f;
360 502a5395 pbrook
    pci_conf[0xaa] = 0x00;
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    pci_conf[0xab] = 0x00;
362 502a5395 pbrook
    pci_conf[0xac] = 0x00;
363 502a5395 pbrook
    pci_conf[0xae] = 0x00;
364 ab431c28 Isaku Yamahata
365 ab431c28 Isaku Yamahata
    d->pic_levels = 0;
366 ab431c28 Isaku Yamahata
}
367 ab431c28 Isaku Yamahata
368 ab431c28 Isaku Yamahata
static int piix3_post_load(void *opaque, int version_id)
369 ab431c28 Isaku Yamahata
{
370 ab431c28 Isaku Yamahata
    PIIX3State *piix3 = opaque;
371 ab431c28 Isaku Yamahata
    piix3_update_irq_levels(piix3);
372 ab431c28 Isaku Yamahata
    return 0;
373 e735b55a Isaku Yamahata
}
374 15a1956a Gleb Natapov
375 e735b55a Isaku Yamahata
static void piix3_pre_save(void *opaque)
376 e735b55a Isaku Yamahata
{
377 e735b55a Isaku Yamahata
    int i;
378 e735b55a Isaku Yamahata
    PIIX3State *piix3 = opaque;
379 e735b55a Isaku Yamahata
380 e735b55a Isaku Yamahata
    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
381 e735b55a Isaku Yamahata
        piix3->pci_irq_levels_vmstate[i] =
382 e735b55a Isaku Yamahata
            pci_bus_get_irq_level(piix3->dev.bus, i);
383 e735b55a Isaku Yamahata
    }
384 502a5395 pbrook
}
385 502a5395 pbrook
386 d1f171bd Juan Quintela
static const VMStateDescription vmstate_piix3 = {
387 d1f171bd Juan Quintela
    .name = "PIIX3",
388 d1f171bd Juan Quintela
    .version_id = 3,
389 d1f171bd Juan Quintela
    .minimum_version_id = 2,
390 d1f171bd Juan Quintela
    .minimum_version_id_old = 2,
391 ab431c28 Isaku Yamahata
    .post_load = piix3_post_load,
392 e735b55a Isaku Yamahata
    .pre_save = piix3_pre_save,
393 d1f171bd Juan Quintela
    .fields      = (VMStateField []) {
394 d1f171bd Juan Quintela
        VMSTATE_PCI_DEVICE(dev, PIIX3State),
395 e735b55a Isaku Yamahata
        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
396 e735b55a Isaku Yamahata
                              PIIX_NUM_PIRQS, 3),
397 d1f171bd Juan Quintela
        VMSTATE_END_OF_LIST()
398 da64182c Juan Quintela
    }
399 d1f171bd Juan Quintela
};
400 1941d19c bellard
401 fd37d881 Juan Quintela
static int piix3_initfn(PCIDevice *dev)
402 502a5395 pbrook
{
403 fd37d881 Juan Quintela
    PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
404 502a5395 pbrook
405 fd37d881 Juan Quintela
    isa_bus_new(&d->dev.qdev);
406 a08d4367 Jan Kiszka
    qemu_register_reset(piix3_reset, d);
407 81a322d4 Gerd Hoffmann
    return 0;
408 502a5395 pbrook
}
409 5c2b87e3 ths
410 8a14daa5 Gerd Hoffmann
static PCIDeviceInfo i440fx_info[] = {
411 8a14daa5 Gerd Hoffmann
    {
412 8a14daa5 Gerd Hoffmann
        .qdev.name    = "i440FX",
413 8a14daa5 Gerd Hoffmann
        .qdev.desc    = "Host bridge",
414 0a3bacf3 Juan Quintela
        .qdev.size    = sizeof(PCII440FXState),
415 be73cfe2 Juan Quintela
        .qdev.vmsd    = &vmstate_i440fx,
416 8a14daa5 Gerd Hoffmann
        .qdev.no_user = 1,
417 0965f12d Gerd Hoffmann
        .no_hotplug   = 1,
418 8a14daa5 Gerd Hoffmann
        .init         = i440fx_initfn,
419 8a14daa5 Gerd Hoffmann
        .config_write = i440fx_write_config,
420 3a9d8549 Isaku Yamahata
        .vendor_id    = PCI_VENDOR_ID_INTEL,
421 3a9d8549 Isaku Yamahata
        .device_id    = PCI_DEVICE_ID_INTEL_82441,
422 3a9d8549 Isaku Yamahata
        .revision     = 0x02,
423 3a9d8549 Isaku Yamahata
        .class_id     = PCI_CLASS_BRIDGE_HOST,
424 8a14daa5 Gerd Hoffmann
    },{
425 8a14daa5 Gerd Hoffmann
        .qdev.name    = "PIIX3",
426 8a14daa5 Gerd Hoffmann
        .qdev.desc    = "ISA bridge",
427 fd37d881 Juan Quintela
        .qdev.size    = sizeof(PIIX3State),
428 be73cfe2 Juan Quintela
        .qdev.vmsd    = &vmstate_piix3,
429 8a14daa5 Gerd Hoffmann
        .qdev.no_user = 1,
430 0965f12d Gerd Hoffmann
        .no_hotplug   = 1,
431 8a14daa5 Gerd Hoffmann
        .init         = piix3_initfn,
432 ab431c28 Isaku Yamahata
        .config_write = piix3_write_config,
433 3a9d8549 Isaku Yamahata
        .vendor_id    = PCI_VENDOR_ID_INTEL,
434 3a9d8549 Isaku Yamahata
        .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
435 3a9d8549 Isaku Yamahata
        .class_id     = PCI_CLASS_BRIDGE_ISA,
436 8a14daa5 Gerd Hoffmann
    },{
437 8a14daa5 Gerd Hoffmann
        /* end of list */
438 8a14daa5 Gerd Hoffmann
    }
439 8a14daa5 Gerd Hoffmann
};
440 8a14daa5 Gerd Hoffmann
441 8a14daa5 Gerd Hoffmann
static SysBusDeviceInfo i440fx_pcihost_info = {
442 8a14daa5 Gerd Hoffmann
    .init         = i440fx_pcihost_initfn,
443 8a14daa5 Gerd Hoffmann
    .qdev.name    = "i440FX-pcihost",
444 779206de Gleb Natapov
    .qdev.fw_name = "pci",
445 8a14daa5 Gerd Hoffmann
    .qdev.size    = sizeof(I440FXState),
446 8a14daa5 Gerd Hoffmann
    .qdev.no_user = 1,
447 8a14daa5 Gerd Hoffmann
};
448 8a14daa5 Gerd Hoffmann
449 8a14daa5 Gerd Hoffmann
static void i440fx_register(void)
450 8a14daa5 Gerd Hoffmann
{
451 8a14daa5 Gerd Hoffmann
    sysbus_register_withprop(&i440fx_pcihost_info);
452 8a14daa5 Gerd Hoffmann
    pci_qdev_register_many(i440fx_info);
453 8a14daa5 Gerd Hoffmann
}
454 8a14daa5 Gerd Hoffmann
device_init(i440fx_register);