Archipelago » qemu

{

    int sci_level, pmsts;

    int64_t expire_time;

    pmsts = get_pmsts(s);

    sci_level = (((pmsts & s->pmen) &

                  (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);

{

    PIIX4PMState *s = opaque;

    uint32_t val;

    addr &= 1;

    if (addr == 0) {

        val = s->apmc;

    pci_conf[0x0b] = 0x06; // bridge device

    pci_conf[0x0e] = 0x00; // header_type

    pci_conf[0x3d] = 0x01; // interrupt pin 1

    pci_conf[0x40] = 0x01; /* PM io base read only bit */

    register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);

    register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);