Revision 3b46e624 hw/grackle_pci.c

b/hw/grackle_pci.c
118 118
    d->config[0x1a] = 0x00;  // subordinate_bus
119 119
    d->config[0x1c] = 0x00;
120 120
    d->config[0x1d] = 0x00;
121
   
121

  
122 122
    d->config[0x20] = 0x00; // memory_base
123 123
    d->config[0x21] = 0x00;
124 124
    d->config[0x22] = 0x01; // memory_limit
125 125
    d->config[0x23] = 0x00;
126
   
126

  
127 127
    d->config[0x24] = 0x00; // prefetchable_memory_base
128 128
    d->config[0x25] = 0x00;
129 129
    d->config[0x26] = 0x00; // prefetchable_memory_limit
......
145 145
    d->config[0x1a] = 0x1;  // subordinate_bus
146 146
    d->config[0x1c] = 0x10; // io_base
147 147
    d->config[0x1d] = 0x20; // io_limit
148
   
148

  
149 149
    d->config[0x20] = 0x80; // memory_base
150 150
    d->config[0x21] = 0x80;
151 151
    d->config[0x22] = 0x90; // memory_limit
152 152
    d->config[0x23] = 0x80;
153
   
153

  
154 154
    d->config[0x24] = 0x00; // prefetchable_memory_base
155 155
    d->config[0x25] = 0x84;
156 156
    d->config[0x26] = 0x00; // prefetchable_memory_limit

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