root / target-ppc / translate_init.c @ 3b46e624
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/*
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* PowerPC CPU initialization for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* A lot of PowerPC definition have been included here.
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* Most of them are not usable for now but have been kept
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* inside "#if defined(TODO) ... #endif" statements to make tests easier.
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*/
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//#define PPC_DUMP_CPU
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//#define PPC_DEBUG_SPR
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//#define PPC_DEBUG_IRQ
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struct ppc_def_t {
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const unsigned char *name; |
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uint32_t pvr; |
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uint32_t pvr_mask; |
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uint64_t insns_flags; |
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uint32_t flags; |
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uint64_t msr_mask; |
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}; |
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/* For user-mode emulation, we don't emulate any IRQ controller */
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#if defined(CONFIG_USER_ONLY)
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#define PPC_IRQ_INIT_FN(name) \
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static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ |
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{ \ |
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} |
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#else
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#define PPC_IRQ_INIT_FN(name) \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
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#endif
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PPC_IRQ_INIT_FN(405);
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PPC_IRQ_INIT_FN(6xx);
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PPC_IRQ_INIT_FN(970);
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/* Generic callbacks:
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* do nothing but store/retrieve spr value
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*/
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#ifdef PPC_DUMP_SPR_ACCESSES
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static void spr_read_generic (void *opaque, int sprn) |
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{ |
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gen_op_load_dump_spr(sprn); |
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} |
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static void spr_write_generic (void *opaque, int sprn) |
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{ |
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gen_op_store_dump_spr(sprn); |
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} |
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#else
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static void spr_read_generic (void *opaque, int sprn) |
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{ |
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gen_op_load_spr(sprn); |
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} |
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static void spr_write_generic (void *opaque, int sprn) |
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{ |
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gen_op_store_spr(sprn); |
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} |
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#endif
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_clear (void *opaque, int sprn) |
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{ |
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gen_op_mask_spr(sprn); |
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} |
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#endif
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/* SPR common to all PowerPC */
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/* XER */
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static void spr_read_xer (void *opaque, int sprn) |
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{ |
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gen_op_load_xer(); |
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} |
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static void spr_write_xer (void *opaque, int sprn) |
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{ |
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gen_op_store_xer(); |
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} |
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/* LR */
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static void spr_read_lr (void *opaque, int sprn) |
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{ |
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gen_op_load_lr(); |
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} |
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static void spr_write_lr (void *opaque, int sprn) |
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{ |
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gen_op_store_lr(); |
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} |
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/* CTR */
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static void spr_read_ctr (void *opaque, int sprn) |
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{ |
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gen_op_load_ctr(); |
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} |
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static void spr_write_ctr (void *opaque, int sprn) |
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{ |
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gen_op_store_ctr(); |
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} |
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/* User read access to SPR */
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/* USPRx */
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/* UMMCRx */
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/* UPMCx */
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/* USIA */
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/* UDECR */
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static void spr_read_ureg (void *opaque, int sprn) |
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{ |
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gen_op_load_spr(sprn + 0x10);
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} |
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/* SPR common to all non-embedded PowerPC */
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/* DECR */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_decr (void *opaque, int sprn) |
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{ |
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gen_op_load_decr(); |
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} |
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static void spr_write_decr (void *opaque, int sprn) |
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{ |
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gen_op_store_decr(); |
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} |
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#endif
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/* SPR common to all non-embedded PowerPC, except 601 */
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/* Time base */
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static void spr_read_tbl (void *opaque, int sprn) |
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{ |
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gen_op_load_tbl(); |
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} |
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static void spr_read_tbu (void *opaque, int sprn) |
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{ |
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gen_op_load_tbu(); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_tbl (void *opaque, int sprn) |
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{ |
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gen_op_store_tbl(); |
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} |
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static void spr_write_tbu (void *opaque, int sprn) |
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{ |
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gen_op_store_tbu(); |
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} |
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#endif
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#if !defined(CONFIG_USER_ONLY)
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/* IBAT0U...IBAT0U */
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/* IBAT0L...IBAT7L */
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static void spr_read_ibat (void *opaque, int sprn) |
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{ |
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gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2); |
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} |
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static void spr_read_ibat_h (void *opaque, int sprn) |
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{ |
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gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2); |
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} |
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static void spr_write_ibatu (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatu_h (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatl (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatl_h (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
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RET_STOP(ctx); |
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} |
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/* DBAT0U...DBAT7U */
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/* DBAT0L...DBAT7L */
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static void spr_read_dbat (void *opaque, int sprn) |
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{ |
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gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2); |
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} |
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static void spr_read_dbat_h (void *opaque, int sprn) |
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{ |
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gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2); |
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} |
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static void spr_write_dbatu (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatu_h (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatl (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatl_h (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
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RET_STOP(ctx); |
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} |
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/* SDR1 */
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static void spr_read_sdr1 (void *opaque, int sprn) |
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{ |
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gen_op_load_sdr1(); |
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} |
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static void spr_write_sdr1 (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_sdr1(); |
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RET_STOP(ctx); |
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} |
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/* 64 bits PowerPC specific SPRs */
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/* ASR */
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/* Currently unused */
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#if 0 && defined(TARGET_PPC64)
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static void spr_read_asr (void *opaque, int sprn)
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{
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gen_op_load_asr();
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}
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static void spr_write_asr (void *opaque, int sprn)
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{
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DisasContext *ctx = opaque;
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gen_op_store_asr();
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RET_STOP(ctx);
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}
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#endif
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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/* PowerPC 601 specific registers */
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/* RTC */
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static void spr_read_601_rtcl (void *opaque, int sprn) |
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{ |
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gen_op_load_601_rtcl(); |
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} |
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static void spr_read_601_rtcu (void *opaque, int sprn) |
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{ |
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gen_op_load_601_rtcu(); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_601_rtcu (void *opaque, int sprn) |
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{ |
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gen_op_store_601_rtcu(); |
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} |
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static void spr_write_601_rtcl (void *opaque, int sprn) |
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{ |
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gen_op_store_601_rtcl(); |
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} |
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#endif
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/* Unified bats */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_601_ubat (void *opaque, int sprn) |
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{ |
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gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2); |
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} |
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static void spr_write_601_ubatu (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_601_ubatl (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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#endif
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/* PowerPC 40x specific registers */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_40x_pit (void *opaque, int sprn) |
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{ |
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gen_op_load_40x_pit(); |
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} |
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static void spr_write_40x_pit (void *opaque, int sprn) |
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{ |
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gen_op_store_40x_pit(); |
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} |
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static void spr_write_40x_dbcr0 (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_40x_dbcr0(); |
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/* We must stop translation as we may have rebooted */
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RET_STOP(ctx); |
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} |
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static void spr_write_40x_sler (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_40x_sler(); |
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/* We must stop the translation as we may have changed
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* some regions endianness
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*/
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RET_STOP(ctx); |
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} |
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static void spr_write_booke_tcr (void *opaque, int sprn) |
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{ |
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gen_op_store_booke_tcr(); |
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} |
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static void spr_write_booke_tsr (void *opaque, int sprn) |
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{ |
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gen_op_store_booke_tsr(); |
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} |
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#endif
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/* PowerPC 403 specific registers */
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/* PBL1 / PBU1 / PBL2 / PBU2 */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_403_pbr (void *opaque, int sprn) |
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{ |
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gen_op_load_403_pb(sprn - SPR_403_PBL1); |
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} |
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static void spr_write_403_pbr (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_403_pb(sprn - SPR_403_PBL1); |
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RET_STOP(ctx); |
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} |
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static void spr_write_pir (void *opaque, int sprn) |
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{ |
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gen_op_store_pir(); |
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} |
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#endif
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#if defined(CONFIG_USER_ONLY)
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#define spr_register(env, num, name, uea_read, uea_write, \
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oea_read, oea_write, initial_value) \ |
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do { \
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_spr_register(env, num, name, uea_read, uea_write, initial_value); \ |
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} while (0) |
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static inline void _spr_register (CPUPPCState *env, int num, |
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const unsigned char *name, |
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void (*uea_read)(void *opaque, int sprn), |
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void (*uea_write)(void *opaque, int sprn), |
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target_ulong initial_value) |
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#else
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static inline void spr_register (CPUPPCState *env, int num, |
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const unsigned char *name, |
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void (*uea_read)(void *opaque, int sprn), |
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void (*uea_write)(void *opaque, int sprn), |
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void (*oea_read)(void *opaque, int sprn), |
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void (*oea_write)(void *opaque, int sprn), |
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target_ulong initial_value) |
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#endif
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{ |
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ppc_spr_t *spr; |
425 |
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spr = &env->spr_cb[num]; |
427 |
if (spr->name != NULL ||env-> spr[num] != 0x00000000 || |
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#if !defined(CONFIG_USER_ONLY)
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spr->oea_read != NULL || spr->oea_write != NULL || |
430 |
#endif
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spr->uea_read != NULL || spr->uea_write != NULL) { |
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printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
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exit(1);
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} |
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#if defined(PPC_DEBUG_SPR)
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printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name, |
437 |
initial_value); |
438 |
#endif
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spr->name = name; |
440 |
spr->uea_read = uea_read; |
441 |
spr->uea_write = uea_write; |
442 |
#if !defined(CONFIG_USER_ONLY)
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spr->oea_read = oea_read; |
444 |
spr->oea_write = oea_write; |
445 |
#endif
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env->spr[num] = initial_value; |
447 |
} |
448 |
|
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/* Generic PowerPC SPRs */
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static void gen_spr_generic (CPUPPCState *env) |
451 |
{ |
452 |
/* Integer processing */
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spr_register(env, SPR_XER, "XER",
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&spr_read_xer, &spr_write_xer, |
455 |
&spr_read_xer, &spr_write_xer, |
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0x00000000);
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/* Branch contol */
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spr_register(env, SPR_LR, "LR",
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&spr_read_lr, &spr_write_lr, |
460 |
&spr_read_lr, &spr_write_lr, |
461 |
0x00000000);
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spr_register(env, SPR_CTR, "CTR",
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&spr_read_ctr, &spr_write_ctr, |
464 |
&spr_read_ctr, &spr_write_ctr, |
465 |
0x00000000);
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/* Interrupt processing */
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spr_register(env, SPR_SRR0, "SRR0",
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SPR_NOACCESS, SPR_NOACCESS, |
469 |
&spr_read_generic, &spr_write_generic, |
470 |
0x00000000);
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spr_register(env, SPR_SRR1, "SRR1",
|
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SPR_NOACCESS, SPR_NOACCESS, |
473 |
&spr_read_generic, &spr_write_generic, |
474 |
0x00000000);
|
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/* Processor control */
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spr_register(env, SPR_SPRG0, "SPRG0",
|
477 |
SPR_NOACCESS, SPR_NOACCESS, |
478 |
&spr_read_generic, &spr_write_generic, |
479 |
0x00000000);
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spr_register(env, SPR_SPRG1, "SPRG1",
|
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SPR_NOACCESS, SPR_NOACCESS, |
482 |
&spr_read_generic, &spr_write_generic, |
483 |
0x00000000);
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spr_register(env, SPR_SPRG2, "SPRG2",
|
485 |
SPR_NOACCESS, SPR_NOACCESS, |
486 |
&spr_read_generic, &spr_write_generic, |
487 |
0x00000000);
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spr_register(env, SPR_SPRG3, "SPRG3",
|
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SPR_NOACCESS, SPR_NOACCESS, |
490 |
&spr_read_generic, &spr_write_generic, |
491 |
0x00000000);
|
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} |
493 |
|
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/* SPR common to all non-embedded PowerPC, including 601 */
|
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static void gen_spr_ne_601 (CPUPPCState *env) |
496 |
{ |
497 |
/* Exception processing */
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spr_register(env, SPR_DSISR, "DSISR",
|
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SPR_NOACCESS, SPR_NOACCESS, |
500 |
&spr_read_generic, &spr_write_generic, |
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0x00000000);
|
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spr_register(env, SPR_DAR, "DAR",
|
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SPR_NOACCESS, SPR_NOACCESS, |
504 |
&spr_read_generic, &spr_write_generic, |
505 |
0x00000000);
|
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/* Timer */
|
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spr_register(env, SPR_DECR, "DECR",
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SPR_NOACCESS, SPR_NOACCESS, |
509 |
&spr_read_decr, &spr_write_decr, |
510 |
0x00000000);
|
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/* Memory management */
|
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spr_register(env, SPR_SDR1, "SDR1",
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SPR_NOACCESS, SPR_NOACCESS, |
514 |
&spr_read_sdr1, &spr_write_sdr1, |
515 |
0x00000000);
|
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} |
517 |
|
518 |
/* BATs 0-3 */
|
519 |
static void gen_low_BATs (CPUPPCState *env) |
520 |
{ |
521 |
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
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SPR_NOACCESS, SPR_NOACCESS, |
523 |
&spr_read_ibat, &spr_write_ibatu, |
524 |
0x00000000);
|
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spr_register(env, SPR_IBAT0L, "IBAT0L",
|
526 |
SPR_NOACCESS, SPR_NOACCESS, |
527 |
&spr_read_ibat, &spr_write_ibatl, |
528 |
0x00000000);
|
529 |
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
530 |
SPR_NOACCESS, SPR_NOACCESS, |
531 |
&spr_read_ibat, &spr_write_ibatu, |
532 |
0x00000000);
|
533 |
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
534 |
SPR_NOACCESS, SPR_NOACCESS, |
535 |
&spr_read_ibat, &spr_write_ibatl, |
536 |
0x00000000);
|
537 |
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
538 |
SPR_NOACCESS, SPR_NOACCESS, |
539 |
&spr_read_ibat, &spr_write_ibatu, |
540 |
0x00000000);
|
541 |
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
542 |
SPR_NOACCESS, SPR_NOACCESS, |
543 |
&spr_read_ibat, &spr_write_ibatl, |
544 |
0x00000000);
|
545 |
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
546 |
SPR_NOACCESS, SPR_NOACCESS, |
547 |
&spr_read_ibat, &spr_write_ibatu, |
548 |
0x00000000);
|
549 |
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
550 |
SPR_NOACCESS, SPR_NOACCESS, |
551 |
&spr_read_ibat, &spr_write_ibatl, |
552 |
0x00000000);
|
553 |
spr_register(env, SPR_DBAT0U, "DBAT0U",
|
554 |
SPR_NOACCESS, SPR_NOACCESS, |
555 |
&spr_read_dbat, &spr_write_dbatu, |
556 |
0x00000000);
|
557 |
spr_register(env, SPR_DBAT0L, "DBAT0L",
|
558 |
SPR_NOACCESS, SPR_NOACCESS, |
559 |
&spr_read_dbat, &spr_write_dbatl, |
560 |
0x00000000);
|
561 |
spr_register(env, SPR_DBAT1U, "DBAT1U",
|
562 |
SPR_NOACCESS, SPR_NOACCESS, |
563 |
&spr_read_dbat, &spr_write_dbatu, |
564 |
0x00000000);
|
565 |
spr_register(env, SPR_DBAT1L, "DBAT1L",
|
566 |
SPR_NOACCESS, SPR_NOACCESS, |
567 |
&spr_read_dbat, &spr_write_dbatl, |
568 |
0x00000000);
|
569 |
spr_register(env, SPR_DBAT2U, "DBAT2U",
|
570 |
SPR_NOACCESS, SPR_NOACCESS, |
571 |
&spr_read_dbat, &spr_write_dbatu, |
572 |
0x00000000);
|
573 |
spr_register(env, SPR_DBAT2L, "DBAT2L",
|
574 |
SPR_NOACCESS, SPR_NOACCESS, |
575 |
&spr_read_dbat, &spr_write_dbatl, |
576 |
0x00000000);
|
577 |
spr_register(env, SPR_DBAT3U, "DBAT3U",
|
578 |
SPR_NOACCESS, SPR_NOACCESS, |
579 |
&spr_read_dbat, &spr_write_dbatu, |
580 |
0x00000000);
|
581 |
spr_register(env, SPR_DBAT3L, "DBAT3L",
|
582 |
SPR_NOACCESS, SPR_NOACCESS, |
583 |
&spr_read_dbat, &spr_write_dbatl, |
584 |
0x00000000);
|
585 |
env->nb_BATs = 4;
|
586 |
} |
587 |
|
588 |
/* BATs 4-7 */
|
589 |
static void gen_high_BATs (CPUPPCState *env) |
590 |
{ |
591 |
spr_register(env, SPR_IBAT4U, "IBAT4U",
|
592 |
SPR_NOACCESS, SPR_NOACCESS, |
593 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
594 |
0x00000000);
|
595 |
spr_register(env, SPR_IBAT4L, "IBAT4L",
|
596 |
SPR_NOACCESS, SPR_NOACCESS, |
597 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
598 |
0x00000000);
|
599 |
spr_register(env, SPR_IBAT5U, "IBAT5U",
|
600 |
SPR_NOACCESS, SPR_NOACCESS, |
601 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
602 |
0x00000000);
|
603 |
spr_register(env, SPR_IBAT5L, "IBAT5L",
|
604 |
SPR_NOACCESS, SPR_NOACCESS, |
605 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
606 |
0x00000000);
|
607 |
spr_register(env, SPR_IBAT6U, "IBAT6U",
|
608 |
SPR_NOACCESS, SPR_NOACCESS, |
609 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
610 |
0x00000000);
|
611 |
spr_register(env, SPR_IBAT6L, "IBAT6L",
|
612 |
SPR_NOACCESS, SPR_NOACCESS, |
613 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
614 |
0x00000000);
|
615 |
spr_register(env, SPR_IBAT7U, "IBAT7U",
|
616 |
SPR_NOACCESS, SPR_NOACCESS, |
617 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
618 |
0x00000000);
|
619 |
spr_register(env, SPR_IBAT7L, "IBAT7L",
|
620 |
SPR_NOACCESS, SPR_NOACCESS, |
621 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
622 |
0x00000000);
|
623 |
spr_register(env, SPR_DBAT4U, "DBAT4U",
|
624 |
SPR_NOACCESS, SPR_NOACCESS, |
625 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
626 |
0x00000000);
|
627 |
spr_register(env, SPR_DBAT4L, "DBAT4L",
|
628 |
SPR_NOACCESS, SPR_NOACCESS, |
629 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
630 |
0x00000000);
|
631 |
spr_register(env, SPR_DBAT5U, "DBAT5U",
|
632 |
SPR_NOACCESS, SPR_NOACCESS, |
633 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
634 |
0x00000000);
|
635 |
spr_register(env, SPR_DBAT5L, "DBAT5L",
|
636 |
SPR_NOACCESS, SPR_NOACCESS, |
637 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
638 |
0x00000000);
|
639 |
spr_register(env, SPR_DBAT6U, "DBAT6U",
|
640 |
SPR_NOACCESS, SPR_NOACCESS, |
641 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
642 |
0x00000000);
|
643 |
spr_register(env, SPR_DBAT6L, "DBAT6L",
|
644 |
SPR_NOACCESS, SPR_NOACCESS, |
645 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
646 |
0x00000000);
|
647 |
spr_register(env, SPR_DBAT7U, "DBAT7U",
|
648 |
SPR_NOACCESS, SPR_NOACCESS, |
649 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
650 |
0x00000000);
|
651 |
spr_register(env, SPR_DBAT7L, "DBAT7L",
|
652 |
SPR_NOACCESS, SPR_NOACCESS, |
653 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
654 |
0x00000000);
|
655 |
env->nb_BATs = 8;
|
656 |
} |
657 |
|
658 |
/* Generic PowerPC time base */
|
659 |
static void gen_tbl (CPUPPCState *env) |
660 |
{ |
661 |
spr_register(env, SPR_VTBL, "TBL",
|
662 |
&spr_read_tbl, SPR_NOACCESS, |
663 |
&spr_read_tbl, SPR_NOACCESS, |
664 |
0x00000000);
|
665 |
spr_register(env, SPR_TBL, "TBL",
|
666 |
SPR_NOACCESS, SPR_NOACCESS, |
667 |
SPR_NOACCESS, &spr_write_tbl, |
668 |
0x00000000);
|
669 |
spr_register(env, SPR_VTBU, "TBU",
|
670 |
&spr_read_tbu, SPR_NOACCESS, |
671 |
&spr_read_tbu, SPR_NOACCESS, |
672 |
0x00000000);
|
673 |
spr_register(env, SPR_TBU, "TBU",
|
674 |
SPR_NOACCESS, SPR_NOACCESS, |
675 |
SPR_NOACCESS, &spr_write_tbu, |
676 |
0x00000000);
|
677 |
} |
678 |
|
679 |
/* Softare table search registers */
|
680 |
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
681 |
{ |
682 |
env->nb_tlb = nb_tlbs; |
683 |
env->nb_ways = nb_ways; |
684 |
env->id_tlbs = 1;
|
685 |
spr_register(env, SPR_DMISS, "DMISS",
|
686 |
SPR_NOACCESS, SPR_NOACCESS, |
687 |
&spr_read_generic, SPR_NOACCESS, |
688 |
0x00000000);
|
689 |
spr_register(env, SPR_DCMP, "DCMP",
|
690 |
SPR_NOACCESS, SPR_NOACCESS, |
691 |
&spr_read_generic, SPR_NOACCESS, |
692 |
0x00000000);
|
693 |
spr_register(env, SPR_HASH1, "HASH1",
|
694 |
SPR_NOACCESS, SPR_NOACCESS, |
695 |
&spr_read_generic, SPR_NOACCESS, |
696 |
0x00000000);
|
697 |
spr_register(env, SPR_HASH2, "HASH2",
|
698 |
SPR_NOACCESS, SPR_NOACCESS, |
699 |
&spr_read_generic, SPR_NOACCESS, |
700 |
0x00000000);
|
701 |
spr_register(env, SPR_IMISS, "IMISS",
|
702 |
SPR_NOACCESS, SPR_NOACCESS, |
703 |
&spr_read_generic, SPR_NOACCESS, |
704 |
0x00000000);
|
705 |
spr_register(env, SPR_ICMP, "ICMP",
|
706 |
SPR_NOACCESS, SPR_NOACCESS, |
707 |
&spr_read_generic, SPR_NOACCESS, |
708 |
0x00000000);
|
709 |
spr_register(env, SPR_RPA, "RPA",
|
710 |
SPR_NOACCESS, SPR_NOACCESS, |
711 |
&spr_read_generic, &spr_write_generic, |
712 |
0x00000000);
|
713 |
} |
714 |
|
715 |
/* SPR common to MPC755 and G2 */
|
716 |
static void gen_spr_G2_755 (CPUPPCState *env) |
717 |
{ |
718 |
/* SGPRs */
|
719 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
720 |
SPR_NOACCESS, SPR_NOACCESS, |
721 |
&spr_read_generic, &spr_write_generic, |
722 |
0x00000000);
|
723 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
724 |
SPR_NOACCESS, SPR_NOACCESS, |
725 |
&spr_read_generic, &spr_write_generic, |
726 |
0x00000000);
|
727 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
728 |
SPR_NOACCESS, SPR_NOACCESS, |
729 |
&spr_read_generic, &spr_write_generic, |
730 |
0x00000000);
|
731 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
732 |
SPR_NOACCESS, SPR_NOACCESS, |
733 |
&spr_read_generic, &spr_write_generic, |
734 |
0x00000000);
|
735 |
/* External access control */
|
736 |
/* XXX : not implemented */
|
737 |
spr_register(env, SPR_EAR, "EAR",
|
738 |
SPR_NOACCESS, SPR_NOACCESS, |
739 |
&spr_read_generic, &spr_write_generic, |
740 |
0x00000000);
|
741 |
} |
742 |
|
743 |
/* SPR common to all 7xx PowerPC implementations */
|
744 |
static void gen_spr_7xx (CPUPPCState *env) |
745 |
{ |
746 |
/* Breakpoints */
|
747 |
/* XXX : not implemented */
|
748 |
spr_register(env, SPR_DABR, "DABR",
|
749 |
SPR_NOACCESS, SPR_NOACCESS, |
750 |
&spr_read_generic, &spr_write_generic, |
751 |
0x00000000);
|
752 |
/* XXX : not implemented */
|
753 |
spr_register(env, SPR_IABR, "IABR",
|
754 |
SPR_NOACCESS, SPR_NOACCESS, |
755 |
&spr_read_generic, &spr_write_generic, |
756 |
0x00000000);
|
757 |
/* Cache management */
|
758 |
/* XXX : not implemented */
|
759 |
spr_register(env, SPR_ICTC, "ICTC",
|
760 |
SPR_NOACCESS, SPR_NOACCESS, |
761 |
&spr_read_generic, &spr_write_generic, |
762 |
0x00000000);
|
763 |
/* XXX : not implemented */
|
764 |
spr_register(env, SPR_L2CR, "L2CR",
|
765 |
SPR_NOACCESS, SPR_NOACCESS, |
766 |
&spr_read_generic, &spr_write_generic, |
767 |
0x00000000);
|
768 |
/* Performance monitors */
|
769 |
/* XXX : not implemented */
|
770 |
spr_register(env, SPR_MMCR0, "MMCR0",
|
771 |
SPR_NOACCESS, SPR_NOACCESS, |
772 |
&spr_read_generic, &spr_write_generic, |
773 |
0x00000000);
|
774 |
/* XXX : not implemented */
|
775 |
spr_register(env, SPR_MMCR1, "MMCR1",
|
776 |
SPR_NOACCESS, SPR_NOACCESS, |
777 |
&spr_read_generic, &spr_write_generic, |
778 |
0x00000000);
|
779 |
/* XXX : not implemented */
|
780 |
spr_register(env, SPR_PMC1, "PMC1",
|
781 |
SPR_NOACCESS, SPR_NOACCESS, |
782 |
&spr_read_generic, &spr_write_generic, |
783 |
0x00000000);
|
784 |
/* XXX : not implemented */
|
785 |
spr_register(env, SPR_PMC2, "PMC2",
|
786 |
SPR_NOACCESS, SPR_NOACCESS, |
787 |
&spr_read_generic, &spr_write_generic, |
788 |
0x00000000);
|
789 |
/* XXX : not implemented */
|
790 |
spr_register(env, SPR_PMC3, "PMC3",
|
791 |
SPR_NOACCESS, SPR_NOACCESS, |
792 |
&spr_read_generic, &spr_write_generic, |
793 |
0x00000000);
|
794 |
/* XXX : not implemented */
|
795 |
spr_register(env, SPR_PMC4, "PMC4",
|
796 |
SPR_NOACCESS, SPR_NOACCESS, |
797 |
&spr_read_generic, &spr_write_generic, |
798 |
0x00000000);
|
799 |
/* XXX : not implemented */
|
800 |
spr_register(env, SPR_SIA, "SIA",
|
801 |
SPR_NOACCESS, SPR_NOACCESS, |
802 |
&spr_read_generic, SPR_NOACCESS, |
803 |
0x00000000);
|
804 |
spr_register(env, SPR_UMMCR0, "UMMCR0",
|
805 |
&spr_read_ureg, SPR_NOACCESS, |
806 |
&spr_read_ureg, SPR_NOACCESS, |
807 |
0x00000000);
|
808 |
spr_register(env, SPR_UMMCR1, "UMMCR1",
|
809 |
&spr_read_ureg, SPR_NOACCESS, |
810 |
&spr_read_ureg, SPR_NOACCESS, |
811 |
0x00000000);
|
812 |
spr_register(env, SPR_UPMC1, "UPMC1",
|
813 |
&spr_read_ureg, SPR_NOACCESS, |
814 |
&spr_read_ureg, SPR_NOACCESS, |
815 |
0x00000000);
|
816 |
spr_register(env, SPR_UPMC2, "UPMC2",
|
817 |
&spr_read_ureg, SPR_NOACCESS, |
818 |
&spr_read_ureg, SPR_NOACCESS, |
819 |
0x00000000);
|
820 |
spr_register(env, SPR_UPMC3, "UPMC3",
|
821 |
&spr_read_ureg, SPR_NOACCESS, |
822 |
&spr_read_ureg, SPR_NOACCESS, |
823 |
0x00000000);
|
824 |
spr_register(env, SPR_UPMC4, "UPMC4",
|
825 |
&spr_read_ureg, SPR_NOACCESS, |
826 |
&spr_read_ureg, SPR_NOACCESS, |
827 |
0x00000000);
|
828 |
spr_register(env, SPR_USIA, "USIA",
|
829 |
&spr_read_ureg, SPR_NOACCESS, |
830 |
&spr_read_ureg, SPR_NOACCESS, |
831 |
0x00000000);
|
832 |
/* Thermal management */
|
833 |
/* XXX : not implemented */
|
834 |
spr_register(env, SPR_THRM1, "THRM1",
|
835 |
SPR_NOACCESS, SPR_NOACCESS, |
836 |
&spr_read_generic, &spr_write_generic, |
837 |
0x00000000);
|
838 |
/* XXX : not implemented */
|
839 |
spr_register(env, SPR_THRM2, "THRM2",
|
840 |
SPR_NOACCESS, SPR_NOACCESS, |
841 |
&spr_read_generic, &spr_write_generic, |
842 |
0x00000000);
|
843 |
/* XXX : not implemented */
|
844 |
spr_register(env, SPR_THRM3, "THRM3",
|
845 |
SPR_NOACCESS, SPR_NOACCESS, |
846 |
&spr_read_generic, &spr_write_generic, |
847 |
0x00000000);
|
848 |
/* External access control */
|
849 |
/* XXX : not implemented */
|
850 |
spr_register(env, SPR_EAR, "EAR",
|
851 |
SPR_NOACCESS, SPR_NOACCESS, |
852 |
&spr_read_generic, &spr_write_generic, |
853 |
0x00000000);
|
854 |
} |
855 |
|
856 |
/* SPR specific to PowerPC 604 implementation */
|
857 |
static void gen_spr_604 (CPUPPCState *env) |
858 |
{ |
859 |
/* Processor identification */
|
860 |
spr_register(env, SPR_PIR, "PIR",
|
861 |
SPR_NOACCESS, SPR_NOACCESS, |
862 |
&spr_read_generic, &spr_write_pir, |
863 |
0x00000000);
|
864 |
/* Breakpoints */
|
865 |
/* XXX : not implemented */
|
866 |
spr_register(env, SPR_IABR, "IABR",
|
867 |
SPR_NOACCESS, SPR_NOACCESS, |
868 |
&spr_read_generic, &spr_write_generic, |
869 |
0x00000000);
|
870 |
/* XXX : not implemented */
|
871 |
spr_register(env, SPR_DABR, "DABR",
|
872 |
SPR_NOACCESS, SPR_NOACCESS, |
873 |
&spr_read_generic, &spr_write_generic, |
874 |
0x00000000);
|
875 |
/* Performance counters */
|
876 |
/* XXX : not implemented */
|
877 |
spr_register(env, SPR_MMCR0, "MMCR0",
|
878 |
SPR_NOACCESS, SPR_NOACCESS, |
879 |
&spr_read_generic, &spr_write_generic, |
880 |
0x00000000);
|
881 |
/* XXX : not implemented */
|
882 |
spr_register(env, SPR_MMCR1, "MMCR1",
|
883 |
SPR_NOACCESS, SPR_NOACCESS, |
884 |
&spr_read_generic, &spr_write_generic, |
885 |
0x00000000);
|
886 |
/* XXX : not implemented */
|
887 |
spr_register(env, SPR_PMC1, "PMC1",
|
888 |
SPR_NOACCESS, SPR_NOACCESS, |
889 |
&spr_read_generic, &spr_write_generic, |
890 |
0x00000000);
|
891 |
/* XXX : not implemented */
|
892 |
spr_register(env, SPR_PMC2, "PMC2",
|
893 |
SPR_NOACCESS, SPR_NOACCESS, |
894 |
&spr_read_generic, &spr_write_generic, |
895 |
0x00000000);
|
896 |
/* XXX : not implemented */
|
897 |
spr_register(env, SPR_PMC3, "PMC3",
|
898 |
SPR_NOACCESS, SPR_NOACCESS, |
899 |
&spr_read_generic, &spr_write_generic, |
900 |
0x00000000);
|
901 |
/* XXX : not implemented */
|
902 |
spr_register(env, SPR_PMC4, "PMC4",
|
903 |
SPR_NOACCESS, SPR_NOACCESS, |
904 |
&spr_read_generic, &spr_write_generic, |
905 |
0x00000000);
|
906 |
/* XXX : not implemented */
|
907 |
spr_register(env, SPR_SIA, "SIA",
|
908 |
SPR_NOACCESS, SPR_NOACCESS, |
909 |
&spr_read_generic, SPR_NOACCESS, |
910 |
0x00000000);
|
911 |
/* XXX : not implemented */
|
912 |
spr_register(env, SPR_SDA, "SDA",
|
913 |
SPR_NOACCESS, SPR_NOACCESS, |
914 |
&spr_read_generic, SPR_NOACCESS, |
915 |
0x00000000);
|
916 |
/* External access control */
|
917 |
/* XXX : not implemented */
|
918 |
spr_register(env, SPR_EAR, "EAR",
|
919 |
SPR_NOACCESS, SPR_NOACCESS, |
920 |
&spr_read_generic, &spr_write_generic, |
921 |
0x00000000);
|
922 |
} |
923 |
|
924 |
/* SPR specific to PowerPC 603 implementation */
|
925 |
static void gen_spr_603 (CPUPPCState *env) |
926 |
{ |
927 |
/* External access control */
|
928 |
/* XXX : not implemented */
|
929 |
spr_register(env, SPR_EAR, "EAR",
|
930 |
SPR_NOACCESS, SPR_NOACCESS, |
931 |
&spr_read_generic, &spr_write_generic, |
932 |
0x00000000);
|
933 |
} |
934 |
|
935 |
/* SPR specific to PowerPC G2 implementation */
|
936 |
static void gen_spr_G2 (CPUPPCState *env) |
937 |
{ |
938 |
/* Memory base address */
|
939 |
/* MBAR */
|
940 |
spr_register(env, SPR_MBAR, "MBAR",
|
941 |
SPR_NOACCESS, SPR_NOACCESS, |
942 |
&spr_read_generic, &spr_write_generic, |
943 |
0x00000000);
|
944 |
/* System version register */
|
945 |
/* SVR */
|
946 |
spr_register(env, SPR_SVR, "SVR",
|
947 |
SPR_NOACCESS, SPR_NOACCESS, |
948 |
&spr_read_generic, SPR_NOACCESS, |
949 |
0x00000000);
|
950 |
/* Exception processing */
|
951 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
952 |
SPR_NOACCESS, SPR_NOACCESS, |
953 |
&spr_read_generic, &spr_write_generic, |
954 |
0x00000000);
|
955 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
956 |
SPR_NOACCESS, SPR_NOACCESS, |
957 |
&spr_read_generic, &spr_write_generic, |
958 |
0x00000000);
|
959 |
/* Breakpoints */
|
960 |
/* XXX : not implemented */
|
961 |
spr_register(env, SPR_DABR, "DABR",
|
962 |
SPR_NOACCESS, SPR_NOACCESS, |
963 |
&spr_read_generic, &spr_write_generic, |
964 |
0x00000000);
|
965 |
/* XXX : not implemented */
|
966 |
spr_register(env, SPR_DABR2, "DABR2",
|
967 |
SPR_NOACCESS, SPR_NOACCESS, |
968 |
&spr_read_generic, &spr_write_generic, |
969 |
0x00000000);
|
970 |
/* XXX : not implemented */
|
971 |
spr_register(env, SPR_IABR, "IABR",
|
972 |
SPR_NOACCESS, SPR_NOACCESS, |
973 |
&spr_read_generic, &spr_write_generic, |
974 |
0x00000000);
|
975 |
/* XXX : not implemented */
|
976 |
spr_register(env, SPR_IABR2, "IABR2",
|
977 |
SPR_NOACCESS, SPR_NOACCESS, |
978 |
&spr_read_generic, &spr_write_generic, |
979 |
0x00000000);
|
980 |
/* XXX : not implemented */
|
981 |
spr_register(env, SPR_IBCR, "IBCR",
|
982 |
SPR_NOACCESS, SPR_NOACCESS, |
983 |
&spr_read_generic, &spr_write_generic, |
984 |
0x00000000);
|
985 |
/* XXX : not implemented */
|
986 |
spr_register(env, SPR_DBCR, "DBCR",
|
987 |
SPR_NOACCESS, SPR_NOACCESS, |
988 |
&spr_read_generic, &spr_write_generic, |
989 |
0x00000000);
|
990 |
} |
991 |
|
992 |
/* SPR specific to PowerPC 602 implementation */
|
993 |
static void gen_spr_602 (CPUPPCState *env) |
994 |
{ |
995 |
/* ESA registers */
|
996 |
/* XXX : not implemented */
|
997 |
spr_register(env, SPR_SER, "SER",
|
998 |
SPR_NOACCESS, SPR_NOACCESS, |
999 |
&spr_read_generic, &spr_write_generic, |
1000 |
0x00000000);
|
1001 |
/* XXX : not implemented */
|
1002 |
spr_register(env, SPR_SEBR, "SEBR",
|
1003 |
SPR_NOACCESS, SPR_NOACCESS, |
1004 |
&spr_read_generic, &spr_write_generic, |
1005 |
0x00000000);
|
1006 |
/* XXX : not implemented */
|
1007 |
spr_register(env, SPR_ESASR, "ESASR",
|
1008 |
SPR_NOACCESS, SPR_NOACCESS, |
1009 |
&spr_read_generic, &spr_write_generic, |
1010 |
0x00000000);
|
1011 |
/* Floating point status */
|
1012 |
/* XXX : not implemented */
|
1013 |
spr_register(env, SPR_SP, "SP",
|
1014 |
SPR_NOACCESS, SPR_NOACCESS, |
1015 |
&spr_read_generic, &spr_write_generic, |
1016 |
0x00000000);
|
1017 |
/* XXX : not implemented */
|
1018 |
spr_register(env, SPR_LT, "LT",
|
1019 |
SPR_NOACCESS, SPR_NOACCESS, |
1020 |
&spr_read_generic, &spr_write_generic, |
1021 |
0x00000000);
|
1022 |
/* Watchdog timer */
|
1023 |
/* XXX : not implemented */
|
1024 |
spr_register(env, SPR_TCR, "TCR",
|
1025 |
SPR_NOACCESS, SPR_NOACCESS, |
1026 |
&spr_read_generic, &spr_write_generic, |
1027 |
0x00000000);
|
1028 |
/* Interrupt base */
|
1029 |
spr_register(env, SPR_IBR, "IBR",
|
1030 |
SPR_NOACCESS, SPR_NOACCESS, |
1031 |
&spr_read_generic, &spr_write_generic, |
1032 |
0x00000000);
|
1033 |
} |
1034 |
|
1035 |
/* SPR specific to PowerPC 601 implementation */
|
1036 |
static void gen_spr_601 (CPUPPCState *env) |
1037 |
{ |
1038 |
/* Multiplication/division register */
|
1039 |
/* MQ */
|
1040 |
spr_register(env, SPR_MQ, "MQ",
|
1041 |
&spr_read_generic, &spr_write_generic, |
1042 |
&spr_read_generic, &spr_write_generic, |
1043 |
0x00000000);
|
1044 |
/* RTC registers */
|
1045 |
spr_register(env, SPR_601_RTCU, "RTCU",
|
1046 |
SPR_NOACCESS, SPR_NOACCESS, |
1047 |
SPR_NOACCESS, &spr_write_601_rtcu, |
1048 |
0x00000000);
|
1049 |
spr_register(env, SPR_601_VRTCU, "RTCU",
|
1050 |
&spr_read_601_rtcu, SPR_NOACCESS, |
1051 |
&spr_read_601_rtcu, SPR_NOACCESS, |
1052 |
0x00000000);
|
1053 |
spr_register(env, SPR_601_RTCL, "RTCL",
|
1054 |
SPR_NOACCESS, SPR_NOACCESS, |
1055 |
SPR_NOACCESS, &spr_write_601_rtcl, |
1056 |
0x00000000);
|
1057 |
spr_register(env, SPR_601_VRTCL, "RTCL",
|
1058 |
&spr_read_601_rtcl, SPR_NOACCESS, |
1059 |
&spr_read_601_rtcl, SPR_NOACCESS, |
1060 |
0x00000000);
|
1061 |
/* Timer */
|
1062 |
#if 0 /* ? */
|
1063 |
spr_register(env, SPR_601_UDECR, "UDECR",
|
1064 |
&spr_read_decr, SPR_NOACCESS,
|
1065 |
&spr_read_decr, SPR_NOACCESS,
|
1066 |
0x00000000);
|
1067 |
#endif
|
1068 |
/* External access control */
|
1069 |
/* XXX : not implemented */
|
1070 |
spr_register(env, SPR_EAR, "EAR",
|
1071 |
SPR_NOACCESS, SPR_NOACCESS, |
1072 |
&spr_read_generic, &spr_write_generic, |
1073 |
0x00000000);
|
1074 |
/* Memory management */
|
1075 |
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
1076 |
SPR_NOACCESS, SPR_NOACCESS, |
1077 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1078 |
0x00000000);
|
1079 |
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
1080 |
SPR_NOACCESS, SPR_NOACCESS, |
1081 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1082 |
0x00000000);
|
1083 |
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
1084 |
SPR_NOACCESS, SPR_NOACCESS, |
1085 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1086 |
0x00000000);
|
1087 |
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
1088 |
SPR_NOACCESS, SPR_NOACCESS, |
1089 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1090 |
0x00000000);
|
1091 |
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
1092 |
SPR_NOACCESS, SPR_NOACCESS, |
1093 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1094 |
0x00000000);
|
1095 |
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
1096 |
SPR_NOACCESS, SPR_NOACCESS, |
1097 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1098 |
0x00000000);
|
1099 |
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
1100 |
SPR_NOACCESS, SPR_NOACCESS, |
1101 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1102 |
0x00000000);
|
1103 |
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
1104 |
SPR_NOACCESS, SPR_NOACCESS, |
1105 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1106 |
0x00000000);
|
1107 |
} |
1108 |
|
1109 |
/* PowerPC BookE SPR */
|
1110 |
static void gen_spr_BookE (CPUPPCState *env) |
1111 |
{ |
1112 |
/* Processor identification */
|
1113 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
1114 |
SPR_NOACCESS, SPR_NOACCESS, |
1115 |
&spr_read_generic, &spr_write_pir, |
1116 |
0x00000000);
|
1117 |
/* Interrupt processing */
|
1118 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
1119 |
SPR_NOACCESS, SPR_NOACCESS, |
1120 |
&spr_read_generic, &spr_write_generic, |
1121 |
0x00000000);
|
1122 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
1123 |
SPR_NOACCESS, SPR_NOACCESS, |
1124 |
&spr_read_generic, &spr_write_generic, |
1125 |
0x00000000);
|
1126 |
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
|
1127 |
SPR_NOACCESS, SPR_NOACCESS, |
1128 |
&spr_read_generic, &spr_write_generic, |
1129 |
0x00000000);
|
1130 |
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
|
1131 |
SPR_NOACCESS, SPR_NOACCESS, |
1132 |
&spr_read_generic, &spr_write_generic, |
1133 |
0x00000000);
|
1134 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
1135 |
SPR_NOACCESS, SPR_NOACCESS, |
1136 |
&spr_read_generic, &spr_write_generic, |
1137 |
0x00000000);
|
1138 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
1139 |
SPR_NOACCESS, SPR_NOACCESS, |
1140 |
&spr_read_generic, &spr_write_generic, |
1141 |
0x00000000);
|
1142 |
/* Debug */
|
1143 |
/* XXX : not implemented */
|
1144 |
spr_register(env, SPR_BOOKE_IAC1, "IAC1",
|
1145 |
SPR_NOACCESS, SPR_NOACCESS, |
1146 |
&spr_read_generic, &spr_write_generic, |
1147 |
0x00000000);
|
1148 |
/* XXX : not implemented */
|
1149 |
spr_register(env, SPR_BOOKE_IAC2, "IAC2",
|
1150 |
SPR_NOACCESS, SPR_NOACCESS, |
1151 |
&spr_read_generic, &spr_write_generic, |
1152 |
0x00000000);
|
1153 |
/* XXX : not implemented */
|
1154 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
1155 |
SPR_NOACCESS, SPR_NOACCESS, |
1156 |
&spr_read_generic, &spr_write_generic, |
1157 |
0x00000000);
|
1158 |
/* XXX : not implemented */
|
1159 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
1160 |
SPR_NOACCESS, SPR_NOACCESS, |
1161 |
&spr_read_generic, &spr_write_generic, |
1162 |
0x00000000);
|
1163 |
/* XXX : not implemented */
|
1164 |
spr_register(env, SPR_BOOKE_DAC1, "DAC1",
|
1165 |
SPR_NOACCESS, SPR_NOACCESS, |
1166 |
&spr_read_generic, &spr_write_generic, |
1167 |
0x00000000);
|
1168 |
/* XXX : not implemented */
|
1169 |
spr_register(env, SPR_BOOKE_DAC2, "DAC2",
|
1170 |
SPR_NOACCESS, SPR_NOACCESS, |
1171 |
&spr_read_generic, &spr_write_generic, |
1172 |
0x00000000);
|
1173 |
/* XXX : not implemented */
|
1174 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
1175 |
SPR_NOACCESS, SPR_NOACCESS, |
1176 |
&spr_read_generic, &spr_write_generic, |
1177 |
0x00000000);
|
1178 |
/* XXX : not implemented */
|
1179 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
1180 |
SPR_NOACCESS, SPR_NOACCESS, |
1181 |
&spr_read_generic, &spr_write_generic, |
1182 |
0x00000000);
|
1183 |
/* XXX : not implemented */
|
1184 |
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
|
1185 |
SPR_NOACCESS, SPR_NOACCESS, |
1186 |
&spr_read_generic, &spr_write_generic, |
1187 |
0x00000000);
|
1188 |
/* XXX : not implemented */
|
1189 |
spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
|
1190 |
SPR_NOACCESS, SPR_NOACCESS, |
1191 |
&spr_read_generic, &spr_write_generic, |
1192 |
0x00000000);
|
1193 |
/* XXX : not implemented */
|
1194 |
spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
|
1195 |
SPR_NOACCESS, SPR_NOACCESS, |
1196 |
&spr_read_generic, &spr_write_generic, |
1197 |
0x00000000);
|
1198 |
/* XXX : not implemented */
|
1199 |
spr_register(env, SPR_BOOKE_DBSR, "DBSR",
|
1200 |
SPR_NOACCESS, SPR_NOACCESS, |
1201 |
&spr_read_generic, &spr_write_clear, |
1202 |
0x00000000);
|
1203 |
spr_register(env, SPR_BOOKE_DEAR, "DEAR",
|
1204 |
SPR_NOACCESS, SPR_NOACCESS, |
1205 |
&spr_read_generic, &spr_write_generic, |
1206 |
0x00000000);
|
1207 |
spr_register(env, SPR_BOOKE_ESR, "ESR",
|
1208 |
SPR_NOACCESS, SPR_NOACCESS, |
1209 |
&spr_read_generic, &spr_write_generic, |
1210 |
0x00000000);
|
1211 |
spr_register(env, SPR_BOOKE_IVPR, "IVPR",
|
1212 |
SPR_NOACCESS, SPR_NOACCESS, |
1213 |
&spr_read_generic, &spr_write_generic, |
1214 |
0x00000000);
|
1215 |
/* Exception vectors */
|
1216 |
spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
|
1217 |
SPR_NOACCESS, SPR_NOACCESS, |
1218 |
&spr_read_generic, &spr_write_generic, |
1219 |
0x00000000);
|
1220 |
spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
|
1221 |
SPR_NOACCESS, SPR_NOACCESS, |
1222 |
&spr_read_generic, &spr_write_generic, |
1223 |
0x00000000);
|
1224 |
spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
|
1225 |
SPR_NOACCESS, SPR_NOACCESS, |
1226 |
&spr_read_generic, &spr_write_generic, |
1227 |
0x00000000);
|
1228 |
spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
|
1229 |
SPR_NOACCESS, SPR_NOACCESS, |
1230 |
&spr_read_generic, &spr_write_generic, |
1231 |
0x00000000);
|
1232 |
spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
|
1233 |
SPR_NOACCESS, SPR_NOACCESS, |
1234 |
&spr_read_generic, &spr_write_generic, |
1235 |
0x00000000);
|
1236 |
spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
|
1237 |
SPR_NOACCESS, SPR_NOACCESS, |
1238 |
&spr_read_generic, &spr_write_generic, |
1239 |
0x00000000);
|
1240 |
spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
|
1241 |
SPR_NOACCESS, SPR_NOACCESS, |
1242 |
&spr_read_generic, &spr_write_generic, |
1243 |
0x00000000);
|
1244 |
spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
|
1245 |
SPR_NOACCESS, SPR_NOACCESS, |
1246 |
&spr_read_generic, &spr_write_generic, |
1247 |
0x00000000);
|
1248 |
spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
|
1249 |
SPR_NOACCESS, SPR_NOACCESS, |
1250 |
&spr_read_generic, &spr_write_generic, |
1251 |
0x00000000);
|
1252 |
spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
|
1253 |
SPR_NOACCESS, SPR_NOACCESS, |
1254 |
&spr_read_generic, &spr_write_generic, |
1255 |
0x00000000);
|
1256 |
spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
|
1257 |
SPR_NOACCESS, SPR_NOACCESS, |
1258 |
&spr_read_generic, &spr_write_generic, |
1259 |
0x00000000);
|
1260 |
spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
|
1261 |
SPR_NOACCESS, SPR_NOACCESS, |
1262 |
&spr_read_generic, &spr_write_generic, |
1263 |
0x00000000);
|
1264 |
spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
|
1265 |
SPR_NOACCESS, SPR_NOACCESS, |
1266 |
&spr_read_generic, &spr_write_generic, |
1267 |
0x00000000);
|
1268 |
spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
|
1269 |
SPR_NOACCESS, SPR_NOACCESS, |
1270 |
&spr_read_generic, &spr_write_generic, |
1271 |
0x00000000);
|
1272 |
spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
|
1273 |
SPR_NOACCESS, SPR_NOACCESS, |
1274 |
&spr_read_generic, &spr_write_generic, |
1275 |
0x00000000);
|
1276 |
spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
|
1277 |
SPR_NOACCESS, SPR_NOACCESS, |
1278 |
&spr_read_generic, &spr_write_generic, |
1279 |
0x00000000);
|
1280 |
spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
|
1281 |
SPR_NOACCESS, SPR_NOACCESS, |
1282 |
&spr_read_generic, &spr_write_generic, |
1283 |
0x00000000);
|
1284 |
spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
|
1285 |
SPR_NOACCESS, SPR_NOACCESS, |
1286 |
&spr_read_generic, &spr_write_generic, |
1287 |
0x00000000);
|
1288 |
spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
|
1289 |
SPR_NOACCESS, SPR_NOACCESS, |
1290 |
&spr_read_generic, &spr_write_generic, |
1291 |
0x00000000);
|
1292 |
spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
|
1293 |
SPR_NOACCESS, SPR_NOACCESS, |
1294 |
&spr_read_generic, &spr_write_generic, |
1295 |
0x00000000);
|
1296 |
spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
|
1297 |
SPR_NOACCESS, SPR_NOACCESS, |
1298 |
&spr_read_generic, &spr_write_generic, |
1299 |
0x00000000);
|
1300 |
spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
|
1301 |
SPR_NOACCESS, SPR_NOACCESS, |
1302 |
&spr_read_generic, &spr_write_generic, |
1303 |
0x00000000);
|
1304 |
spr_register(env, SPR_BOOKE_PID, "PID",
|
1305 |
SPR_NOACCESS, SPR_NOACCESS, |
1306 |
&spr_read_generic, &spr_write_generic, |
1307 |
0x00000000);
|
1308 |
spr_register(env, SPR_BOOKE_TCR, "TCR",
|
1309 |
SPR_NOACCESS, SPR_NOACCESS, |
1310 |
&spr_read_generic, &spr_write_booke_tcr, |
1311 |
0x00000000);
|
1312 |
spr_register(env, SPR_BOOKE_TSR, "TSR",
|
1313 |
SPR_NOACCESS, SPR_NOACCESS, |
1314 |
&spr_read_generic, &spr_write_booke_tsr, |
1315 |
0x00000000);
|
1316 |
/* Timer */
|
1317 |
spr_register(env, SPR_DECR, "DECR",
|
1318 |
SPR_NOACCESS, SPR_NOACCESS, |
1319 |
&spr_read_decr, &spr_write_decr, |
1320 |
0x00000000);
|
1321 |
spr_register(env, SPR_BOOKE_DECAR, "DECAR",
|
1322 |
SPR_NOACCESS, SPR_NOACCESS, |
1323 |
SPR_NOACCESS, &spr_write_generic, |
1324 |
0x00000000);
|
1325 |
/* SPRGs */
|
1326 |
spr_register(env, SPR_USPRG0, "USPRG0",
|
1327 |
&spr_read_generic, &spr_write_generic, |
1328 |
&spr_read_generic, &spr_write_generic, |
1329 |
0x00000000);
|
1330 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
1331 |
SPR_NOACCESS, SPR_NOACCESS, |
1332 |
&spr_read_generic, &spr_write_generic, |
1333 |
0x00000000);
|
1334 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
1335 |
&spr_read_ureg, SPR_NOACCESS, |
1336 |
&spr_read_ureg, SPR_NOACCESS, |
1337 |
0x00000000);
|
1338 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
1339 |
SPR_NOACCESS, SPR_NOACCESS, |
1340 |
&spr_read_generic, &spr_write_generic, |
1341 |
0x00000000);
|
1342 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
1343 |
&spr_read_ureg, SPR_NOACCESS, |
1344 |
&spr_read_ureg, SPR_NOACCESS, |
1345 |
0x00000000);
|
1346 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
1347 |
SPR_NOACCESS, SPR_NOACCESS, |
1348 |
&spr_read_generic, &spr_write_generic, |
1349 |
0x00000000);
|
1350 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
1351 |
&spr_read_ureg, SPR_NOACCESS, |
1352 |
&spr_read_ureg, SPR_NOACCESS, |
1353 |
0x00000000);
|
1354 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
1355 |
SPR_NOACCESS, SPR_NOACCESS, |
1356 |
&spr_read_generic, &spr_write_generic, |
1357 |
0x00000000);
|
1358 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
1359 |
&spr_read_ureg, SPR_NOACCESS, |
1360 |
&spr_read_ureg, SPR_NOACCESS, |
1361 |
0x00000000);
|
1362 |
} |
1363 |
|
1364 |
/* FSL storage control registers */
|
1365 |
static void gen_spr_BookE_FSL (CPUPPCState *env) |
1366 |
{ |
1367 |
/* TLB assist registers */
|
1368 |
spr_register(env, SPR_BOOKE_MAS0, "MAS0",
|
1369 |
SPR_NOACCESS, SPR_NOACCESS, |
1370 |
&spr_read_generic, &spr_write_generic, |
1371 |
0x00000000);
|
1372 |
spr_register(env, SPR_BOOKE_MAS1, "MAS2",
|
1373 |
SPR_NOACCESS, SPR_NOACCESS, |
1374 |
&spr_read_generic, &spr_write_generic, |
1375 |
0x00000000);
|
1376 |
spr_register(env, SPR_BOOKE_MAS2, "MAS3",
|
1377 |
SPR_NOACCESS, SPR_NOACCESS, |
1378 |
&spr_read_generic, &spr_write_generic, |
1379 |
0x00000000);
|
1380 |
spr_register(env, SPR_BOOKE_MAS3, "MAS4",
|
1381 |
SPR_NOACCESS, SPR_NOACCESS, |
1382 |
&spr_read_generic, &spr_write_generic, |
1383 |
0x00000000);
|
1384 |
spr_register(env, SPR_BOOKE_MAS4, "MAS5",
|
1385 |
SPR_NOACCESS, SPR_NOACCESS, |
1386 |
&spr_read_generic, &spr_write_generic, |
1387 |
0x00000000);
|
1388 |
spr_register(env, SPR_BOOKE_MAS6, "MAS6",
|
1389 |
SPR_NOACCESS, SPR_NOACCESS, |
1390 |
&spr_read_generic, &spr_write_generic, |
1391 |
0x00000000);
|
1392 |
spr_register(env, SPR_BOOKE_MAS7, "MAS7",
|
1393 |
SPR_NOACCESS, SPR_NOACCESS, |
1394 |
&spr_read_generic, &spr_write_generic, |
1395 |
0x00000000);
|
1396 |
if (env->nb_pids > 1) { |
1397 |
spr_register(env, SPR_BOOKE_PID1, "PID1",
|
1398 |
SPR_NOACCESS, SPR_NOACCESS, |
1399 |
&spr_read_generic, &spr_write_generic, |
1400 |
0x00000000);
|
1401 |
} |
1402 |
if (env->nb_pids > 2) { |
1403 |
spr_register(env, SPR_BOOKE_PID2, "PID2",
|
1404 |
SPR_NOACCESS, SPR_NOACCESS, |
1405 |
&spr_read_generic, &spr_write_generic, |
1406 |
0x00000000);
|
1407 |
} |
1408 |
spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
|
1409 |
SPR_NOACCESS, SPR_NOACCESS, |
1410 |
&spr_read_generic, SPR_NOACCESS, |
1411 |
0x00000000); /* TOFIX */ |
1412 |
spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
|
1413 |
SPR_NOACCESS, SPR_NOACCESS, |
1414 |
&spr_read_generic, &spr_write_generic, |
1415 |
0x00000000); /* TOFIX */ |
1416 |
switch (env->nb_ways) {
|
1417 |
case 4: |
1418 |
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
|
1419 |
SPR_NOACCESS, SPR_NOACCESS, |
1420 |
&spr_read_generic, SPR_NOACCESS, |
1421 |
0x00000000); /* TOFIX */ |
1422 |
/* Fallthru */
|
1423 |
case 3: |
1424 |
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
|
1425 |
SPR_NOACCESS, SPR_NOACCESS, |
1426 |
&spr_read_generic, SPR_NOACCESS, |
1427 |
0x00000000); /* TOFIX */ |
1428 |
/* Fallthru */
|
1429 |
case 2: |
1430 |
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
|
1431 |
SPR_NOACCESS, SPR_NOACCESS, |
1432 |
&spr_read_generic, SPR_NOACCESS, |
1433 |
0x00000000); /* TOFIX */ |
1434 |
/* Fallthru */
|
1435 |
case 1: |
1436 |
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
|
1437 |
SPR_NOACCESS, SPR_NOACCESS, |
1438 |
&spr_read_generic, SPR_NOACCESS, |
1439 |
0x00000000); /* TOFIX */ |
1440 |
/* Fallthru */
|
1441 |
case 0: |
1442 |
default:
|
1443 |
break;
|
1444 |
} |
1445 |
} |
1446 |
|
1447 |
/* SPR specific to PowerPC 440 implementation */
|
1448 |
static void gen_spr_440 (CPUPPCState *env) |
1449 |
{ |
1450 |
/* Cache control */
|
1451 |
/* XXX : not implemented */
|
1452 |
spr_register(env, SPR_440_DNV0, "DNV0",
|
1453 |
SPR_NOACCESS, SPR_NOACCESS, |
1454 |
&spr_read_generic, &spr_write_generic, |
1455 |
0x00000000);
|
1456 |
/* XXX : not implemented */
|
1457 |
spr_register(env, SPR_440_DNV1, "DNV1",
|
1458 |
SPR_NOACCESS, SPR_NOACCESS, |
1459 |
&spr_read_generic, &spr_write_generic, |
1460 |
0x00000000);
|
1461 |
/* XXX : not implemented */
|
1462 |
spr_register(env, SPR_440_DNV2, "DNV2",
|
1463 |
SPR_NOACCESS, SPR_NOACCESS, |
1464 |
&spr_read_generic, &spr_write_generic, |
1465 |
0x00000000);
|
1466 |
/* XXX : not implemented */
|
1467 |
spr_register(env, SPR_440_DNV3, "DNV3",
|
1468 |
SPR_NOACCESS, SPR_NOACCESS, |
1469 |
&spr_read_generic, &spr_write_generic, |
1470 |
0x00000000);
|
1471 |
/* XXX : not implemented */
|
1472 |
spr_register(env, SPR_440_DVT0, "DVT0",
|
1473 |
SPR_NOACCESS, SPR_NOACCESS, |
1474 |
&spr_read_generic, &spr_write_generic, |
1475 |
0x00000000);
|
1476 |
/* XXX : not implemented */
|
1477 |
spr_register(env, SPR_440_DVT1, "DVT1",
|
1478 |
SPR_NOACCESS, SPR_NOACCESS, |
1479 |
&spr_read_generic, &spr_write_generic, |
1480 |
0x00000000);
|
1481 |
/* XXX : not implemented */
|
1482 |
spr_register(env, SPR_440_DVT2, "DVT2",
|
1483 |
SPR_NOACCESS, SPR_NOACCESS, |
1484 |
&spr_read_generic, &spr_write_generic, |
1485 |
0x00000000);
|
1486 |
/* XXX : not implemented */
|
1487 |
spr_register(env, SPR_440_DVT3, "DVT3",
|
1488 |
SPR_NOACCESS, SPR_NOACCESS, |
1489 |
&spr_read_generic, &spr_write_generic, |
1490 |
0x00000000);
|
1491 |
/* XXX : not implemented */
|
1492 |
spr_register(env, SPR_440_DVLIM, "DVLIM",
|
1493 |
SPR_NOACCESS, SPR_NOACCESS, |
1494 |
&spr_read_generic, &spr_write_generic, |
1495 |
0x00000000);
|
1496 |
/* XXX : not implemented */
|
1497 |
spr_register(env, SPR_440_INV0, "INV0",
|
1498 |
SPR_NOACCESS, SPR_NOACCESS, |
1499 |
&spr_read_generic, &spr_write_generic, |
1500 |
0x00000000);
|
1501 |
/* XXX : not implemented */
|
1502 |
spr_register(env, SPR_440_INV1, "INV1",
|
1503 |
SPR_NOACCESS, SPR_NOACCESS, |
1504 |
&spr_read_generic, &spr_write_generic, |
1505 |
0x00000000);
|
1506 |
/* XXX : not implemented */
|
1507 |
spr_register(env, SPR_440_INV2, "INV2",
|
1508 |
SPR_NOACCESS, SPR_NOACCESS, |
1509 |
&spr_read_generic, &spr_write_generic, |
1510 |
0x00000000);
|
1511 |
/* XXX : not implemented */
|
1512 |
spr_register(env, SPR_440_INV3, "INV3",
|
1513 |
SPR_NOACCESS, SPR_NOACCESS, |
1514 |
&spr_read_generic, &spr_write_generic, |
1515 |
0x00000000);
|
1516 |
/* XXX : not implemented */
|
1517 |
spr_register(env, SPR_440_IVT0, "IVT0",
|
1518 |
SPR_NOACCESS, SPR_NOACCESS, |
1519 |
&spr_read_generic, &spr_write_generic, |
1520 |
0x00000000);
|
1521 |
/* XXX : not implemented */
|
1522 |
spr_register(env, SPR_440_IVT1, "IVT1",
|
1523 |
SPR_NOACCESS, SPR_NOACCESS, |
1524 |
&spr_read_generic, &spr_write_generic, |
1525 |
0x00000000);
|
1526 |
/* XXX : not implemented */
|
1527 |
spr_register(env, SPR_440_IVT2, "IVT2",
|
1528 |
SPR_NOACCESS, SPR_NOACCESS, |
1529 |
&spr_read_generic, &spr_write_generic, |
1530 |
0x00000000);
|
1531 |
/* XXX : not implemented */
|
1532 |
spr_register(env, SPR_440_IVT3, "IVT3",
|
1533 |
SPR_NOACCESS, SPR_NOACCESS, |
1534 |
&spr_read_generic, &spr_write_generic, |
1535 |
0x00000000);
|
1536 |
/* XXX : not implemented */
|
1537 |
spr_register(env, SPR_440_IVLIM, "IVLIM",
|
1538 |
SPR_NOACCESS, SPR_NOACCESS, |
1539 |
&spr_read_generic, &spr_write_generic, |
1540 |
0x00000000);
|
1541 |
/* Cache debug */
|
1542 |
/* XXX : not implemented */
|
1543 |
spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
|
1544 |
SPR_NOACCESS, SPR_NOACCESS, |
1545 |
&spr_read_generic, SPR_NOACCESS, |
1546 |
0x00000000);
|
1547 |
/* XXX : not implemented */
|
1548 |
spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
|
1549 |
SPR_NOACCESS, SPR_NOACCESS, |
1550 |
&spr_read_generic, SPR_NOACCESS, |
1551 |
0x00000000);
|
1552 |
/* XXX : not implemented */
|
1553 |
spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
|
1554 |
SPR_NOACCESS, SPR_NOACCESS, |
1555 |
&spr_read_generic, SPR_NOACCESS, |
1556 |
0x00000000);
|
1557 |
/* XXX : not implemented */
|
1558 |
spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
|
1559 |
SPR_NOACCESS, SPR_NOACCESS, |
1560 |
&spr_read_generic, SPR_NOACCESS, |
1561 |
0x00000000);
|
1562 |
/* XXX : not implemented */
|
1563 |
spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
|
1564 |
SPR_NOACCESS, SPR_NOACCESS, |
1565 |
&spr_read_generic, SPR_NOACCESS, |
1566 |
0x00000000);
|
1567 |
/* XXX : not implemented */
|
1568 |
spr_register(env, SPR_440_DBDR, "DBDR",
|
1569 |
SPR_NOACCESS, SPR_NOACCESS, |
1570 |
&spr_read_generic, &spr_write_generic, |
1571 |
0x00000000);
|
1572 |
/* Processor control */
|
1573 |
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
1574 |
SPR_NOACCESS, SPR_NOACCESS, |
1575 |
&spr_read_generic, &spr_write_generic, |
1576 |
0x00000000);
|
1577 |
spr_register(env, SPR_440_RSTCFG, "RSTCFG",
|
1578 |
SPR_NOACCESS, SPR_NOACCESS, |
1579 |
&spr_read_generic, SPR_NOACCESS, |
1580 |
0x00000000);
|
1581 |
/* Storage control */
|
1582 |
spr_register(env, SPR_440_MMUCR, "MMUCR",
|
1583 |
SPR_NOACCESS, SPR_NOACCESS, |
1584 |
&spr_read_generic, &spr_write_generic, |
1585 |
0x00000000);
|
1586 |
} |
1587 |
|
1588 |
/* SPR shared between PowerPC 40x implementations */
|
1589 |
static void gen_spr_40x (CPUPPCState *env) |
1590 |
{ |
1591 |
/* Cache */
|
1592 |
/* XXX : not implemented */
|
1593 |
spr_register(env, SPR_40x_DCCR, "DCCR",
|
1594 |
SPR_NOACCESS, SPR_NOACCESS, |
1595 |
&spr_read_generic, &spr_write_generic, |
1596 |
0x00000000);
|
1597 |
/* XXX : not implemented */
|
1598 |
spr_register(env, SPR_40x_DCWR, "DCWR",
|
1599 |
SPR_NOACCESS, SPR_NOACCESS, |
1600 |
&spr_read_generic, &spr_write_generic, |
1601 |
0x00000000);
|
1602 |
/* XXX : not implemented */
|
1603 |
spr_register(env, SPR_40x_ICCR, "ICCR",
|
1604 |
SPR_NOACCESS, SPR_NOACCESS, |
1605 |
&spr_read_generic, &spr_write_generic, |
1606 |
0x00000000);
|
1607 |
/* XXX : not implemented */
|
1608 |
spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
|
1609 |
SPR_NOACCESS, SPR_NOACCESS, |
1610 |
&spr_read_generic, SPR_NOACCESS, |
1611 |
0x00000000);
|
1612 |
/* Bus access control */
|
1613 |
spr_register(env, SPR_40x_SGR, "SGR",
|
1614 |
SPR_NOACCESS, SPR_NOACCESS, |
1615 |
&spr_read_generic, &spr_write_generic, |
1616 |
0xFFFFFFFF);
|
1617 |
spr_register(env, SPR_40x_ZPR, "ZPR",
|
1618 |
SPR_NOACCESS, SPR_NOACCESS, |
1619 |
&spr_read_generic, &spr_write_generic, |
1620 |
0x00000000);
|
1621 |
/* MMU */
|
1622 |
spr_register(env, SPR_40x_PID, "PID",
|
1623 |
SPR_NOACCESS, SPR_NOACCESS, |
1624 |
&spr_read_generic, &spr_write_generic, |
1625 |
0x00000000);
|
1626 |
/* Exception */
|
1627 |
spr_register(env, SPR_40x_DEAR, "DEAR",
|
1628 |
SPR_NOACCESS, SPR_NOACCESS, |
1629 |
&spr_read_generic, &spr_write_generic, |
1630 |
0x00000000);
|
1631 |
spr_register(env, SPR_40x_ESR, "ESR",
|
1632 |
SPR_NOACCESS, SPR_NOACCESS, |
1633 |
&spr_read_generic, &spr_write_generic, |
1634 |
0x00000000);
|
1635 |
spr_register(env, SPR_40x_EVPR, "EVPR",
|
1636 |
SPR_NOACCESS, SPR_NOACCESS, |
1637 |
&spr_read_generic, &spr_write_generic, |
1638 |
0x00000000);
|
1639 |
spr_register(env, SPR_40x_SRR2, "SRR2",
|
1640 |
&spr_read_generic, &spr_write_generic, |
1641 |
&spr_read_generic, &spr_write_generic, |
1642 |
0x00000000);
|
1643 |
spr_register(env, SPR_40x_SRR3, "SRR3",
|
1644 |
&spr_read_generic, &spr_write_generic, |
1645 |
&spr_read_generic, &spr_write_generic, |
1646 |
0x00000000);
|
1647 |
/* Timers */
|
1648 |
spr_register(env, SPR_40x_PIT, "PIT",
|
1649 |
SPR_NOACCESS, SPR_NOACCESS, |
1650 |
&spr_read_40x_pit, &spr_write_40x_pit, |
1651 |
0x00000000);
|
1652 |
spr_register(env, SPR_40x_TCR, "TCR",
|
1653 |
SPR_NOACCESS, SPR_NOACCESS, |
1654 |
&spr_read_generic, &spr_write_booke_tcr, |
1655 |
0x00000000);
|
1656 |
spr_register(env, SPR_40x_TSR, "TSR",
|
1657 |
SPR_NOACCESS, SPR_NOACCESS, |
1658 |
&spr_read_generic, &spr_write_booke_tsr, |
1659 |
0x00000000);
|
1660 |
/* Debug interface */
|
1661 |
/* XXX : not implemented */
|
1662 |
spr_register(env, SPR_40x_DAC1, "DAC1",
|
1663 |
SPR_NOACCESS, SPR_NOACCESS, |
1664 |
&spr_read_generic, &spr_write_generic, |
1665 |
0x00000000);
|
1666 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
1667 |
SPR_NOACCESS, SPR_NOACCESS, |
1668 |
&spr_read_generic, &spr_write_generic, |
1669 |
0x00000000);
|
1670 |
/* XXX : not implemented */
|
1671 |
spr_register(env, SPR_40x_DBCR0, "DBCR0",
|
1672 |
SPR_NOACCESS, SPR_NOACCESS, |
1673 |
&spr_read_generic, &spr_write_40x_dbcr0, |
1674 |
0x00000000);
|
1675 |
/* XXX : not implemented */
|
1676 |
spr_register(env, SPR_40x_DBSR, "DBSR",
|
1677 |
SPR_NOACCESS, SPR_NOACCESS, |
1678 |
&spr_read_generic, &spr_write_clear, |
1679 |
/* Last reset was system reset */
|
1680 |
0x00000300);
|
1681 |
/* XXX : not implemented */
|
1682 |
spr_register(env, SPR_40x_IAC1, "IAC1",
|
1683 |
SPR_NOACCESS, SPR_NOACCESS, |
1684 |
&spr_read_generic, &spr_write_generic, |
1685 |
0x00000000);
|
1686 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
1687 |
SPR_NOACCESS, SPR_NOACCESS, |
1688 |
&spr_read_generic, &spr_write_generic, |
1689 |
0x00000000);
|
1690 |
} |
1691 |
|
1692 |
/* SPR specific to PowerPC 405 implementation */
|
1693 |
static void gen_spr_405 (CPUPPCState *env) |
1694 |
{ |
1695 |
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
1696 |
SPR_NOACCESS, SPR_NOACCESS, |
1697 |
&spr_read_generic, &spr_write_generic, |
1698 |
0x00700000);
|
1699 |
/* Debug */
|
1700 |
/* XXX : not implemented */
|
1701 |
spr_register(env, SPR_405_DBCR1, "DBCR1",
|
1702 |
SPR_NOACCESS, SPR_NOACCESS, |
1703 |
&spr_read_generic, &spr_write_generic, |
1704 |
0x00000000);
|
1705 |
/* XXX : not implemented */
|
1706 |
spr_register(env, SPR_405_DVC1, "DVC1",
|
1707 |
SPR_NOACCESS, SPR_NOACCESS, |
1708 |
&spr_read_generic, &spr_write_generic, |
1709 |
0x00000000);
|
1710 |
/* XXX : not implemented */
|
1711 |
spr_register(env, SPR_405_DVC2, "DVC2",
|
1712 |
SPR_NOACCESS, SPR_NOACCESS, |
1713 |
&spr_read_generic, &spr_write_generic, |
1714 |
0x00000000);
|
1715 |
/* XXX : not implemented */
|
1716 |
spr_register(env, SPR_405_IAC3, "IAC3",
|
1717 |
SPR_NOACCESS, SPR_NOACCESS, |
1718 |
&spr_read_generic, &spr_write_generic, |
1719 |
0x00000000);
|
1720 |
/* XXX : not implemented */
|
1721 |
spr_register(env, SPR_405_IAC4, "IAC4",
|
1722 |
SPR_NOACCESS, SPR_NOACCESS, |
1723 |
&spr_read_generic, &spr_write_generic, |
1724 |
0x00000000);
|
1725 |
/* Storage control */
|
1726 |
spr_register(env, SPR_405_SLER, "SLER",
|
1727 |
SPR_NOACCESS, SPR_NOACCESS, |
1728 |
&spr_read_generic, &spr_write_40x_sler, |
1729 |
0x00000000);
|
1730 |
/* XXX : not implemented */
|
1731 |
spr_register(env, SPR_405_SU0R, "SU0R",
|
1732 |
SPR_NOACCESS, SPR_NOACCESS, |
1733 |
&spr_read_generic, &spr_write_generic, |
1734 |
0x00000000);
|
1735 |
/* SPRG */
|
1736 |
spr_register(env, SPR_USPRG0, "USPRG0",
|
1737 |
&spr_read_ureg, SPR_NOACCESS, |
1738 |
&spr_read_ureg, SPR_NOACCESS, |
1739 |
0x00000000);
|
1740 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
1741 |
SPR_NOACCESS, SPR_NOACCESS, |
1742 |
&spr_read_generic, &spr_write_generic, |
1743 |
0x00000000);
|
1744 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
1745 |
&spr_read_ureg, SPR_NOACCESS, |
1746 |
&spr_read_ureg, SPR_NOACCESS, |
1747 |
0x00000000);
|
1748 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
1749 |
SPR_NOACCESS, SPR_NOACCESS, |
1750 |
spr_read_generic, &spr_write_generic, |
1751 |
0x00000000);
|
1752 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
1753 |
&spr_read_ureg, SPR_NOACCESS, |
1754 |
&spr_read_ureg, SPR_NOACCESS, |
1755 |
0x00000000);
|
1756 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
1757 |
SPR_NOACCESS, SPR_NOACCESS, |
1758 |
spr_read_generic, &spr_write_generic, |
1759 |
0x00000000);
|
1760 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
1761 |
&spr_read_ureg, SPR_NOACCESS, |
1762 |
&spr_read_ureg, SPR_NOACCESS, |
1763 |
0x00000000);
|
1764 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
1765 |
SPR_NOACCESS, SPR_NOACCESS, |
1766 |
spr_read_generic, &spr_write_generic, |
1767 |
0x00000000);
|
1768 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
1769 |
&spr_read_ureg, SPR_NOACCESS, |
1770 |
&spr_read_ureg, SPR_NOACCESS, |
1771 |
0x00000000);
|
1772 |
} |
1773 |
|
1774 |
/* SPR shared between PowerPC 401 & 403 implementations */
|
1775 |
static void gen_spr_401_403 (CPUPPCState *env) |
1776 |
{ |
1777 |
/* Time base */
|
1778 |
spr_register(env, SPR_403_VTBL, "TBL",
|
1779 |
&spr_read_tbl, SPR_NOACCESS, |
1780 |
&spr_read_tbl, SPR_NOACCESS, |
1781 |
0x00000000);
|
1782 |
spr_register(env, SPR_403_TBL, "TBL",
|
1783 |
SPR_NOACCESS, SPR_NOACCESS, |
1784 |
SPR_NOACCESS, &spr_write_tbl, |
1785 |
0x00000000);
|
1786 |
spr_register(env, SPR_403_VTBU, "TBU",
|
1787 |
&spr_read_tbu, SPR_NOACCESS, |
1788 |
&spr_read_tbu, SPR_NOACCESS, |
1789 |
0x00000000);
|
1790 |
spr_register(env, SPR_403_TBU, "TBU",
|
1791 |
SPR_NOACCESS, SPR_NOACCESS, |
1792 |
SPR_NOACCESS, &spr_write_tbu, |
1793 |
0x00000000);
|
1794 |
/* Debug */
|
1795 |
/* XXX: not implemented */
|
1796 |
spr_register(env, SPR_403_CDBCR, "CDBCR",
|
1797 |
SPR_NOACCESS, SPR_NOACCESS, |
1798 |
&spr_read_generic, &spr_write_generic, |
1799 |
0x00000000);
|
1800 |
} |
1801 |
|
1802 |
/* SPR specific to PowerPC 403 implementation */
|
1803 |
static void gen_spr_403 (CPUPPCState *env) |
1804 |
{ |
1805 |
/* MMU */
|
1806 |
spr_register(env, SPR_403_PBL1, "PBL1",
|
1807 |
SPR_NOACCESS, SPR_NOACCESS, |
1808 |
&spr_read_403_pbr, &spr_write_403_pbr, |
1809 |
0x00000000);
|
1810 |
spr_register(env, SPR_403_PBU1, "PBU1",
|
1811 |
SPR_NOACCESS, SPR_NOACCESS, |
1812 |
&spr_read_403_pbr, &spr_write_403_pbr, |
1813 |
0x00000000);
|
1814 |
spr_register(env, SPR_403_PBL2, "PBL2",
|
1815 |
SPR_NOACCESS, SPR_NOACCESS, |
1816 |
&spr_read_403_pbr, &spr_write_403_pbr, |
1817 |
0x00000000);
|
1818 |
spr_register(env, SPR_403_PBU2, "PBU2",
|
1819 |
SPR_NOACCESS, SPR_NOACCESS, |
1820 |
&spr_read_403_pbr, &spr_write_403_pbr, |
1821 |
0x00000000);
|
1822 |
/* Debug */
|
1823 |
/* XXX : not implemented */
|
1824 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
1825 |
SPR_NOACCESS, SPR_NOACCESS, |
1826 |
&spr_read_generic, &spr_write_generic, |
1827 |
0x00000000);
|
1828 |
/* XXX : not implemented */
|
1829 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
1830 |
SPR_NOACCESS, SPR_NOACCESS, |
1831 |
&spr_read_generic, &spr_write_generic, |
1832 |
0x00000000);
|
1833 |
} |
1834 |
|
1835 |
/* SPR specific to PowerPC compression coprocessor extension */
|
1836 |
#if defined (TODO)
|
1837 |
static void gen_spr_compress (CPUPPCState *env) |
1838 |
{ |
1839 |
spr_register(env, SPR_401_SKR, "SKR",
|
1840 |
SPR_NOACCESS, SPR_NOACCESS, |
1841 |
&spr_read_generic, &spr_write_generic, |
1842 |
0x00000000);
|
1843 |
} |
1844 |
#endif
|
1845 |
|
1846 |
// XXX: TODO (64 bits PowerPC SPRs)
|
1847 |
/*
|
1848 |
* ASR => SPR 280 (64 bits)
|
1849 |
* FPECR => SPR 1022 (?)
|
1850 |
* VRSAVE => SPR 256 (Altivec)
|
1851 |
* SCOMC => SPR 276 (64 bits ?)
|
1852 |
* SCOMD => SPR 277 (64 bits ?)
|
1853 |
* HSPRG0 => SPR 304 (hypervisor)
|
1854 |
* HSPRG1 => SPR 305 (hypervisor)
|
1855 |
* HDEC => SPR 310 (hypervisor)
|
1856 |
* HIOR => SPR 311 (hypervisor)
|
1857 |
* RMOR => SPR 312 (970)
|
1858 |
* HRMOR => SPR 313 (hypervisor)
|
1859 |
* HSRR0 => SPR 314 (hypervisor)
|
1860 |
* HSRR1 => SPR 315 (hypervisor)
|
1861 |
* LPCR => SPR 316 (970)
|
1862 |
* LPIDR => SPR 317 (970)
|
1863 |
* ... and more (thermal management, performance counters, ...)
|
1864 |
*/
|
1865 |
|
1866 |
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) |
1867 |
{ |
1868 |
env->reserve = -1;
|
1869 |
/* Default MMU definitions */
|
1870 |
env->nb_BATs = -1;
|
1871 |
env->nb_tlb = 0;
|
1872 |
env->nb_ways = 0;
|
1873 |
/* XXX: missing:
|
1874 |
* 32 bits PowerPC:
|
1875 |
* - MPC5xx(x)
|
1876 |
* - MPC8xx(x)
|
1877 |
* - RCPU (same as MPC5xx ?)
|
1878 |
*/
|
1879 |
spr_register(env, SPR_PVR, "PVR",
|
1880 |
SPR_NOACCESS, SPR_NOACCESS, |
1881 |
&spr_read_generic, SPR_NOACCESS, |
1882 |
def->pvr); |
1883 |
printf("%s: PVR %08x mask %08x => %08x\n", __func__,
|
1884 |
def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); |
1885 |
switch (def->pvr) {
|
1886 |
/* Embedded PowerPC from IBM */
|
1887 |
case CPU_PPC_401A1: /* 401 A1 family */ |
1888 |
case CPU_PPC_401B2: /* 401 B2 family */ |
1889 |
case CPU_PPC_401C2: /* 401 C2 family */ |
1890 |
case CPU_PPC_401D2: /* 401 D2 family */ |
1891 |
case CPU_PPC_401E2: /* 401 E2 family */ |
1892 |
case CPU_PPC_401F2: /* 401 F2 family */ |
1893 |
case CPU_PPC_401G2: /* 401 G2 family */ |
1894 |
case CPU_PPC_IOP480: /* IOP 480 family */ |
1895 |
case CPU_PPC_COBRA: /* IBM Processor for Network Resources */ |
1896 |
gen_spr_generic(env); |
1897 |
gen_spr_40x(env); |
1898 |
gen_spr_401_403(env); |
1899 |
#if defined (TODO)
|
1900 |
/* XXX: optional ? */
|
1901 |
gen_spr_compress(env); |
1902 |
#endif
|
1903 |
env->nb_BATs = 0;
|
1904 |
env->nb_tlb = 64;
|
1905 |
env->nb_ways = 1;
|
1906 |
env->id_tlbs = 0;
|
1907 |
/* XXX: TODO: allocate internal IRQ controller */
|
1908 |
break;
|
1909 |
|
1910 |
case CPU_PPC_403GA: /* 403 GA family */ |
1911 |
case CPU_PPC_403GB: /* 403 GB family */ |
1912 |
case CPU_PPC_403GC: /* 403 GC family */ |
1913 |
case CPU_PPC_403GCX: /* 403 GCX family */ |
1914 |
gen_spr_generic(env); |
1915 |
gen_spr_40x(env); |
1916 |
gen_spr_401_403(env); |
1917 |
gen_spr_403(env); |
1918 |
env->nb_BATs = 0;
|
1919 |
env->nb_tlb = 64;
|
1920 |
env->nb_ways = 1;
|
1921 |
env->id_tlbs = 0;
|
1922 |
/* XXX: TODO: allocate internal IRQ controller */
|
1923 |
break;
|
1924 |
|
1925 |
case CPU_PPC_405CR: /* 405 GP/CR family */ |
1926 |
case CPU_PPC_405EP: /* 405 EP family */ |
1927 |
case CPU_PPC_405GPR: /* 405 GPR family */ |
1928 |
case CPU_PPC_405D2: /* 405 D2 family */ |
1929 |
case CPU_PPC_405D4: /* 405 D4 family */ |
1930 |
gen_spr_generic(env); |
1931 |
/* Time base */
|
1932 |
gen_tbl(env); |
1933 |
gen_spr_40x(env); |
1934 |
gen_spr_405(env); |
1935 |
env->nb_BATs = 0;
|
1936 |
env->nb_tlb = 64;
|
1937 |
env->nb_ways = 1;
|
1938 |
env->id_tlbs = 0;
|
1939 |
/* Allocate hardware IRQ controller */
|
1940 |
ppc405_irq_init(env); |
1941 |
break;
|
1942 |
|
1943 |
case CPU_PPC_NPE405H: /* NPe405 H family */ |
1944 |
case CPU_PPC_NPE405H2:
|
1945 |
case CPU_PPC_NPE405L: /* Npe405 L family */ |
1946 |
gen_spr_generic(env); |
1947 |
/* Time base */
|
1948 |
gen_tbl(env); |
1949 |
gen_spr_40x(env); |
1950 |
gen_spr_405(env); |
1951 |
env->nb_BATs = 0;
|
1952 |
env->nb_tlb = 64;
|
1953 |
env->nb_ways = 1;
|
1954 |
env->id_tlbs = 0;
|
1955 |
/* Allocate hardware IRQ controller */
|
1956 |
ppc405_irq_init(env); |
1957 |
break;
|
1958 |
|
1959 |
#if defined (TODO)
|
1960 |
case CPU_PPC_STB01000:
|
1961 |
#endif
|
1962 |
#if defined (TODO)
|
1963 |
case CPU_PPC_STB01010:
|
1964 |
#endif
|
1965 |
#if defined (TODO)
|
1966 |
case CPU_PPC_STB0210:
|
1967 |
#endif
|
1968 |
case CPU_PPC_STB03: /* STB03 family */ |
1969 |
#if defined (TODO)
|
1970 |
case CPU_PPC_STB043: /* STB043 family */ |
1971 |
#endif
|
1972 |
#if defined (TODO)
|
1973 |
case CPU_PPC_STB045: /* STB045 family */ |
1974 |
#endif
|
1975 |
case CPU_PPC_STB25: /* STB25 family */ |
1976 |
#if defined (TODO)
|
1977 |
case CPU_PPC_STB130: /* STB130 family */ |
1978 |
#endif
|
1979 |
gen_spr_generic(env); |
1980 |
/* Time base */
|
1981 |
gen_tbl(env); |
1982 |
gen_spr_40x(env); |
1983 |
gen_spr_405(env); |
1984 |
env->nb_BATs = 0;
|
1985 |
env->nb_tlb = 64;
|
1986 |
env->nb_ways = 1;
|
1987 |
env->id_tlbs = 0;
|
1988 |
/* Allocate hardware IRQ controller */
|
1989 |
ppc405_irq_init(env); |
1990 |
break;
|
1991 |
|
1992 |
case CPU_PPC_440EP: /* 440 EP family */ |
1993 |
case CPU_PPC_440GP: /* 440 GP family */ |
1994 |
case CPU_PPC_440GX: /* 440 GX family */ |
1995 |
case CPU_PPC_440GXc: /* 440 GXc family */ |
1996 |
case CPU_PPC_440GXf: /* 440 GXf family */ |
1997 |
case CPU_PPC_440SP: /* 440 SP family */ |
1998 |
case CPU_PPC_440SP2:
|
1999 |
case CPU_PPC_440SPE: /* 440 SPE family */ |
2000 |
gen_spr_generic(env); |
2001 |
/* Time base */
|
2002 |
gen_tbl(env); |
2003 |
gen_spr_BookE(env); |
2004 |
gen_spr_440(env); |
2005 |
env->nb_BATs = 0;
|
2006 |
env->nb_tlb = 64;
|
2007 |
env->nb_ways = 1;
|
2008 |
env->id_tlbs = 0;
|
2009 |
/* XXX: TODO: allocate internal IRQ controller */
|
2010 |
break;
|
2011 |
|
2012 |
/* Embedded PowerPC from Freescale */
|
2013 |
#if defined (TODO)
|
2014 |
case CPU_PPC_5xx:
|
2015 |
break;
|
2016 |
#endif
|
2017 |
#if defined (TODO)
|
2018 |
case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */ |
2019 |
break;
|
2020 |
#endif
|
2021 |
#if defined (TODO)
|
2022 |
case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */ |
2023 |
case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */ |
2024 |
break;
|
2025 |
#endif
|
2026 |
#if defined (TODO)
|
2027 |
case CPU_PPC_827x: /* MPC 827x / 828x */ |
2028 |
break;
|
2029 |
#endif
|
2030 |
|
2031 |
/* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
|
2032 |
case CPU_PPC_e500v110:
|
2033 |
case CPU_PPC_e500v120:
|
2034 |
case CPU_PPC_e500v210:
|
2035 |
case CPU_PPC_e500v220:
|
2036 |
gen_spr_generic(env); |
2037 |
/* Time base */
|
2038 |
gen_tbl(env); |
2039 |
gen_spr_BookE(env); |
2040 |
gen_spr_BookE_FSL(env); |
2041 |
env->nb_BATs = 0;
|
2042 |
env->nb_tlb = 64;
|
2043 |
env->nb_ways = 1;
|
2044 |
env->id_tlbs = 0;
|
2045 |
/* XXX: TODO: allocate internal IRQ controller */
|
2046 |
break;
|
2047 |
|
2048 |
#if defined (TODO)
|
2049 |
case CPU_PPC_e600:
|
2050 |
break;
|
2051 |
#endif
|
2052 |
|
2053 |
/* 32 bits PowerPC */
|
2054 |
case CPU_PPC_601: /* PowerPC 601 */ |
2055 |
gen_spr_generic(env); |
2056 |
gen_spr_ne_601(env); |
2057 |
gen_spr_601(env); |
2058 |
/* Hardware implementation registers */
|
2059 |
/* XXX : not implemented */
|
2060 |
spr_register(env, SPR_HID0, "HID0",
|
2061 |
SPR_NOACCESS, SPR_NOACCESS, |
2062 |
&spr_read_generic, &spr_write_generic, |
2063 |
0x00000000);
|
2064 |
/* XXX : not implemented */
|
2065 |
spr_register(env, SPR_HID1, "HID1",
|
2066 |
SPR_NOACCESS, SPR_NOACCESS, |
2067 |
&spr_read_generic, &spr_write_generic, |
2068 |
0x00000000);
|
2069 |
/* XXX : not implemented */
|
2070 |
spr_register(env, SPR_601_HID2, "HID2",
|
2071 |
SPR_NOACCESS, SPR_NOACCESS, |
2072 |
&spr_read_generic, &spr_write_generic, |
2073 |
0x00000000);
|
2074 |
/* XXX : not implemented */
|
2075 |
spr_register(env, SPR_601_HID5, "HID5",
|
2076 |
SPR_NOACCESS, SPR_NOACCESS, |
2077 |
&spr_read_generic, &spr_write_generic, |
2078 |
0x00000000);
|
2079 |
/* XXX : not implemented */
|
2080 |
#if 0 /* ? */
|
2081 |
spr_register(env, SPR_601_HID15, "HID15",
|
2082 |
SPR_NOACCESS, SPR_NOACCESS,
|
2083 |
&spr_read_generic, &spr_write_generic,
|
2084 |
0x00000000);
|
2085 |
#endif
|
2086 |
env->nb_tlb = 64;
|
2087 |
env->nb_ways = 2;
|
2088 |
env->id_tlbs = 0;
|
2089 |
env->id_tlbs = 0;
|
2090 |
/* XXX: TODO: allocate internal IRQ controller */
|
2091 |
break;
|
2092 |
|
2093 |
case CPU_PPC_602: /* PowerPC 602 */ |
2094 |
gen_spr_generic(env); |
2095 |
gen_spr_ne_601(env); |
2096 |
/* Memory management */
|
2097 |
gen_low_BATs(env); |
2098 |
/* Time base */
|
2099 |
gen_tbl(env); |
2100 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
2101 |
gen_spr_602(env); |
2102 |
/* hardware implementation registers */
|
2103 |
/* XXX : not implemented */
|
2104 |
spr_register(env, SPR_HID0, "HID0",
|
2105 |
SPR_NOACCESS, SPR_NOACCESS, |
2106 |
&spr_read_generic, &spr_write_generic, |
2107 |
0x00000000);
|
2108 |
/* XXX : not implemented */
|
2109 |
spr_register(env, SPR_HID1, "HID1",
|
2110 |
SPR_NOACCESS, SPR_NOACCESS, |
2111 |
&spr_read_generic, &spr_write_generic, |
2112 |
0x00000000);
|
2113 |
/* Allocate hardware IRQ controller */
|
2114 |
ppc6xx_irq_init(env); |
2115 |
break;
|
2116 |
|
2117 |
case CPU_PPC_603: /* PowerPC 603 */ |
2118 |
case CPU_PPC_603E: /* PowerPC 603e */ |
2119 |
case CPU_PPC_603E7v:
|
2120 |
case CPU_PPC_603E7v2:
|
2121 |
case CPU_PPC_603P: /* PowerPC 603p */ |
2122 |
case CPU_PPC_603R: /* PowerPC 603r */ |
2123 |
gen_spr_generic(env); |
2124 |
gen_spr_ne_601(env); |
2125 |
/* Memory management */
|
2126 |
gen_low_BATs(env); |
2127 |
/* Time base */
|
2128 |
gen_tbl(env); |
2129 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
2130 |
gen_spr_603(env); |
2131 |
/* hardware implementation registers */
|
2132 |
/* XXX : not implemented */
|
2133 |
spr_register(env, SPR_HID0, "HID0",
|
2134 |
SPR_NOACCESS, SPR_NOACCESS, |
2135 |
&spr_read_generic, &spr_write_generic, |
2136 |
0x00000000);
|
2137 |
/* XXX : not implemented */
|
2138 |
spr_register(env, SPR_HID1, "HID1",
|
2139 |
SPR_NOACCESS, SPR_NOACCESS, |
2140 |
&spr_read_generic, &spr_write_generic, |
2141 |
0x00000000);
|
2142 |
/* Allocate hardware IRQ controller */
|
2143 |
ppc6xx_irq_init(env); |
2144 |
break;
|
2145 |
|
2146 |
case CPU_PPC_G2: /* PowerPC G2 family */ |
2147 |
case CPU_PPC_G2H4:
|
2148 |
case CPU_PPC_G2gp:
|
2149 |
case CPU_PPC_G2ls:
|
2150 |
case CPU_PPC_G2LE: /* PowerPC G2LE family */ |
2151 |
case CPU_PPC_G2LEgp:
|
2152 |
case CPU_PPC_G2LEls:
|
2153 |
gen_spr_generic(env); |
2154 |
gen_spr_ne_601(env); |
2155 |
/* Memory management */
|
2156 |
gen_low_BATs(env); |
2157 |
/* Time base */
|
2158 |
gen_tbl(env); |
2159 |
/* Memory management */
|
2160 |
gen_high_BATs(env); |
2161 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
2162 |
gen_spr_G2_755(env); |
2163 |
gen_spr_G2(env); |
2164 |
/* Hardware implementation register */
|
2165 |
/* XXX : not implemented */
|
2166 |
spr_register(env, SPR_HID0, "HID0",
|
2167 |
SPR_NOACCESS, SPR_NOACCESS, |
2168 |
&spr_read_generic, &spr_write_generic, |
2169 |
0x00000000);
|
2170 |
/* XXX : not implemented */
|
2171 |
spr_register(env, SPR_HID1, "HID1",
|
2172 |
SPR_NOACCESS, SPR_NOACCESS, |
2173 |
&spr_read_generic, &spr_write_generic, |
2174 |
0x00000000);
|
2175 |
/* XXX : not implemented */
|
2176 |
spr_register(env, SPR_HID2, "HID2",
|
2177 |
SPR_NOACCESS, SPR_NOACCESS, |
2178 |
&spr_read_generic, &spr_write_generic, |
2179 |
0x00000000);
|
2180 |
/* Allocate hardware IRQ controller */
|
2181 |
ppc6xx_irq_init(env); |
2182 |
break;
|
2183 |
|
2184 |
case CPU_PPC_604: /* PowerPC 604 */ |
2185 |
case CPU_PPC_604E: /* PowerPC 604e */ |
2186 |
case CPU_PPC_604R: /* PowerPC 604r */ |
2187 |
gen_spr_generic(env); |
2188 |
gen_spr_ne_601(env); |
2189 |
/* Memory management */
|
2190 |
gen_low_BATs(env); |
2191 |
/* Time base */
|
2192 |
gen_tbl(env); |
2193 |
gen_spr_604(env); |
2194 |
/* Hardware implementation registers */
|
2195 |
/* XXX : not implemented */
|
2196 |
spr_register(env, SPR_HID0, "HID0",
|
2197 |
SPR_NOACCESS, SPR_NOACCESS, |
2198 |
&spr_read_generic, &spr_write_generic, |
2199 |
0x00000000);
|
2200 |
/* XXX : not implemented */
|
2201 |
spr_register(env, SPR_HID1, "HID1",
|
2202 |
SPR_NOACCESS, SPR_NOACCESS, |
2203 |
&spr_read_generic, &spr_write_generic, |
2204 |
0x00000000);
|
2205 |
/* Allocate hardware IRQ controller */
|
2206 |
ppc6xx_irq_init(env); |
2207 |
break;
|
2208 |
|
2209 |
case CPU_PPC_74x: /* PowerPC 740 / 750 */ |
2210 |
case CPU_PPC_740E:
|
2211 |
case CPU_PPC_750E:
|
2212 |
case CPU_PPC_74xP: /* PowerPC 740P / 750P */ |
2213 |
case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */ |
2214 |
case CPU_PPC_750CXE22:
|
2215 |
case CPU_PPC_750CXE23:
|
2216 |
case CPU_PPC_750CXE24:
|
2217 |
case CPU_PPC_750CXE24b:
|
2218 |
case CPU_PPC_750CXE31:
|
2219 |
case CPU_PPC_750CXE31b:
|
2220 |
case CPU_PPC_750CXR:
|
2221 |
gen_spr_generic(env); |
2222 |
gen_spr_ne_601(env); |
2223 |
/* Memory management */
|
2224 |
gen_low_BATs(env); |
2225 |
/* Time base */
|
2226 |
gen_tbl(env); |
2227 |
gen_spr_7xx(env); |
2228 |
/* Hardware implementation registers */
|
2229 |
/* XXX : not implemented */
|
2230 |
spr_register(env, SPR_HID0, "HID0",
|
2231 |
SPR_NOACCESS, SPR_NOACCESS, |
2232 |
&spr_read_generic, &spr_write_generic, |
2233 |
0x00000000);
|
2234 |
/* XXX : not implemented */
|
2235 |
spr_register(env, SPR_HID1, "HID1",
|
2236 |
SPR_NOACCESS, SPR_NOACCESS, |
2237 |
&spr_read_generic, &spr_write_generic, |
2238 |
0x00000000);
|
2239 |
/* Allocate hardware IRQ controller */
|
2240 |
ppc6xx_irq_init(env); |
2241 |
break;
|
2242 |
|
2243 |
case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */ |
2244 |
case CPU_PPC_750FX20:
|
2245 |
case CPU_PPC_750FX21:
|
2246 |
case CPU_PPC_750FX22:
|
2247 |
case CPU_PPC_750FX23:
|
2248 |
case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */ |
2249 |
case CPU_PPC_750GX11:
|
2250 |
case CPU_PPC_750GX12:
|
2251 |
gen_spr_generic(env); |
2252 |
gen_spr_ne_601(env); |
2253 |
/* Memory management */
|
2254 |
gen_low_BATs(env); |
2255 |
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
|
2256 |
gen_high_BATs(env); |
2257 |
/* Time base */
|
2258 |
gen_tbl(env); |
2259 |
gen_spr_7xx(env); |
2260 |
/* Hardware implementation registers */
|
2261 |
/* XXX : not implemented */
|
2262 |
spr_register(env, SPR_HID0, "HID0",
|
2263 |
SPR_NOACCESS, SPR_NOACCESS, |
2264 |
&spr_read_generic, &spr_write_generic, |
2265 |
0x00000000);
|
2266 |
/* XXX : not implemented */
|
2267 |
spr_register(env, SPR_HID1, "HID1",
|
2268 |
SPR_NOACCESS, SPR_NOACCESS, |
2269 |
&spr_read_generic, &spr_write_generic, |
2270 |
0x00000000);
|
2271 |
/* XXX : not implemented */
|
2272 |
spr_register(env, SPR_750_HID2, "HID2",
|
2273 |
SPR_NOACCESS, SPR_NOACCESS, |
2274 |
&spr_read_generic, &spr_write_generic, |
2275 |
0x00000000);
|
2276 |
/* Allocate hardware IRQ controller */
|
2277 |
ppc6xx_irq_init(env); |
2278 |
break;
|
2279 |
|
2280 |
case CPU_PPC_755_10: /* PowerPC 755 */ |
2281 |
case CPU_PPC_755_11:
|
2282 |
case CPU_PPC_755_20:
|
2283 |
case CPU_PPC_755D:
|
2284 |
case CPU_PPC_755E:
|
2285 |
gen_spr_generic(env); |
2286 |
gen_spr_ne_601(env); |
2287 |
/* Memory management */
|
2288 |
gen_low_BATs(env); |
2289 |
/* Time base */
|
2290 |
gen_tbl(env); |
2291 |
/* Memory management */
|
2292 |
gen_high_BATs(env); |
2293 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
2294 |
gen_spr_G2_755(env); |
2295 |
/* L2 cache control */
|
2296 |
/* XXX : not implemented */
|
2297 |
spr_register(env, SPR_ICTC, "ICTC",
|
2298 |
SPR_NOACCESS, SPR_NOACCESS, |
2299 |
&spr_read_generic, &spr_write_generic, |
2300 |
0x00000000);
|
2301 |
/* XXX : not implemented */
|
2302 |
spr_register(env, SPR_L2PM, "L2PM",
|
2303 |
SPR_NOACCESS, SPR_NOACCESS, |
2304 |
&spr_read_generic, &spr_write_generic, |
2305 |
0x00000000);
|
2306 |
/* Hardware implementation registers */
|
2307 |
/* XXX : not implemented */
|
2308 |
spr_register(env, SPR_HID0, "HID0",
|
2309 |
SPR_NOACCESS, SPR_NOACCESS, |
2310 |
&spr_read_generic, &spr_write_generic, |
2311 |
0x00000000);
|
2312 |
/* XXX : not implemented */
|
2313 |
spr_register(env, SPR_HID1, "HID1",
|
2314 |
SPR_NOACCESS, SPR_NOACCESS, |
2315 |
&spr_read_generic, &spr_write_generic, |
2316 |
0x00000000);
|
2317 |
/* XXX : not implemented */
|
2318 |
spr_register(env, SPR_HID2, "HID2",
|
2319 |
SPR_NOACCESS, SPR_NOACCESS, |
2320 |
&spr_read_generic, &spr_write_generic, |
2321 |
0x00000000);
|
2322 |
/* Allocate hardware IRQ controller */
|
2323 |
ppc6xx_irq_init(env); |
2324 |
break;
|
2325 |
|
2326 |
#if defined (TODO)
|
2327 |
/* G4 family */
|
2328 |
case CPU_PPC_7400: /* PowerPC 7400 */ |
2329 |
case CPU_PPC_7410C: /* PowerPC 7410 */ |
2330 |
case CPU_PPC_7410D:
|
2331 |
case CPU_PPC_7410E:
|
2332 |
case CPU_PPC_7441: /* PowerPC 7441 */ |
2333 |
case CPU_PPC_7445: /* PowerPC 7445 */ |
2334 |
case CPU_PPC_7447: /* PowerPC 7447 */ |
2335 |
case CPU_PPC_7447A: /* PowerPC 7447A */ |
2336 |
case CPU_PPC_7448: /* PowerPC 7448 */ |
2337 |
case CPU_PPC_7450: /* PowerPC 7450 */ |
2338 |
case CPU_PPC_7450b:
|
2339 |
case CPU_PPC_7451: /* PowerPC 7451 */ |
2340 |
case CPU_PPC_7451G:
|
2341 |
case CPU_PPC_7455: /* PowerPC 7455 */ |
2342 |
case CPU_PPC_7455F:
|
2343 |
case CPU_PPC_7455G:
|
2344 |
case CPU_PPC_7457: /* PowerPC 7457 */ |
2345 |
case CPU_PPC_7457C:
|
2346 |
case CPU_PPC_7457A: /* PowerPC 7457A */ |
2347 |
break;
|
2348 |
#endif
|
2349 |
|
2350 |
/* 64 bits PowerPC */
|
2351 |
#if defined (TARGET_PPC64)
|
2352 |
#if defined (TODO)
|
2353 |
case CPU_PPC_620: /* PowerPC 620 */ |
2354 |
case CPU_PPC_630: /* PowerPC 630 (Power 3) */ |
2355 |
case CPU_PPC_631: /* PowerPC 631 (Power 3+) */ |
2356 |
case CPU_PPC_POWER4: /* Power 4 */ |
2357 |
case CPU_PPC_POWER4P: /* Power 4+ */ |
2358 |
case CPU_PPC_POWER5: /* Power 5 */ |
2359 |
case CPU_PPC_POWER5P: /* Power 5+ */ |
2360 |
#endif
|
2361 |
break;
|
2362 |
|
2363 |
case CPU_PPC_970: /* PowerPC 970 */ |
2364 |
case CPU_PPC_970FX10: /* PowerPC 970 FX */ |
2365 |
case CPU_PPC_970FX20:
|
2366 |
case CPU_PPC_970FX21:
|
2367 |
case CPU_PPC_970FX30:
|
2368 |
case CPU_PPC_970FX31:
|
2369 |
case CPU_PPC_970MP10: /* PowerPC 970 MP */ |
2370 |
case CPU_PPC_970MP11:
|
2371 |
gen_spr_generic(env); |
2372 |
gen_spr_ne_601(env); |
2373 |
/* XXX: not correct */
|
2374 |
gen_low_BATs(env); |
2375 |
/* Time base */
|
2376 |
gen_tbl(env); |
2377 |
gen_spr_7xx(env); |
2378 |
/* Hardware implementation registers */
|
2379 |
/* XXX : not implemented */
|
2380 |
spr_register(env, SPR_HID0, "HID0",
|
2381 |
SPR_NOACCESS, SPR_NOACCESS, |
2382 |
&spr_read_generic, &spr_write_generic, |
2383 |
0x00000000);
|
2384 |
/* XXX : not implemented */
|
2385 |
spr_register(env, SPR_HID1, "HID1",
|
2386 |
SPR_NOACCESS, SPR_NOACCESS, |
2387 |
&spr_read_generic, &spr_write_generic, |
2388 |
0x00000000);
|
2389 |
/* XXX : not implemented */
|
2390 |
spr_register(env, SPR_750_HID2, "HID2",
|
2391 |
SPR_NOACCESS, SPR_NOACCESS, |
2392 |
&spr_read_generic, &spr_write_generic, |
2393 |
0x00000000);
|
2394 |
/* Allocate hardware IRQ controller */
|
2395 |
ppc970_irq_init(env); |
2396 |
break;
|
2397 |
|
2398 |
#if defined (TODO)
|
2399 |
case CPU_PPC_CELL10: /* Cell family */ |
2400 |
case CPU_PPC_CELL20:
|
2401 |
case CPU_PPC_CELL30:
|
2402 |
case CPU_PPC_CELL31:
|
2403 |
#endif
|
2404 |
break;
|
2405 |
|
2406 |
#if defined (TODO)
|
2407 |
case CPU_PPC_RS64: /* Apache (RS64/A35) */ |
2408 |
case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */ |
2409 |
case CPU_PPC_RS64III: /* Pulsar (RS64-III) */ |
2410 |
case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */ |
2411 |
#endif
|
2412 |
break;
|
2413 |
#endif /* defined (TARGET_PPC64) */ |
2414 |
|
2415 |
#if defined (TODO)
|
2416 |
/* POWER */
|
2417 |
case CPU_POWER: /* POWER */ |
2418 |
case CPU_POWER2: /* POWER2 */ |
2419 |
break;
|
2420 |
#endif
|
2421 |
|
2422 |
default:
|
2423 |
gen_spr_generic(env); |
2424 |
/* XXX: TODO: allocate internal IRQ controller */
|
2425 |
break;
|
2426 |
} |
2427 |
if (env->nb_BATs == -1) |
2428 |
env->nb_BATs = 4;
|
2429 |
/* Allocate TLBs buffer when needed */
|
2430 |
if (env->nb_tlb != 0) { |
2431 |
int nb_tlb = env->nb_tlb;
|
2432 |
if (env->id_tlbs != 0) |
2433 |
nb_tlb *= 2;
|
2434 |
env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
|
2435 |
/* Pre-compute some useful values */
|
2436 |
env->tlb_per_way = env->nb_tlb / env->nb_ways; |
2437 |
} |
2438 |
} |
2439 |
|
2440 |
#if defined(PPC_DUMP_CPU)
|
2441 |
static void dump_sprs (CPUPPCState *env) |
2442 |
{ |
2443 |
ppc_spr_t *spr; |
2444 |
uint32_t pvr = env->spr[SPR_PVR]; |
2445 |
uint32_t sr, sw, ur, uw; |
2446 |
int i, j, n;
|
2447 |
|
2448 |
printf("* SPRs for PVR=%08x\n", pvr);
|
2449 |
for (i = 0; i < 32; i++) { |
2450 |
for (j = 0; j < 32; j++) { |
2451 |
n = (i << 5) | j;
|
2452 |
spr = &env->spr_cb[n]; |
2453 |
#if !defined(CONFIG_USER_ONLY)
|
2454 |
sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
|
2455 |
sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
|
2456 |
#else
|
2457 |
sw = 0;
|
2458 |
sr = 0;
|
2459 |
#endif
|
2460 |
uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
|
2461 |
ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
|
2462 |
if (sw || sr || uw || ur) {
|
2463 |
printf("%4d (%03x) %8s s%c%c u%c%c\n",
|
2464 |
(i << 5) | j, (i << 5) | j, spr->name, |
2465 |
sw ? 'w' : '-', sr ? 'r' : '-', |
2466 |
uw ? 'w' : '-', ur ? 'r' : '-'); |
2467 |
} |
2468 |
} |
2469 |
} |
2470 |
fflush(stdout); |
2471 |
fflush(stderr); |
2472 |
} |
2473 |
#endif
|
2474 |
|
2475 |
/*****************************************************************************/
|
2476 |
#include <stdlib.h> |
2477 |
#include <string.h> |
2478 |
|
2479 |
int fflush (FILE *stream);
|
2480 |
|
2481 |
/* Opcode types */
|
2482 |
enum {
|
2483 |
PPC_DIRECT = 0, /* Opcode routine */ |
2484 |
PPC_INDIRECT = 1, /* Indirect opcode table */ |
2485 |
}; |
2486 |
|
2487 |
static inline int is_indirect_opcode (void *handler) |
2488 |
{ |
2489 |
return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
2490 |
} |
2491 |
|
2492 |
static inline opc_handler_t **ind_table(void *handler) |
2493 |
{ |
2494 |
return (opc_handler_t **)((unsigned long)handler & ~3); |
2495 |
} |
2496 |
|
2497 |
/* Instruction table creation */
|
2498 |
/* Opcodes tables creation */
|
2499 |
static void fill_new_table (opc_handler_t **table, int len) |
2500 |
{ |
2501 |
int i;
|
2502 |
|
2503 |
for (i = 0; i < len; i++) |
2504 |
table[i] = &invalid_handler; |
2505 |
} |
2506 |
|
2507 |
static int create_new_table (opc_handler_t **table, unsigned char idx) |
2508 |
{ |
2509 |
opc_handler_t **tmp; |
2510 |
|
2511 |
tmp = malloc(0x20 * sizeof(opc_handler_t)); |
2512 |
if (tmp == NULL) |
2513 |
return -1; |
2514 |
fill_new_table(tmp, 0x20);
|
2515 |
table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
2516 |
|
2517 |
return 0; |
2518 |
} |
2519 |
|
2520 |
static int insert_in_table (opc_handler_t **table, unsigned char idx, |
2521 |
opc_handler_t *handler) |
2522 |
{ |
2523 |
if (table[idx] != &invalid_handler)
|
2524 |
return -1; |
2525 |
table[idx] = handler; |
2526 |
|
2527 |
return 0; |
2528 |
} |
2529 |
|
2530 |
static int register_direct_insn (opc_handler_t **ppc_opcodes, |
2531 |
unsigned char idx, opc_handler_t *handler) |
2532 |
{ |
2533 |
if (insert_in_table(ppc_opcodes, idx, handler) < 0) { |
2534 |
printf("*** ERROR: opcode %02x already assigned in main "
|
2535 |
"opcode table\n", idx);
|
2536 |
return -1; |
2537 |
} |
2538 |
|
2539 |
return 0; |
2540 |
} |
2541 |
|
2542 |
static int register_ind_in_table (opc_handler_t **table, |
2543 |
unsigned char idx1, unsigned char idx2, |
2544 |
opc_handler_t *handler) |
2545 |
{ |
2546 |
if (table[idx1] == &invalid_handler) {
|
2547 |
if (create_new_table(table, idx1) < 0) { |
2548 |
printf("*** ERROR: unable to create indirect table "
|
2549 |
"idx=%02x\n", idx1);
|
2550 |
return -1; |
2551 |
} |
2552 |
} else {
|
2553 |
if (!is_indirect_opcode(table[idx1])) {
|
2554 |
printf("*** ERROR: idx %02x already assigned to a direct "
|
2555 |
"opcode\n", idx1);
|
2556 |
return -1; |
2557 |
} |
2558 |
} |
2559 |
if (handler != NULL && |
2560 |
insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
2561 |
printf("*** ERROR: opcode %02x already assigned in "
|
2562 |
"opcode table %02x\n", idx2, idx1);
|
2563 |
return -1; |
2564 |
} |
2565 |
|
2566 |
return 0; |
2567 |
} |
2568 |
|
2569 |
static int register_ind_insn (opc_handler_t **ppc_opcodes, |
2570 |
unsigned char idx1, unsigned char idx2, |
2571 |
opc_handler_t *handler) |
2572 |
{ |
2573 |
int ret;
|
2574 |
|
2575 |
ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
2576 |
|
2577 |
return ret;
|
2578 |
} |
2579 |
|
2580 |
static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
2581 |
unsigned char idx1, unsigned char idx2, |
2582 |
unsigned char idx3, opc_handler_t *handler) |
2583 |
{ |
2584 |
if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { |
2585 |
printf("*** ERROR: unable to join indirect table idx "
|
2586 |
"[%02x-%02x]\n", idx1, idx2);
|
2587 |
return -1; |
2588 |
} |
2589 |
if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
|
2590 |
handler) < 0) {
|
2591 |
printf("*** ERROR: unable to insert opcode "
|
2592 |
"[%02x-%02x-%02x]\n", idx1, idx2, idx3);
|
2593 |
return -1; |
2594 |
} |
2595 |
|
2596 |
return 0; |
2597 |
} |
2598 |
|
2599 |
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
2600 |
{ |
2601 |
if (insn->opc2 != 0xFF) { |
2602 |
if (insn->opc3 != 0xFF) { |
2603 |
if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
|
2604 |
insn->opc3, &insn->handler) < 0)
|
2605 |
return -1; |
2606 |
} else {
|
2607 |
if (register_ind_insn(ppc_opcodes, insn->opc1,
|
2608 |
insn->opc2, &insn->handler) < 0)
|
2609 |
return -1; |
2610 |
} |
2611 |
} else {
|
2612 |
if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
2613 |
return -1; |
2614 |
} |
2615 |
|
2616 |
return 0; |
2617 |
} |
2618 |
|
2619 |
static int test_opcode_table (opc_handler_t **table, int len) |
2620 |
{ |
2621 |
int i, count, tmp;
|
2622 |
|
2623 |
for (i = 0, count = 0; i < len; i++) { |
2624 |
/* Consistency fixup */
|
2625 |
if (table[i] == NULL) |
2626 |
table[i] = &invalid_handler; |
2627 |
if (table[i] != &invalid_handler) {
|
2628 |
if (is_indirect_opcode(table[i])) {
|
2629 |
tmp = test_opcode_table(ind_table(table[i]), 0x20);
|
2630 |
if (tmp == 0) { |
2631 |
free(table[i]); |
2632 |
table[i] = &invalid_handler; |
2633 |
} else {
|
2634 |
count++; |
2635 |
} |
2636 |
} else {
|
2637 |
count++; |
2638 |
} |
2639 |
} |
2640 |
} |
2641 |
|
2642 |
return count;
|
2643 |
} |
2644 |
|
2645 |
static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
2646 |
{ |
2647 |
if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
2648 |
printf("*** WARNING: no opcode defined !\n");
|
2649 |
} |
2650 |
|
2651 |
/*****************************************************************************/
|
2652 |
static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) |
2653 |
{ |
2654 |
opcode_t *opc, *start, *end; |
2655 |
|
2656 |
fill_new_table(env->opcodes, 0x40);
|
2657 |
#if defined(PPC_DUMP_CPU)
|
2658 |
printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
|
2659 |
" %08x\n",
|
2660 |
def->pvr, def->name, def->insns_flags, def->flags); |
2661 |
#endif
|
2662 |
if (&opc_start < &opc_end) {
|
2663 |
start = &opc_start; |
2664 |
end = &opc_end; |
2665 |
} else {
|
2666 |
start = &opc_end; |
2667 |
end = &opc_start; |
2668 |
} |
2669 |
for (opc = start + 1; opc != end; opc++) { |
2670 |
if ((opc->handler.type & def->insns_flags) != 0) { |
2671 |
if (register_insn(env->opcodes, opc) < 0) { |
2672 |
printf("*** ERROR initializing PowerPC instruction "
|
2673 |
"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
|
2674 |
opc->opc3); |
2675 |
return -1; |
2676 |
} |
2677 |
#if defined(PPC_DUMP_CPU)
|
2678 |
if (opc1 != 0x00) { |
2679 |
if (opc->opc3 == 0xFF) { |
2680 |
if (opc->opc2 == 0xFF) { |
2681 |
printf(" %02x -- -- (%2d ----) : %s\n",
|
2682 |
opc->opc1, opc->opc1, opc->oname); |
2683 |
} else {
|
2684 |
printf(" %02x %02x -- (%2d %4d) : %s\n",
|
2685 |
opc->opc1, opc->opc2, opc->opc1, opc->opc2, |
2686 |
opc->oname); |
2687 |
} |
2688 |
} else {
|
2689 |
printf(" %02x %02x %02x (%2d %4d) : %s\n",
|
2690 |
opc->opc1, opc->opc2, opc->opc3, |
2691 |
opc->opc1, (opc->opc3 << 5) | opc->opc2,
|
2692 |
opc->oname); |
2693 |
} |
2694 |
} |
2695 |
#endif
|
2696 |
} |
2697 |
} |
2698 |
fix_opcode_tables(env->opcodes); |
2699 |
fflush(stdout); |
2700 |
fflush(stderr); |
2701 |
|
2702 |
return 0; |
2703 |
} |
2704 |
|
2705 |
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
|
2706 |
{ |
2707 |
env->msr_mask = def->msr_mask; |
2708 |
env->flags = def->flags; |
2709 |
if (create_ppc_opcodes(env, def) < 0) |
2710 |
return -1; |
2711 |
init_ppc_proc(env, def); |
2712 |
#if defined(PPC_DUMP_CPU)
|
2713 |
dump_sprs(env); |
2714 |
if (env->tlb != NULL) { |
2715 |
printf("%d %s TLB in %d ways\n", env->nb_tlb,
|
2716 |
env->id_tlbs ? "splitted" : "merged", env->nb_ways); |
2717 |
} |
2718 |
#endif
|
2719 |
|
2720 |
return 0; |
2721 |
} |
2722 |
|
2723 |
/*****************************************************************************/
|
2724 |
/* PowerPC CPU definitions */
|
2725 |
static ppc_def_t ppc_defs[] = {
|
2726 |
/* Embedded PowerPC */
|
2727 |
#if defined (TODO)
|
2728 |
/* PowerPC 401 */
|
2729 |
{ |
2730 |
.name = "401",
|
2731 |
.pvr = CPU_PPC_401, |
2732 |
.pvr_mask = 0xFFFF0000,
|
2733 |
.insns_flags = PPC_INSNS_401, |
2734 |
.flags = PPC_FLAGS_401, |
2735 |
.msr_mask = xxx, |
2736 |
}, |
2737 |
#endif
|
2738 |
#if defined (TODO)
|
2739 |
/* IOP480 (401 microcontroler) */
|
2740 |
{ |
2741 |
.name = "iop480",
|
2742 |
.pvr = CPU_PPC_IOP480, |
2743 |
.pvr_mask = 0xFFFF0000,
|
2744 |
.insns_flags = PPC_INSNS_401, |
2745 |
.flags = PPC_FLAGS_401, |
2746 |
.msr_mask = xxx, |
2747 |
}, |
2748 |
#endif
|
2749 |
#if defined (TODO)
|
2750 |
/* IBM Processor for Network Resources */
|
2751 |
{ |
2752 |
.name = "Cobra",
|
2753 |
.pvr = CPU_PPC_COBRA, |
2754 |
.pvr_mask = 0xFFFF0000,
|
2755 |
.insns_flags = PPC_INSNS_401, |
2756 |
.flags = PPC_FLAGS_401, |
2757 |
.msr_mask = xxx, |
2758 |
}, |
2759 |
#endif
|
2760 |
#if defined (TODO)
|
2761 |
/* Generic PowerPC 403 */
|
2762 |
{ |
2763 |
.name = "403",
|
2764 |
.pvr = CPU_PPC_403, |
2765 |
.pvr_mask = 0xFFFFFF00,
|
2766 |
.insns_flags = PPC_INSNS_403, |
2767 |
.flags = PPC_FLAGS_403, |
2768 |
.msr_mask = 0x000000000007D23DULL,
|
2769 |
}, |
2770 |
#endif
|
2771 |
#if defined (TODO)
|
2772 |
/* PowerPC 403 GA */
|
2773 |
{ |
2774 |
.name = "403ga",
|
2775 |
.pvr = CPU_PPC_403GA, |
2776 |
.pvr_mask = 0xFFFFFF00,
|
2777 |
.insns_flags = PPC_INSNS_403, |
2778 |
.flags = PPC_FLAGS_403, |
2779 |
.msr_mask = 0x000000000007D23DULL,
|
2780 |
}, |
2781 |
#endif
|
2782 |
#if defined (TODO)
|
2783 |
/* PowerPC 403 GB */
|
2784 |
{ |
2785 |
.name = "403gb",
|
2786 |
.pvr = CPU_PPC_403GB, |
2787 |
.pvr_mask = 0xFFFFFF00,
|
2788 |
.insns_flags = PPC_INSNS_403, |
2789 |
.flags = PPC_FLAGS_403, |
2790 |
.msr_mask = 0x000000000007D23DULL,
|
2791 |
}, |
2792 |
#endif
|
2793 |
#if defined (TODO)
|
2794 |
/* PowerPC 403 GC */
|
2795 |
{ |
2796 |
.name = "403gc",
|
2797 |
.pvr = CPU_PPC_403GC, |
2798 |
.pvr_mask = 0xFFFFFF00,
|
2799 |
.insns_flags = PPC_INSNS_403, |
2800 |
.flags = PPC_FLAGS_403, |
2801 |
.msr_mask = 0x000000000007D23DULL,
|
2802 |
}, |
2803 |
#endif
|
2804 |
#if defined (TODO)
|
2805 |
/* PowerPC 403 GCX */
|
2806 |
{ |
2807 |
.name = "403gcx",
|
2808 |
.pvr = CPU_PPC_403GCX, |
2809 |
.pvr_mask = 0xFFFFFF00,
|
2810 |
.insns_flags = PPC_INSNS_403, |
2811 |
.flags = PPC_FLAGS_403, |
2812 |
.msr_mask = 0x000000000007D23DULL,
|
2813 |
}, |
2814 |
#endif
|
2815 |
/* Generic PowerPC 405 */
|
2816 |
{ |
2817 |
.name = "405",
|
2818 |
.pvr = CPU_PPC_405, |
2819 |
.pvr_mask = 0xFFFF0000,
|
2820 |
.insns_flags = PPC_INSNS_405, |
2821 |
.flags = PPC_FLAGS_405, |
2822 |
.msr_mask = 0x00000000020EFF30ULL,
|
2823 |
}, |
2824 |
/* PowerPC 405 CR */
|
2825 |
{ |
2826 |
.name = "405cr",
|
2827 |
.pvr = CPU_PPC_405, |
2828 |
.pvr_mask = 0xFFFFFFFF,
|
2829 |
.insns_flags = PPC_INSNS_405, |
2830 |
.flags = PPC_FLAGS_405, |
2831 |
.msr_mask = 0x00000000020EFF30ULL,
|
2832 |
}, |
2833 |
#if defined (TODO)
|
2834 |
/* PowerPC 405 GP */
|
2835 |
{ |
2836 |
.name = "405gp",
|
2837 |
.pvr = CPU_PPC_405, |
2838 |
.pvr_mask = 0xFFFFFFFF,
|
2839 |
.insns_flags = PPC_INSNS_405, |
2840 |
.flags = PPC_FLAGS_405, |
2841 |
.msr_mask = 0x00000000020EFF30ULL,
|
2842 |
}, |
2843 |
#endif
|
2844 |
/* PowerPC 405 EP */
|
2845 |
{ |
2846 |
.name = "405ep",
|
2847 |
.pvr = CPU_PPC_405EP, |
2848 |
.pvr_mask = 0xFFFFFFFF,
|
2849 |
.insns_flags = PPC_INSNS_405, |
2850 |
.flags = PPC_FLAGS_405, |
2851 |
.msr_mask = 0x00000000000ED630ULL,
|
2852 |
}, |
2853 |
#if defined (TODO)
|
2854 |
/* PowerPC 405 EZ */
|
2855 |
{ |
2856 |
.name = "405ez",
|
2857 |
.pvr = CPU_PPC_405EZ, |
2858 |
.pvr_mask = 0xFFFFFFFF,
|
2859 |
.insns_flags = PPC_INSNS_405, |
2860 |
.flags = PPC_FLAGS_405, |
2861 |
.msr_mask = 0x00000000020EFF30ULL,
|
2862 |
}, |
2863 |
#endif
|
2864 |
#if defined (TODO)
|
2865 |
/* PowerPC 405 GPR */
|
2866 |
{ |
2867 |
.name = "405gpr",
|
2868 |
.pvr = CPU_PPC_405GPR, |
2869 |
.pvr_mask = 0xFFFFFFFF,
|
2870 |
.insns_flags = PPC_INSNS_405, |
2871 |
.flags = PPC_FLAGS_405, |
2872 |
.msr_mask = 0x00000000020EFF30ULL,
|
2873 |
}, |
2874 |
#endif
|
2875 |
/* PowerPC 405 D2 */
|
2876 |
{ |
2877 |
.name = "405d2",
|
2878 |
.pvr = CPU_PPC_405D2, |
2879 |
.pvr_mask = 0xFFFFFFFF,
|
2880 |
.insns_flags = PPC_INSNS_405, |
2881 |
.flags = PPC_FLAGS_405, |
2882 |
.msr_mask = 0x00000000020EFF30ULL,
|
2883 |
}, |
2884 |
/* PowerPC 405 D4 */
|
2885 |
{ |
2886 |
.name = "405d4",
|
2887 |
.pvr = CPU_PPC_405D4, |
2888 |
.pvr_mask = 0xFFFFFFFF,
|
2889 |
.insns_flags = PPC_INSNS_405, |
2890 |
.flags = PPC_FLAGS_405, |
2891 |
.msr_mask = 0x00000000020EFF30ULL,
|
2892 |
}, |
2893 |
#if defined (TODO)
|
2894 |
/* Npe405 H */
|
2895 |
{ |
2896 |
.name = "Npe405H",
|
2897 |
.pvr = CPU_PPC_NPE405H, |
2898 |
.pvr_mask = 0xFFFFFFFF,
|
2899 |
.insns_flags = PPC_INSNS_405, |
2900 |
.flags = PPC_FLAGS_405, |
2901 |
.msr_mask = 0x00000000020EFF30ULL,
|
2902 |
}, |
2903 |
#endif
|
2904 |
#if defined (TODO)
|
2905 |
/* Npe405 L */
|
2906 |
{ |
2907 |
.name = "Npe405L",
|
2908 |
.pvr = CPU_PPC_NPE405L, |
2909 |
.pvr_mask = 0xFFFFFFFF,
|
2910 |
.insns_flags = PPC_INSNS_405, |
2911 |
.flags = PPC_FLAGS_405, |
2912 |
.msr_mask = 0x00000000020EFF30ULL,
|
2913 |
}, |
2914 |
#endif
|
2915 |
#if defined (TODO)
|
2916 |
/* STB010000 */
|
2917 |
{ |
2918 |
.name = "STB01000",
|
2919 |
.pvr = CPU_PPC_STB01000, |
2920 |
.pvr_mask = 0xFFFFFFFF,
|
2921 |
.insns_flags = PPC_INSNS_405, |
2922 |
.flags = PPC_FLAGS_405, |
2923 |
.msr_mask = 0x00000000020EFF30ULL,
|
2924 |
}, |
2925 |
#endif
|
2926 |
#if defined (TODO)
|
2927 |
/* STB01010 */
|
2928 |
{ |
2929 |
.name = "STB01010",
|
2930 |
.pvr = CPU_PPC_STB01010, |
2931 |
.pvr_mask = 0xFFFFFFFF,
|
2932 |
.insns_flags = PPC_INSNS_405, |
2933 |
.flags = PPC_FLAGS_405, |
2934 |
.msr_mask = 0x00000000020EFF30ULL,
|
2935 |
}, |
2936 |
#endif
|
2937 |
#if defined (TODO)
|
2938 |
/* STB0210 */
|
2939 |
{ |
2940 |
.name = "STB0210",
|
2941 |
.pvr = CPU_PPC_STB0210, |
2942 |
.pvr_mask = 0xFFFFFFFF,
|
2943 |
.insns_flags = PPC_INSNS_405, |
2944 |
.flags = PPC_FLAGS_405, |
2945 |
.msr_mask = 0x00000000020EFF30ULL,
|
2946 |
}, |
2947 |
#endif
|
2948 |
#if defined (TODO)
|
2949 |
/* STB03xx */
|
2950 |
{ |
2951 |
.name = "STB03",
|
2952 |
.pvr = CPU_PPC_STB03, |
2953 |
.pvr_mask = 0xFFFFFFFF,
|
2954 |
.insns_flags = PPC_INSNS_405, |
2955 |
.flags = PPC_FLAGS_405, |
2956 |
.msr_mask = 0x00000000020EFF30ULL,
|
2957 |
}, |
2958 |
#endif
|
2959 |
#if defined (TODO)
|
2960 |
/* STB043x */
|
2961 |
{ |
2962 |
.name = "STB043",
|
2963 |
.pvr = CPU_PPC_STB043, |
2964 |
.pvr_mask = 0xFFFFFFFF,
|
2965 |
.insns_flags = PPC_INSNS_405, |
2966 |
.flags = PPC_FLAGS_405, |
2967 |
.msr_mask = 0x00000000020EFF30ULL,
|
2968 |
}, |
2969 |
#endif
|
2970 |
#if defined (TODO)
|
2971 |
/* STB045x */
|
2972 |
{ |
2973 |
.name = "STB045",
|
2974 |
.pvr = CPU_PPC_STB045, |
2975 |
.pvr_mask = 0xFFFFFFFF,
|
2976 |
.insns_flags = PPC_INSNS_405, |
2977 |
.flags = PPC_FLAGS_405, |
2978 |
.msr_mask = 0x00000000020EFF30ULL,
|
2979 |
}, |
2980 |
#endif
|
2981 |
#if defined (TODO)
|
2982 |
/* STB25xx */
|
2983 |
{ |
2984 |
.name = "STB25",
|
2985 |
.pvr = CPU_PPC_STB25, |
2986 |
.pvr_mask = 0xFFFFFFFF,
|
2987 |
.insns_flags = PPC_INSNS_405, |
2988 |
.flags = PPC_FLAGS_405, |
2989 |
.msr_mask = 0x00000000020EFF30ULL,
|
2990 |
}, |
2991 |
#endif
|
2992 |
#if defined (TODO)
|
2993 |
/* STB130 */
|
2994 |
{ |
2995 |
.name = "STB130",
|
2996 |
.pvr = CPU_PPC_STB130, |
2997 |
.pvr_mask = 0xFFFFFFFF,
|
2998 |
.insns_flags = PPC_INSNS_405, |
2999 |
.flags = PPC_FLAGS_405, |
3000 |
.msr_mask = 0x00000000020EFF30ULL,
|
3001 |
}, |
3002 |
#endif
|
3003 |
/* Xilinx PowerPC 405 cores */
|
3004 |
#if defined (TODO)
|
3005 |
{ |
3006 |
.name = "x2vp4",
|
3007 |
.pvr = CPU_PPC_X2VP4, |
3008 |
.pvr_mask = 0xFFFFFFFF,
|
3009 |
.insns_flags = PPC_INSNS_405, |
3010 |
.flags = PPC_FLAGS_405, |
3011 |
.msr_mask = 0x00000000020EFF30ULL,
|
3012 |
}, |
3013 |
{ |
3014 |
.name = "x2vp7",
|
3015 |
.pvr = CPU_PPC_X2VP7, |
3016 |
.pvr_mask = 0xFFFFFFFF,
|
3017 |
.insns_flags = PPC_INSNS_405, |
3018 |
.flags = PPC_FLAGS_405, |
3019 |
.msr_mask = 0x00000000020EFF30ULL,
|
3020 |
}, |
3021 |
{ |
3022 |
.name = "x2vp20",
|
3023 |
.pvr = CPU_PPC_X2VP20, |
3024 |
.pvr_mask = 0xFFFFFFFF,
|
3025 |
.insns_flags = PPC_INSNS_405, |
3026 |
.flags = PPC_FLAGS_405, |
3027 |
.msr_mask = 0x00000000020EFF30ULL,
|
3028 |
}, |
3029 |
{ |
3030 |
.name = "x2vp50",
|
3031 |
.pvr = CPU_PPC_X2VP50, |
3032 |
.pvr_mask = 0xFFFFFFFF,
|
3033 |
.insns_flags = PPC_INSNS_405, |
3034 |
.flags = PPC_FLAGS_405, |
3035 |
.msr_mask = 0x00000000020EFF30ULL,
|
3036 |
}, |
3037 |
#endif
|
3038 |
#if defined (TODO)
|
3039 |
/* PowerPC 440 EP */
|
3040 |
{ |
3041 |
.name = "440ep",
|
3042 |
.pvr = CPU_PPC_440EP, |
3043 |
.pvr_mask = 0xFFFF0000,
|
3044 |
.insns_flags = PPC_INSNS_440, |
3045 |
.flags = PPC_FLAGS_440, |
3046 |
.msr_mask = 0x000000000006D630ULL,
|
3047 |
}, |
3048 |
#endif
|
3049 |
#if defined (TODO)
|
3050 |
/* PowerPC 440 GR */
|
3051 |
{ |
3052 |
.name = "440gr",
|
3053 |
.pvr = CPU_PPC_440GR, |
3054 |
.pvr_mask = 0xFFFF0000,
|
3055 |
.insns_flags = PPC_INSNS_440, |
3056 |
.flags = PPC_FLAGS_440, |
3057 |
.msr_mask = 0x000000000006D630ULL,
|
3058 |
}, |
3059 |
#endif
|
3060 |
#if defined (TODO)
|
3061 |
/* PowerPC 440 GP */
|
3062 |
{ |
3063 |
.name = "440gp",
|
3064 |
.pvr = CPU_PPC_440GP, |
3065 |
.pvr_mask = 0xFFFFFF00,
|
3066 |
.insns_flags = PPC_INSNS_440, |
3067 |
.flags = PPC_FLAGS_440, |
3068 |
.msr_mask = 0x000000000006D630ULL,
|
3069 |
}, |
3070 |
#endif
|
3071 |
#if defined (TODO)
|
3072 |
/* PowerPC 440 GX */
|
3073 |
{ |
3074 |
.name = "440gx",
|
3075 |
.pvr = CPU_PPC_440GX, |
3076 |
.pvr_mask = 0xFFFF0000,
|
3077 |
.insns_flags = PPC_INSNS_405, |
3078 |
.flags = PPC_FLAGS_440, |
3079 |
.msr_mask = 0x000000000006D630ULL,
|
3080 |
}, |
3081 |
#endif
|
3082 |
#if defined (TODO)
|
3083 |
/* PowerPC 440 GXc */
|
3084 |
{ |
3085 |
.name = "440gxc",
|
3086 |
.pvr = CPU_PPC_440GXC, |
3087 |
.pvr_mask = 0xFFFF0000,
|
3088 |
.insns_flags = PPC_INSNS_405, |
3089 |
.flags = PPC_FLAGS_440, |
3090 |
.msr_mask = 0x000000000006D630ULL,
|
3091 |
}, |
3092 |
#endif
|
3093 |
#if defined (TODO)
|
3094 |
/* PowerPC 440 GXf */
|
3095 |
{ |
3096 |
.name = "440gxf",
|
3097 |
.pvr = CPU_PPC_440GXF, |
3098 |
.pvr_mask = 0xFFFF0000,
|
3099 |
.insns_flags = PPC_INSNS_405, |
3100 |
.flags = PPC_FLAGS_440, |
3101 |
.msr_mask = 0x000000000006D630ULL,
|
3102 |
}, |
3103 |
#endif
|
3104 |
#if defined (TODO)
|
3105 |
/* PowerPC 440 SP */
|
3106 |
{ |
3107 |
.name = "440sp",
|
3108 |
.pvr = CPU_PPC_440SP, |
3109 |
.pvr_mask = 0xFFFF0000,
|
3110 |
.insns_flags = PPC_INSNS_405, |
3111 |
.flags = PPC_FLAGS_440, |
3112 |
.msr_mask = 0x000000000006D630ULL,
|
3113 |
}, |
3114 |
#endif
|
3115 |
#if defined (TODO)
|
3116 |
/* PowerPC 440 SP2 */
|
3117 |
{ |
3118 |
.name = "440sp2",
|
3119 |
.pvr = CPU_PPC_440SP2, |
3120 |
.pvr_mask = 0xFFFF0000,
|
3121 |
.insns_flags = PPC_INSNS_405, |
3122 |
.flags = PPC_FLAGS_440, |
3123 |
.msr_mask = 0x000000000006D630ULL,
|
3124 |
}, |
3125 |
#endif
|
3126 |
#if defined (TODO)
|
3127 |
/* PowerPC 440 SPE */
|
3128 |
{ |
3129 |
.name = "440spe",
|
3130 |
.pvr = CPU_PPC_440SPE, |
3131 |
.pvr_mask = 0xFFFF0000,
|
3132 |
.insns_flags = PPC_INSNS_405, |
3133 |
.flags = PPC_FLAGS_440, |
3134 |
.msr_mask = 0x000000000006D630ULL,
|
3135 |
}, |
3136 |
#endif
|
3137 |
/* Fake generic BookE PowerPC */
|
3138 |
{ |
3139 |
.name = "BookE",
|
3140 |
.pvr = CPU_PPC_e500, |
3141 |
.pvr_mask = 0xFFFFFFFF,
|
3142 |
.insns_flags = PPC_INSNS_BOOKE, |
3143 |
.flags = PPC_FLAGS_BOOKE, |
3144 |
.msr_mask = 0x000000000006D630ULL,
|
3145 |
}, |
3146 |
/* PowerPC 460 cores - TODO */
|
3147 |
/* PowerPC MPC 5xx cores - TODO */
|
3148 |
/* PowerPC MPC 8xx cores - TODO */
|
3149 |
/* PowerPC MPC 8xxx cores - TODO */
|
3150 |
/* e200 cores - TODO */
|
3151 |
/* e500 cores - TODO */
|
3152 |
/* e600 cores - TODO */
|
3153 |
|
3154 |
/* 32 bits "classic" PowerPC */
|
3155 |
#if defined (TODO)
|
3156 |
/* PowerPC 601 */
|
3157 |
{ |
3158 |
.name = "601",
|
3159 |
.pvr = CPU_PPC_601, |
3160 |
.pvr_mask = 0xFFFF0000,
|
3161 |
.insns_flags = PPC_INSNS_601, |
3162 |
.flags = PPC_FLAGS_601, |
3163 |
.msr_mask = 0x000000000000FD70ULL,
|
3164 |
}, |
3165 |
#endif
|
3166 |
#if defined (TODO)
|
3167 |
/* PowerPC 602 */
|
3168 |
{ |
3169 |
.name = "602",
|
3170 |
.pvr = CPU_PPC_602, |
3171 |
.pvr_mask = 0xFFFF0000,
|
3172 |
.insns_flags = PPC_INSNS_602, |
3173 |
.flags = PPC_FLAGS_602, |
3174 |
.msr_mask = 0x0000000000C7FF73ULL,
|
3175 |
}, |
3176 |
#endif
|
3177 |
/* PowerPC 603 */
|
3178 |
{ |
3179 |
.name = "603",
|
3180 |
.pvr = CPU_PPC_603, |
3181 |
.pvr_mask = 0xFFFFFFFF,
|
3182 |
.insns_flags = PPC_INSNS_603, |
3183 |
.flags = PPC_FLAGS_603, |
3184 |
.msr_mask = 0x000000000007FF73ULL,
|
3185 |
}, |
3186 |
/* PowerPC 603e */
|
3187 |
{ |
3188 |
.name = "603e",
|
3189 |
.pvr = CPU_PPC_603E, |
3190 |
.pvr_mask = 0xFFFFFFFF,
|
3191 |
.insns_flags = PPC_INSNS_603, |
3192 |
.flags = PPC_FLAGS_603, |
3193 |
.msr_mask = 0x000000000007FF73ULL,
|
3194 |
}, |
3195 |
{ |
3196 |
.name = "Stretch",
|
3197 |
.pvr = CPU_PPC_603E, |
3198 |
.pvr_mask = 0xFFFFFFFF,
|
3199 |
.insns_flags = PPC_INSNS_603, |
3200 |
.flags = PPC_FLAGS_603, |
3201 |
.msr_mask = 0x000000000007FF73ULL,
|
3202 |
}, |
3203 |
/* PowerPC 603p */
|
3204 |
{ |
3205 |
.name = "603p",
|
3206 |
.pvr = CPU_PPC_603P, |
3207 |
.pvr_mask = 0xFFFFFFFF,
|
3208 |
.insns_flags = PPC_INSNS_603, |
3209 |
.flags = PPC_FLAGS_603, |
3210 |
.msr_mask = 0x000000000007FF73ULL,
|
3211 |
}, |
3212 |
/* PowerPC 603e7 */
|
3213 |
{ |
3214 |
.name = "603e7",
|
3215 |
.pvr = CPU_PPC_603E7, |
3216 |
.pvr_mask = 0xFFFFFFFF,
|
3217 |
.insns_flags = PPC_INSNS_603, |
3218 |
.flags = PPC_FLAGS_603, |
3219 |
.msr_mask = 0x000000000007FF73ULL,
|
3220 |
}, |
3221 |
/* PowerPC 603e7v */
|
3222 |
{ |
3223 |
.name = "603e7v",
|
3224 |
.pvr = CPU_PPC_603E7v, |
3225 |
.pvr_mask = 0xFFFFFFFF,
|
3226 |
.insns_flags = PPC_INSNS_603, |
3227 |
.flags = PPC_FLAGS_603, |
3228 |
.msr_mask = 0x000000000007FF73ULL,
|
3229 |
}, |
3230 |
/* PowerPC 603e7v2 */
|
3231 |
{ |
3232 |
.name = "603e7v2",
|
3233 |
.pvr = CPU_PPC_603E7v2, |
3234 |
.pvr_mask = 0xFFFFFFFF,
|
3235 |
.insns_flags = PPC_INSNS_603, |
3236 |
.flags = PPC_FLAGS_603, |
3237 |
.msr_mask = 0x000000000007FF73ULL,
|
3238 |
}, |
3239 |
/* PowerPC 603r */
|
3240 |
{ |
3241 |
.name = "603r",
|
3242 |
.pvr = CPU_PPC_603R, |
3243 |
.pvr_mask = 0xFFFFFFFF,
|
3244 |
.insns_flags = PPC_INSNS_603, |
3245 |
.flags = PPC_FLAGS_603, |
3246 |
.msr_mask = 0x000000000007FF73ULL,
|
3247 |
}, |
3248 |
{ |
3249 |
.name = "Goldeneye",
|
3250 |
.pvr = CPU_PPC_603R, |
3251 |
.pvr_mask = 0xFFFFFFFF,
|
3252 |
.insns_flags = PPC_INSNS_603, |
3253 |
.flags = PPC_FLAGS_603, |
3254 |
.msr_mask = 0x000000000007FF73ULL,
|
3255 |
}, |
3256 |
#if defined (TODO)
|
3257 |
/* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
|
3258 |
{ |
3259 |
.name = "G2",
|
3260 |
.pvr = CPU_PPC_G2, |
3261 |
.pvr_mask = 0xFFFF0000,
|
3262 |
.insns_flags = PPC_INSNS_G2, |
3263 |
.flags = PPC_FLAGS_G2, |
3264 |
.msr_mask = 0x000000000006FFF2ULL,
|
3265 |
}, |
3266 |
{ |
3267 |
.name = "G2h4",
|
3268 |
.pvr = CPU_PPC_G2H4, |
3269 |
.pvr_mask = 0xFFFF0000,
|
3270 |
.insns_flags = PPC_INSNS_G2, |
3271 |
.flags = PPC_FLAGS_G2, |
3272 |
.msr_mask = 0x000000000006FFF2ULL,
|
3273 |
}, |
3274 |
{ |
3275 |
.name = "G2gp",
|
3276 |
.pvr = CPU_PPC_G2gp, |
3277 |
.pvr_mask = 0xFFFF0000,
|
3278 |
.insns_flags = PPC_INSNS_G2, |
3279 |
.flags = PPC_FLAGS_G2, |
3280 |
.msr_mask = 0x000000000006FFF2ULL,
|
3281 |
}, |
3282 |
{ |
3283 |
.name = "G2ls",
|
3284 |
.pvr = CPU_PPC_G2ls, |
3285 |
.pvr_mask = 0xFFFF0000,
|
3286 |
.insns_flags = PPC_INSNS_G2, |
3287 |
.flags = PPC_FLAGS_G2, |
3288 |
.msr_mask = 0x000000000006FFF2ULL,
|
3289 |
}, |
3290 |
{ /* Same as G2, with LE mode support */
|
3291 |
.name = "G2le",
|
3292 |
.pvr = CPU_PPC_G2LE, |
3293 |
.pvr_mask = 0xFFFF0000,
|
3294 |
.insns_flags = PPC_INSNS_G2, |
3295 |
.flags = PPC_FLAGS_G2, |
3296 |
.msr_mask = 0x000000000007FFF3ULL,
|
3297 |
}, |
3298 |
{ |
3299 |
.name = "G2legp",
|
3300 |
.pvr = CPU_PPC_G2LEgp, |
3301 |
.pvr_mask = 0xFFFF0000,
|
3302 |
.insns_flags = PPC_INSNS_G2, |
3303 |
.flags = PPC_FLAGS_G2, |
3304 |
.msr_mask = 0x000000000007FFF3ULL,
|
3305 |
}, |
3306 |
{ |
3307 |
.name = "G2lels",
|
3308 |
.pvr = CPU_PPC_G2LEls, |
3309 |
.pvr_mask = 0xFFFF0000,
|
3310 |
.insns_flags = PPC_INSNS_G2, |
3311 |
.flags = PPC_FLAGS_G2, |
3312 |
.msr_mask = 0x000000000007FFF3ULL,
|
3313 |
}, |
3314 |
#endif
|
3315 |
/* PowerPC 604 */
|
3316 |
{ |
3317 |
.name = "604",
|
3318 |
.pvr = CPU_PPC_604, |
3319 |
.pvr_mask = 0xFFFFFFFF,
|
3320 |
.insns_flags = PPC_INSNS_604, |
3321 |
.flags = PPC_FLAGS_604, |
3322 |
.msr_mask = 0x000000000005FF77ULL,
|
3323 |
}, |
3324 |
/* PowerPC 604e */
|
3325 |
{ |
3326 |
.name = "604e",
|
3327 |
.pvr = CPU_PPC_604E, |
3328 |
.pvr_mask = 0xFFFFFFFF,
|
3329 |
.insns_flags = PPC_INSNS_604, |
3330 |
.flags = PPC_FLAGS_604, |
3331 |
.msr_mask = 0x000000000005FF77ULL,
|
3332 |
}, |
3333 |
/* PowerPC 604r */
|
3334 |
{ |
3335 |
.name = "604r",
|
3336 |
.pvr = CPU_PPC_604R, |
3337 |
.pvr_mask = 0xFFFFFFFF,
|
3338 |
.insns_flags = PPC_INSNS_604, |
3339 |
.flags = PPC_FLAGS_604, |
3340 |
.msr_mask = 0x000000000005FF77ULL,
|
3341 |
}, |
3342 |
/* generic G3 */
|
3343 |
{ |
3344 |
.name = "G3",
|
3345 |
.pvr = CPU_PPC_74x, |
3346 |
.pvr_mask = 0xFFFFFFFF,
|
3347 |
.insns_flags = PPC_INSNS_7x0, |
3348 |
.flags = PPC_FLAGS_7x0, |
3349 |
.msr_mask = 0x000000000007FF77ULL,
|
3350 |
}, |
3351 |
/* MPC740 (G3) */
|
3352 |
{ |
3353 |
.name = "740",
|
3354 |
.pvr = CPU_PPC_74x, |
3355 |
.pvr_mask = 0xFFFFFFFF,
|
3356 |
.insns_flags = PPC_INSNS_7x0, |
3357 |
.flags = PPC_FLAGS_7x0, |
3358 |
.msr_mask = 0x000000000007FF77ULL,
|
3359 |
}, |
3360 |
{ |
3361 |
.name = "Arthur",
|
3362 |
.pvr = CPU_PPC_74x, |
3363 |
.pvr_mask = 0xFFFFFFFF,
|
3364 |
.insns_flags = PPC_INSNS_7x0, |
3365 |
.flags = PPC_FLAGS_7x0, |
3366 |
.msr_mask = 0x000000000007FF77ULL,
|
3367 |
}, |
3368 |
#if defined (TODO)
|
3369 |
/* MPC745 (G3) */
|
3370 |
{ |
3371 |
.name = "745",
|
3372 |
.pvr = CPU_PPC_74x, |
3373 |
.pvr_mask = 0xFFFFF000,
|
3374 |
.insns_flags = PPC_INSNS_7x5, |
3375 |
.flags = PPC_FLAGS_7x5, |
3376 |
.msr_mask = 0x000000000007FF77ULL,
|
3377 |
}, |
3378 |
{ |
3379 |
.name = "Goldfinger",
|
3380 |
.pvr = CPU_PPC_74x, |
3381 |
.pvr_mask = 0xFFFFF000,
|
3382 |
.insns_flags = PPC_INSNS_7x5, |
3383 |
.flags = PPC_FLAGS_7x5, |
3384 |
.msr_mask = 0x000000000007FF77ULL,
|
3385 |
}, |
3386 |
#endif
|
3387 |
/* MPC750 (G3) */
|
3388 |
{ |
3389 |
.name = "750",
|
3390 |
.pvr = CPU_PPC_74x, |
3391 |
.pvr_mask = 0xFFFFFFFF,
|
3392 |
.insns_flags = PPC_INSNS_7x0, |
3393 |
.flags = PPC_FLAGS_7x0, |
3394 |
.msr_mask = 0x000000000007FF77ULL,
|
3395 |
}, |
3396 |
#if defined (TODO)
|
3397 |
/* MPC755 (G3) */
|
3398 |
{ |
3399 |
.name = "755",
|
3400 |
.pvr = CPU_PPC_755, |
3401 |
.pvr_mask = 0xFFFFF000,
|
3402 |
.insns_flags = PPC_INSNS_7x5, |
3403 |
.flags = PPC_FLAGS_7x5, |
3404 |
.msr_mask = 0x000000000007FF77ULL,
|
3405 |
}, |
3406 |
#endif
|
3407 |
/* MPC740P (G3) */
|
3408 |
{ |
3409 |
.name = "740p",
|
3410 |
.pvr = CPU_PPC_74xP, |
3411 |
.pvr_mask = 0xFFFFFFFF,
|
3412 |
.insns_flags = PPC_INSNS_7x0, |
3413 |
.flags = PPC_FLAGS_7x0, |
3414 |
.msr_mask = 0x000000000007FF77ULL,
|
3415 |
}, |
3416 |
{ |
3417 |
.name = "Conan/Doyle",
|
3418 |
.pvr = CPU_PPC_74xP, |
3419 |
.pvr_mask = 0xFFFFFFFF,
|
3420 |
.insns_flags = PPC_INSNS_7x0, |
3421 |
.flags = PPC_FLAGS_7x0, |
3422 |
.msr_mask = 0x000000000007FF77ULL,
|
3423 |
}, |
3424 |
#if defined (TODO)
|
3425 |
/* MPC745P (G3) */
|
3426 |
{ |
3427 |
.name = "745p",
|
3428 |
.pvr = CPU_PPC_74xP, |
3429 |
.pvr_mask = 0xFFFFF000,
|
3430 |
.insns_flags = PPC_INSNS_7x5, |
3431 |
.flags = PPC_FLAGS_7x5, |
3432 |
.msr_mask = 0x000000000007FF77ULL,
|
3433 |
}, |
3434 |
#endif
|
3435 |
/* MPC750P (G3) */
|
3436 |
{ |
3437 |
.name = "750p",
|
3438 |
.pvr = CPU_PPC_74xP, |
3439 |
.pvr_mask = 0xFFFFFFFF,
|
3440 |
.insns_flags = PPC_INSNS_7x0, |
3441 |
.flags = PPC_FLAGS_7x0, |
3442 |
.msr_mask = 0x000000000007FF77ULL,
|
3443 |
}, |
3444 |
#if defined (TODO)
|
3445 |
/* MPC755P (G3) */
|
3446 |
{ |
3447 |
.name = "755p",
|
3448 |
.pvr = CPU_PPC_74xP, |
3449 |
.pvr_mask = 0xFFFFF000,
|
3450 |
.insns_flags = PPC_INSNS_7x5, |
3451 |
.flags = PPC_FLAGS_7x5, |
3452 |
.msr_mask = 0x000000000007FF77ULL,
|
3453 |
}, |
3454 |
#endif
|
3455 |
/* IBM 750CXe (G3 embedded) */
|
3456 |
{ |
3457 |
.name = "750cxe",
|
3458 |
.pvr = CPU_PPC_750CXE, |
3459 |
.pvr_mask = 0xFFFFFFFF,
|
3460 |
.insns_flags = PPC_INSNS_7x0, |
3461 |
.flags = PPC_FLAGS_7x0, |
3462 |
.msr_mask = 0x000000000007FF77ULL,
|
3463 |
}, |
3464 |
/* IBM 750FX (G3 embedded) */
|
3465 |
{ |
3466 |
.name = "750fx",
|
3467 |
.pvr = CPU_PPC_750FX, |
3468 |
.pvr_mask = 0xFFFFFFFF,
|
3469 |
.insns_flags = PPC_INSNS_7x0, |
3470 |
.flags = PPC_FLAGS_7x0, |
3471 |
.msr_mask = 0x000000000007FF77ULL,
|
3472 |
}, |
3473 |
/* IBM 750GX (G3 embedded) */
|
3474 |
{ |
3475 |
.name = "750gx",
|
3476 |
.pvr = CPU_PPC_750GX, |
3477 |
.pvr_mask = 0xFFFFFFFF,
|
3478 |
.insns_flags = PPC_INSNS_7x0, |
3479 |
.flags = PPC_FLAGS_7x0, |
3480 |
.msr_mask = 0x000000000007FF77ULL,
|
3481 |
}, |
3482 |
#if defined (TODO)
|
3483 |
/* generic G4 */
|
3484 |
{ |
3485 |
.name = "G4",
|
3486 |
.pvr = CPU_PPC_7400, |
3487 |
.pvr_mask = 0xFFFF0000,
|
3488 |
.insns_flags = PPC_INSNS_74xx, |
3489 |
.flags = PPC_FLAGS_74xx, |
3490 |
.msr_mask = 0x000000000205FF77ULL,
|
3491 |
}, |
3492 |
#endif
|
3493 |
#if defined (TODO)
|
3494 |
/* PowerPC 7400 (G4) */
|
3495 |
{ |
3496 |
.name = "7400",
|
3497 |
.pvr = CPU_PPC_7400, |
3498 |
.pvr_mask = 0xFFFF0000,
|
3499 |
.insns_flags = PPC_INSNS_74xx, |
3500 |
.flags = PPC_FLAGS_74xx, |
3501 |
.msr_mask = 0x000000000205FF77ULL,
|
3502 |
}, |
3503 |
{ |
3504 |
.name = "Max",
|
3505 |
.pvr = CPU_PPC_7400, |
3506 |
.pvr_mask = 0xFFFF0000,
|
3507 |
.insns_flags = PPC_INSNS_74xx, |
3508 |
.flags = PPC_FLAGS_74xx, |
3509 |
.msr_mask = 0x000000000205FF77ULL,
|
3510 |
}, |
3511 |
#endif
|
3512 |
#if defined (TODO)
|
3513 |
/* PowerPC 7410 (G4) */
|
3514 |
{ |
3515 |
.name = "7410",
|
3516 |
.pvr = CPU_PPC_7410, |
3517 |
.pvr_mask = 0xFFFF0000,
|
3518 |
.insns_flags = PPC_INSNS_74xx, |
3519 |
.flags = PPC_FLAGS_74xx, |
3520 |
.msr_mask = 0x000000000205FF77ULL,
|
3521 |
}, |
3522 |
{ |
3523 |
.name = "Nitro",
|
3524 |
.pvr = CPU_PPC_7410, |
3525 |
.pvr_mask = 0xFFFF0000,
|
3526 |
.insns_flags = PPC_INSNS_74xx, |
3527 |
.flags = PPC_FLAGS_74xx, |
3528 |
.msr_mask = 0x000000000205FF77ULL,
|
3529 |
}, |
3530 |
#endif
|
3531 |
/* XXX: 7441 */
|
3532 |
/* XXX: 7445 */
|
3533 |
/* XXX: 7447 */
|
3534 |
/* XXX: 7447A */
|
3535 |
#if defined (TODO)
|
3536 |
/* PowerPC 7450 (G4) */
|
3537 |
{ |
3538 |
.name = "7450",
|
3539 |
.pvr = CPU_PPC_7450, |
3540 |
.pvr_mask = 0xFFFF0000,
|
3541 |
.insns_flags = PPC_INSNS_74xx, |
3542 |
.flags = PPC_FLAGS_74xx, |
3543 |
.msr_mask = 0x000000000205FF77ULL,
|
3544 |
}, |
3545 |
{ |
3546 |
.name = "Vger",
|
3547 |
.pvr = CPU_PPC_7450, |
3548 |
.pvr_mask = 0xFFFF0000,
|
3549 |
.insns_flags = PPC_INSNS_74xx, |
3550 |
.flags = PPC_FLAGS_74xx, |
3551 |
.msr_mask = 0x000000000205FF77ULL,
|
3552 |
}, |
3553 |
#endif
|
3554 |
/* XXX: 7451 */
|
3555 |
#if defined (TODO)
|
3556 |
/* PowerPC 7455 (G4) */
|
3557 |
{ |
3558 |
.name = "7455",
|
3559 |
.pvr = CPU_PPC_7455, |
3560 |
.pvr_mask = 0xFFFF0000,
|
3561 |
.insns_flags = PPC_INSNS_74xx, |
3562 |
.flags = PPC_FLAGS_74xx, |
3563 |
.msr_mask = 0x000000000205FF77ULL,
|
3564 |
}, |
3565 |
{ |
3566 |
.name = "Apollo 6",
|
3567 |
.pvr = CPU_PPC_7455, |
3568 |
.pvr_mask = 0xFFFF0000,
|
3569 |
.insns_flags = PPC_INSNS_74xx, |
3570 |
.flags = PPC_FLAGS_74xx, |
3571 |
.msr_mask = 0x000000000205FF77ULL,
|
3572 |
}, |
3573 |
#endif
|
3574 |
#if defined (TODO)
|
3575 |
/* PowerPC 7457 (G4) */
|
3576 |
{ |
3577 |
.name = "7457",
|
3578 |
.pvr = CPU_PPC_7457, |
3579 |
.pvr_mask = 0xFFFF0000,
|
3580 |
.insns_flags = PPC_INSNS_74xx, |
3581 |
.flags = PPC_FLAGS_74xx, |
3582 |
.msr_mask = 0x000000000205FF77ULL,
|
3583 |
}, |
3584 |
{ |
3585 |
.name = "Apollo 7",
|
3586 |
.pvr = CPU_PPC_7457, |
3587 |
.pvr_mask = 0xFFFF0000,
|
3588 |
.insns_flags = PPC_INSNS_74xx, |
3589 |
.flags = PPC_FLAGS_74xx, |
3590 |
.msr_mask = 0x000000000205FF77ULL,
|
3591 |
}, |
3592 |
#endif
|
3593 |
#if defined (TODO)
|
3594 |
/* PowerPC 7457A (G4) */
|
3595 |
{ |
3596 |
.name = "7457A",
|
3597 |
.pvr = CPU_PPC_7457A, |
3598 |
.pvr_mask = 0xFFFF0000,
|
3599 |
.insns_flags = PPC_INSNS_74xx, |
3600 |
.flags = PPC_FLAGS_74xx, |
3601 |
.msr_mask = 0x000000000205FF77ULL,
|
3602 |
}, |
3603 |
{ |
3604 |
.name = "Apollo 7 PM",
|
3605 |
.pvr = CPU_PPC_7457A, |
3606 |
.pvr_mask = 0xFFFF0000,
|
3607 |
.insns_flags = PPC_INSNS_74xx, |
3608 |
.flags = PPC_FLAGS_74xx, |
3609 |
.msr_mask = 0x000000000205FF77ULL,
|
3610 |
}, |
3611 |
#endif
|
3612 |
/* 64 bits PowerPC */
|
3613 |
#if defined (TARGET_PPC64)
|
3614 |
#if defined (TODO)
|
3615 |
/* PowerPC 620 */
|
3616 |
{ |
3617 |
.name = "620",
|
3618 |
.pvr = CPU_PPC_620, |
3619 |
.pvr_mask = 0xFFFF0000,
|
3620 |
.insns_flags = PPC_INSNS_620, |
3621 |
.flags = PPC_FLAGS_620, |
3622 |
.msr_mask = 0x800000000005FF73ULL,
|
3623 |
}, |
3624 |
#endif
|
3625 |
#if defined (TODO)
|
3626 |
/* PowerPC 630 (POWER3) */
|
3627 |
{ |
3628 |
.name = "630",
|
3629 |
.pvr = CPU_PPC_630, |
3630 |
.pvr_mask = 0xFFFF0000,
|
3631 |
.insns_flags = PPC_INSNS_630, |
3632 |
.flags = PPC_FLAGS_630, |
3633 |
.msr_mask = xxx, |
3634 |
} |
3635 |
{ |
3636 |
.name = "POWER3",
|
3637 |
.pvr = CPU_PPC_630, |
3638 |
.pvr_mask = 0xFFFF0000,
|
3639 |
.insns_flags = PPC_INSNS_630, |
3640 |
.flags = PPC_FLAGS_630, |
3641 |
.msr_mask = xxx, |
3642 |
} |
3643 |
#endif
|
3644 |
#if defined (TODO)
|
3645 |
/* PowerPC 631 (Power 3+)*/
|
3646 |
{ |
3647 |
.name = "631",
|
3648 |
.pvr = CPU_PPC_631, |
3649 |
.pvr_mask = 0xFFFF0000,
|
3650 |
.insns_flags = PPC_INSNS_631, |
3651 |
.flags = PPC_FLAGS_631, |
3652 |
.msr_mask = xxx, |
3653 |
}, |
3654 |
{ |
3655 |
.name = "POWER3+",
|
3656 |
.pvr = CPU_PPC_631, |
3657 |
.pvr_mask = 0xFFFF0000,
|
3658 |
.insns_flags = PPC_INSNS_631, |
3659 |
.flags = PPC_FLAGS_631, |
3660 |
.msr_mask = xxx, |
3661 |
}, |
3662 |
#endif
|
3663 |
#if defined (TODO)
|
3664 |
/* POWER4 */
|
3665 |
{ |
3666 |
.name = "POWER4",
|
3667 |
.pvr = CPU_PPC_POWER4, |
3668 |
.pvr_mask = 0xFFFF0000,
|
3669 |
.insns_flags = PPC_INSNS_POWER4, |
3670 |
.flags = PPC_FLAGS_POWER4, |
3671 |
.msr_mask = xxx, |
3672 |
}, |
3673 |
#endif
|
3674 |
#if defined (TODO)
|
3675 |
/* POWER4p */
|
3676 |
{ |
3677 |
.name = "POWER4+",
|
3678 |
.pvr = CPU_PPC_POWER4P, |
3679 |
.pvr_mask = 0xFFFF0000,
|
3680 |
.insns_flags = PPC_INSNS_POWER4, |
3681 |
.flags = PPC_FLAGS_POWER4, |
3682 |
.msr_mask = xxx, |
3683 |
}, |
3684 |
#endif
|
3685 |
#if defined (TODO)
|
3686 |
/* POWER5 */
|
3687 |
{ |
3688 |
.name = "POWER5",
|
3689 |
.pvr = CPU_PPC_POWER5, |
3690 |
.pvr_mask = 0xFFFF0000,
|
3691 |
.insns_flags = PPC_INSNS_POWER5, |
3692 |
.flags = PPC_FLAGS_POWER5, |
3693 |
.msr_mask = xxx, |
3694 |
}, |
3695 |
#endif
|
3696 |
#if defined (TODO)
|
3697 |
/* POWER5+ */
|
3698 |
{ |
3699 |
.name = "POWER5+",
|
3700 |
.pvr = CPU_PPC_POWER5P, |
3701 |
.pvr_mask = 0xFFFF0000,
|
3702 |
.insns_flags = PPC_INSNS_POWER5, |
3703 |
.flags = PPC_FLAGS_POWER5, |
3704 |
.msr_mask = xxx, |
3705 |
}, |
3706 |
#endif
|
3707 |
#if defined (TODO)
|
3708 |
/* PowerPC 970 */
|
3709 |
{ |
3710 |
.name = "970",
|
3711 |
.pvr = CPU_PPC_970, |
3712 |
.pvr_mask = 0xFFFF0000,
|
3713 |
.insns_flags = PPC_INSNS_970, |
3714 |
.flags = PPC_FLAGS_970, |
3715 |
.msr_mask = 0x900000000204FF36ULL,
|
3716 |
}, |
3717 |
#endif
|
3718 |
#if defined (TODO)
|
3719 |
/* PowerPC 970FX (G5) */
|
3720 |
{ |
3721 |
.name = "970fx",
|
3722 |
.pvr = CPU_PPC_970FX, |
3723 |
.pvr_mask = 0xFFFF0000,
|
3724 |
.insns_flags = PPC_INSNS_970FX, |
3725 |
.flags = PPC_FLAGS_970FX, |
3726 |
.msr_mask = 0x800000000204FF36ULL,
|
3727 |
}, |
3728 |
#endif
|
3729 |
#if defined (TODO)
|
3730 |
/* RS64 (Apache/A35) */
|
3731 |
/* This one seems to support the whole POWER2 instruction set
|
3732 |
* and the PowerPC 64 one.
|
3733 |
*/
|
3734 |
{ |
3735 |
.name = "RS64",
|
3736 |
.pvr = CPU_PPC_RS64, |
3737 |
.pvr_mask = 0xFFFF0000,
|
3738 |
.insns_flags = PPC_INSNS_RS64, |
3739 |
.flags = PPC_FLAGS_RS64, |
3740 |
.msr_mask = xxx, |
3741 |
}, |
3742 |
{ |
3743 |
.name = "Apache",
|
3744 |
.pvr = CPU_PPC_RS64, |
3745 |
.pvr_mask = 0xFFFF0000,
|
3746 |
.insns_flags = PPC_INSNS_RS64, |
3747 |
.flags = PPC_FLAGS_RS64, |
3748 |
.msr_mask = xxx, |
3749 |
}, |
3750 |
{ |
3751 |
.name = "A35",
|
3752 |
.pvr = CPU_PPC_RS64, |
3753 |
.pvr_mask = 0xFFFF0000,
|
3754 |
.insns_flags = PPC_INSNS_RS64, |
3755 |
.flags = PPC_FLAGS_RS64, |
3756 |
.msr_mask = xxx, |
3757 |
}, |
3758 |
#endif
|
3759 |
#if defined (TODO)
|
3760 |
/* RS64-II (NorthStar/A50) */
|
3761 |
{ |
3762 |
.name = "RS64-II",
|
3763 |
.pvr = CPU_PPC_RS64II, |
3764 |
.pvr_mask = 0xFFFF0000,
|
3765 |
.insns_flags = PPC_INSNS_RS64, |
3766 |
.flags = PPC_FLAGS_RS64, |
3767 |
.msr_mask = xxx, |
3768 |
}, |
3769 |
{ |
3770 |
.name = "NortStar",
|
3771 |
.pvr = CPU_PPC_RS64II, |
3772 |
.pvr_mask = 0xFFFF0000,
|
3773 |
.insns_flags = PPC_INSNS_RS64, |
3774 |
.flags = PPC_FLAGS_RS64, |
3775 |
.msr_mask = xxx, |
3776 |
}, |
3777 |
{ |
3778 |
.name = "A50",
|
3779 |
.pvr = CPU_PPC_RS64II, |
3780 |
.pvr_mask = 0xFFFF0000,
|
3781 |
.insns_flags = PPC_INSNS_RS64, |
3782 |
.flags = PPC_FLAGS_RS64, |
3783 |
.msr_mask = xxx, |
3784 |
}, |
3785 |
#endif
|
3786 |
#if defined (TODO)
|
3787 |
/* RS64-III (Pulsar) */
|
3788 |
{ |
3789 |
.name = "RS64-III",
|
3790 |
.pvr = CPU_PPC_RS64III, |
3791 |
.pvr_mask = 0xFFFF0000,
|
3792 |
.insns_flags = PPC_INSNS_RS64, |
3793 |
.flags = PPC_FLAGS_RS64, |
3794 |
.msr_mask = xxx, |
3795 |
}, |
3796 |
{ |
3797 |
.name = "Pulsar",
|
3798 |
.pvr = CPU_PPC_RS64III, |
3799 |
.pvr_mask = 0xFFFF0000,
|
3800 |
.insns_flags = PPC_INSNS_RS64, |
3801 |
.flags = PPC_FLAGS_RS64, |
3802 |
.msr_mask = xxx, |
3803 |
}, |
3804 |
#endif
|
3805 |
#if defined (TODO)
|
3806 |
/* RS64-IV (IceStar/IStar/SStar) */
|
3807 |
{ |
3808 |
.name = "RS64-IV",
|
3809 |
.pvr = CPU_PPC_RS64IV, |
3810 |
.pvr_mask = 0xFFFF0000,
|
3811 |
.insns_flags = PPC_INSNS_RS64, |
3812 |
.flags = PPC_FLAGS_RS64, |
3813 |
.msr_mask = xxx, |
3814 |
}, |
3815 |
{ |
3816 |
.name = "IceStar",
|
3817 |
.pvr = CPU_PPC_RS64IV, |
3818 |
.pvr_mask = 0xFFFF0000,
|
3819 |
.insns_flags = PPC_INSNS_RS64, |
3820 |
.flags = PPC_FLAGS_RS64, |
3821 |
.msr_mask = xxx, |
3822 |
}, |
3823 |
{ |
3824 |
.name = "IStar",
|
3825 |
.pvr = CPU_PPC_RS64IV, |
3826 |
.pvr_mask = 0xFFFF0000,
|
3827 |
.insns_flags = PPC_INSNS_RS64, |
3828 |
.flags = PPC_FLAGS_RS64, |
3829 |
.msr_mask = xxx, |
3830 |
}, |
3831 |
{ |
3832 |
.name = "SStar",
|
3833 |
.pvr = CPU_PPC_RS64IV, |
3834 |
.pvr_mask = 0xFFFF0000,
|
3835 |
.insns_flags = PPC_INSNS_RS64, |
3836 |
.flags = PPC_FLAGS_RS64, |
3837 |
.msr_mask = xxx, |
3838 |
}, |
3839 |
#endif
|
3840 |
/* POWER */
|
3841 |
#if defined (TODO)
|
3842 |
/* Original POWER */
|
3843 |
{ |
3844 |
.name = "POWER",
|
3845 |
.pvr = CPU_POWER, |
3846 |
.pvr_mask = 0xFFFF0000,
|
3847 |
.insns_flags = PPC_INSNS_POWER, |
3848 |
.flags = PPC_FLAGS_POWER, |
3849 |
.msr_mask = xxx, |
3850 |
}, |
3851 |
#endif
|
3852 |
#endif /* defined (TARGET_PPC64) */ |
3853 |
#if defined (TODO)
|
3854 |
/* POWER2 */
|
3855 |
{ |
3856 |
.name = "POWER2",
|
3857 |
.pvr = CPU_POWER2, |
3858 |
.pvr_mask = 0xFFFF0000,
|
3859 |
.insns_flags = PPC_INSNS_POWER, |
3860 |
.flags = PPC_FLAGS_POWER, |
3861 |
.msr_mask = xxx, |
3862 |
}, |
3863 |
#endif
|
3864 |
/* Generic PowerPCs */
|
3865 |
#if defined (TODO)
|
3866 |
{ |
3867 |
.name = "ppc64",
|
3868 |
.pvr = CPU_PPC_970, |
3869 |
.pvr_mask = 0xFFFF0000,
|
3870 |
.insns_flags = PPC_INSNS_PPC64, |
3871 |
.flags = PPC_FLAGS_PPC64, |
3872 |
.msr_mask = 0xA00000000204FF36ULL,
|
3873 |
}, |
3874 |
#endif
|
3875 |
{ |
3876 |
.name = "ppc32",
|
3877 |
.pvr = CPU_PPC_604, |
3878 |
.pvr_mask = 0xFFFFFFFF,
|
3879 |
.insns_flags = PPC_INSNS_PPC32, |
3880 |
.flags = PPC_FLAGS_PPC32, |
3881 |
.msr_mask = 0x000000000005FF77ULL,
|
3882 |
}, |
3883 |
/* Fallback */
|
3884 |
{ |
3885 |
.name = "ppc",
|
3886 |
.pvr = CPU_PPC_604, |
3887 |
.pvr_mask = 0xFFFFFFFF,
|
3888 |
.insns_flags = PPC_INSNS_PPC32, |
3889 |
.flags = PPC_FLAGS_PPC32, |
3890 |
.msr_mask = 0x000000000005FF77ULL,
|
3891 |
}, |
3892 |
}; |
3893 |
|
3894 |
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def) |
3895 |
{ |
3896 |
int i, ret;
|
3897 |
|
3898 |
ret = -1;
|
3899 |
*def = NULL;
|
3900 |
for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) { |
3901 |
if (strcasecmp(name, ppc_defs[i].name) == 0) { |
3902 |
*def = &ppc_defs[i]; |
3903 |
ret = 0;
|
3904 |
break;
|
3905 |
} |
3906 |
} |
3907 |
|
3908 |
return ret;
|
3909 |
} |
3910 |
|
3911 |
int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
|
3912 |
{ |
3913 |
int i, ret;
|
3914 |
|
3915 |
ret = -1;
|
3916 |
*def = NULL;
|
3917 |
for (i = 0; ppc_defs[i].name != NULL; i++) { |
3918 |
if ((pvr & ppc_defs[i].pvr_mask) ==
|
3919 |
(ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) { |
3920 |
*def = &ppc_defs[i]; |
3921 |
ret = 0;
|
3922 |
break;
|
3923 |
} |
3924 |
} |
3925 |
|
3926 |
return ret;
|
3927 |
} |
3928 |
|
3929 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
3930 |
{ |
3931 |
int i;
|
3932 |
|
3933 |
for (i = 0; ; i++) { |
3934 |
(*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
|
3935 |
ppc_defs[i].name, |
3936 |
ppc_defs[i].pvr, ppc_defs[i].pvr_mask); |
3937 |
if (strcmp(ppc_defs[i].name, "ppc") == 0) |
3938 |
break;
|
3939 |
} |
3940 |
} |