Revision 3b4fefd6
| b/target-alpha/helper.h | ||
|---|---|---|
| 110 | 110 |
DEF_HELPER_2(stq_phys, void, i64, i64) |
| 111 | 111 |
DEF_HELPER_2(stl_c_phys, i64, i64, i64) |
| 112 | 112 |
DEF_HELPER_2(stq_c_phys, i64, i64, i64) |
| 113 |
|
|
| 114 |
DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void) |
|
| 115 |
DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64) |
|
| 113 | 116 |
#endif |
| 114 | 117 |
|
| 115 | 118 |
#include "def-helper.h" |
| b/target-alpha/op_helper.c | ||
|---|---|---|
| 1205 | 1205 |
swap_shadow_regs(env); |
| 1206 | 1206 |
} |
| 1207 | 1207 |
} |
| 1208 |
|
|
| 1209 |
void helper_tbia(void) |
|
| 1210 |
{
|
|
| 1211 |
tlb_flush(env, 1); |
|
| 1212 |
} |
|
| 1213 |
|
|
| 1214 |
void helper_tbis(uint64_t p) |
|
| 1215 |
{
|
|
| 1216 |
tlb_flush_page(env, p); |
|
| 1217 |
} |
|
| 1208 | 1218 |
#endif |
| 1209 | 1219 |
|
| 1210 | 1220 |
/*****************************************************************************/ |
| ... | ... | |
| 1335 | 1345 |
} |
| 1336 | 1346 |
env = saved_env; |
| 1337 | 1347 |
} |
| 1338 |
|
|
| 1339 | 1348 |
#endif |
| b/target-alpha/translate.c | ||
|---|---|---|
| 1621 | 1621 |
static void gen_mtpr(int rb, int regno) |
| 1622 | 1622 |
{
|
| 1623 | 1623 |
TCGv tmp; |
| 1624 |
int data; |
|
| 1625 | 1624 |
|
| 1626 | 1625 |
if (rb == 31) {
|
| 1627 | 1626 |
tmp = tcg_const_i64(0); |
| ... | ... | |
| 1629 | 1628 |
tmp = cpu_ir[rb]; |
| 1630 | 1629 |
} |
| 1631 | 1630 |
|
| 1632 |
/* The basic registers are data only, and unknown registers |
|
| 1633 |
are read-zero, write-ignore. */ |
|
| 1634 |
data = cpu_pr_data(regno); |
|
| 1635 |
if (data != 0) {
|
|
| 1636 |
if (data & PR_BYTE) {
|
|
| 1637 |
tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); |
|
| 1638 |
} else if (data & PR_LONG) {
|
|
| 1639 |
tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); |
|
| 1640 |
} else {
|
|
| 1641 |
tcg_gen_st_i64(tmp, cpu_env, data); |
|
| 1631 |
/* These two register numbers perform a TLB cache flush. Thankfully we |
|
| 1632 |
can only do this inside PALmode, which means that the current basic |
|
| 1633 |
block cannot be affected by the change in mappings. */ |
|
| 1634 |
if (regno == 255) {
|
|
| 1635 |
/* TBIA */ |
|
| 1636 |
gen_helper_tbia(); |
|
| 1637 |
} else if (regno == 254) {
|
|
| 1638 |
/* TBIS */ |
|
| 1639 |
gen_helper_tbis(tmp); |
|
| 1640 |
} else {
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|
| 1641 |
/* The basic registers are data only, and unknown registers |
|
| 1642 |
are read-zero, write-ignore. */ |
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| 1643 |
int data = cpu_pr_data(regno); |
|
| 1644 |
if (data != 0) {
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| 1645 |
if (data & PR_BYTE) {
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| 1646 |
tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); |
|
| 1647 |
} else if (data & PR_LONG) {
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| 1648 |
tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); |
|
| 1649 |
} else {
|
|
| 1650 |
tcg_gen_st_i64(tmp, cpu_env, data); |
|
| 1651 |
} |
|
| 1642 | 1652 |
} |
| 1643 | 1653 |
} |
| 1644 | 1654 |
|
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