Revision 3b4fefd6 target-alpha/translate.c

b/target-alpha/translate.c
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static void gen_mtpr(int rb, int regno)
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{
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    TCGv tmp;
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    int data;
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    if (rb == 31) {
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        tmp = tcg_const_i64(0);
......
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        tmp = cpu_ir[rb];
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    }
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    /* The basic registers are data only, and unknown registers
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       are read-zero, write-ignore.  */
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    data = cpu_pr_data(regno);
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    if (data != 0) {
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        if (data & PR_BYTE) {
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            tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE);
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        } else if (data & PR_LONG) {
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            tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG);
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        } else {
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            tcg_gen_st_i64(tmp, cpu_env, data);
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    /* These two register numbers perform a TLB cache flush.  Thankfully we
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       can only do this inside PALmode, which means that the current basic
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       block cannot be affected by the change in mappings.  */
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    if (regno == 255) {
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        /* TBIA */
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        gen_helper_tbia();
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    } else if (regno == 254) {
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        /* TBIS */
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        gen_helper_tbis(tmp);
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    } else {
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        /* The basic registers are data only, and unknown registers
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           are read-zero, write-ignore.  */
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        int data = cpu_pr_data(regno);
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        if (data != 0) {
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            if (data & PR_BYTE) {
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                tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE);
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            } else if (data & PR_LONG) {
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                tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG);
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            } else {
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                tcg_gen_st_i64(tmp, cpu_env, data);
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            }
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        }
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    }
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