root / tcg / x86_64 / tcg-target.c @ 3b6dac34
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"%rax",
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"%rcx",
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"%rdx",
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"%rbx",
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"%rsp",
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"%rbp",
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"%rsi",
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"%rdi",
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"%r8",
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"%r9",
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"%r10",
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"%r11",
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"%r12",
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"%r13",
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"%r14",
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"%r15",
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}; |
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#endif
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_RBP, |
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TCG_REG_RBX, |
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TCG_REG_R12, |
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TCG_REG_R13, |
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R10, |
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TCG_REG_R11, |
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TCG_REG_R9, |
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TCG_REG_R8, |
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TCG_REG_RCX, |
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TCG_REG_RDX, |
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TCG_REG_RSI, |
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TCG_REG_RDI, |
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TCG_REG_RAX, |
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}; |
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|
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static const int tcg_target_call_iarg_regs[6] = { |
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TCG_REG_RDI, |
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TCG_REG_RSI, |
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TCG_REG_RDX, |
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TCG_REG_RCX, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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}; |
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|
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static const int tcg_target_call_oarg_regs[2] = { |
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TCG_REG_RAX, |
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TCG_REG_RDX |
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}; |
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static uint8_t *tb_ret_addr;
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|
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static void patch_reloc(uint8_t *code_ptr, int type, |
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tcg_target_long value, tcg_target_long addend) |
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{ |
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value += addend; |
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switch(type) {
|
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case R_X86_64_32:
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if (value != (uint32_t)value)
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tcg_abort(); |
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*(uint32_t *)code_ptr = value; |
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break;
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case R_X86_64_32S:
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if (value != (int32_t)value)
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tcg_abort(); |
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*(uint32_t *)code_ptr = value; |
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break;
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case R_386_PC32:
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value -= (long)code_ptr;
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if (value != (int32_t)value)
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tcg_abort(); |
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*(uint32_t *)code_ptr = value; |
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break;
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default:
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tcg_abort(); |
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} |
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} |
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|
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags) |
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{ |
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return 6; |
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} |
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|
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
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{ |
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const char *ct_str; |
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|
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ct_str = *pct_str; |
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switch(ct_str[0]) { |
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case 'a': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX); |
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break;
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case 'b': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX); |
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break;
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case 'c': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX); |
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break;
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case 'd': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX); |
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break;
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case 'S': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI); |
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break;
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case 'D': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI); |
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break;
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case 'q': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xf); |
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break;
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case 'r': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffff); |
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break;
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case 'L': /* qemu_ld/st constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffff); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI); |
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break;
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case 'e': |
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ct->ct |= TCG_CT_CONST_S32; |
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break;
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case 'Z': |
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ct->ct |= TCG_CT_CONST_U32; |
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break;
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default:
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return -1; |
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} |
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ct_str++; |
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*pct_str = ct_str; |
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return 0; |
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} |
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val, |
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const TCGArgConstraint *arg_ct)
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{ |
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int ct;
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ct = arg_ct->ct; |
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if (ct & TCG_CT_CONST)
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return 1; |
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else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) |
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return 1; |
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else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) |
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return 1; |
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else
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return 0; |
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} |
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#define ARITH_ADD 0 |
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#define ARITH_OR 1 |
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#define ARITH_ADC 2 |
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#define ARITH_SBB 3 |
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#define ARITH_AND 4 |
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#define ARITH_SUB 5 |
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#define ARITH_XOR 6 |
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#define ARITH_CMP 7 |
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|
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#define SHIFT_ROL 0 |
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#define SHIFT_ROR 1 |
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#define SHIFT_SHL 4 |
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#define SHIFT_SHR 5 |
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#define SHIFT_SAR 7 |
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#define JCC_JMP (-1) |
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#define JCC_JO 0x0 |
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#define JCC_JNO 0x1 |
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#define JCC_JB 0x2 |
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#define JCC_JAE 0x3 |
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#define JCC_JE 0x4 |
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#define JCC_JNE 0x5 |
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#define JCC_JBE 0x6 |
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#define JCC_JA 0x7 |
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#define JCC_JS 0x8 |
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#define JCC_JNS 0x9 |
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#define JCC_JP 0xa |
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#define JCC_JNP 0xb |
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#define JCC_JL 0xc |
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#define JCC_JGE 0xd |
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#define JCC_JLE 0xe |
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#define JCC_JG 0xf |
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|
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#define P_EXT 0x100 /* 0x0f opcode prefix */ |
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#define P_REXW 0x200 /* set rex.w = 1 */ |
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#define P_REXB_R 0x400 /* REG field as byte register */ |
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#define P_REXB_RM 0x800 /* R/M field as byte register */ |
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static const uint8_t tcg_cond_to_jcc[10] = { |
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[TCG_COND_EQ] = JCC_JE, |
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[TCG_COND_NE] = JCC_JNE, |
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[TCG_COND_LT] = JCC_JL, |
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[TCG_COND_GE] = JCC_JGE, |
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[TCG_COND_LE] = JCC_JLE, |
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[TCG_COND_GT] = JCC_JG, |
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[TCG_COND_LTU] = JCC_JB, |
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[TCG_COND_GEU] = JCC_JAE, |
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[TCG_COND_LEU] = JCC_JBE, |
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[TCG_COND_GTU] = JCC_JA, |
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}; |
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static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) |
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{ |
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int rex = 0; |
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rex |= (opc & P_REXW) >> 6; /* REX.W */ |
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rex |= (r & 8) >> 1; /* REX.R */ |
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rex |= (x & 8) >> 2; /* REX.X */ |
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rex |= (rm & 8) >> 3; /* REX.B */ |
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|
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/* P_REXB_{R,RM} indicates that the given register is the low byte.
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For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
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as otherwise the encoding indicates %[abcd]h. Note that the values
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that are ORed in merely indicate that the REX byte must be present;
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those bits get discarded in output. */
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rex |= opc & (r >= 4 ? P_REXB_R : 0); |
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rex |= opc & (rm >= 4 ? P_REXB_RM : 0); |
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if (rex) {
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tcg_out8(s, (uint8_t)(rex | 0x40));
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} |
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if (opc & P_EXT) {
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tcg_out8(s, 0x0f);
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} |
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tcg_out8(s, opc & 0xff);
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} |
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|
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static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) |
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{ |
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tcg_out_opc(s, opc, r, rm, 0);
|
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tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7)); |
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} |
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|
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/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
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static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, |
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tcg_target_long offset) |
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{ |
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if (rm < 0) { |
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tcg_target_long val; |
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tcg_out_opc(s, opc, r, 0, 0); |
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val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1)); |
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if (val == (int32_t)val) {
|
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/* eip relative */
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tcg_out8(s, 0x05 | ((r & 7) << 3)); |
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tcg_out32(s, val); |
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} else if (offset == (int32_t)offset) { |
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tcg_out8(s, 0x04 | ((r & 7) << 3)); |
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tcg_out8(s, 0x25); /* sib */ |
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tcg_out32(s, offset); |
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} else {
|
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tcg_abort(); |
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} |
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} else if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
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tcg_out_opc(s, opc, r, rm, 0);
|
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if ((rm & 7) == TCG_REG_RSP) { |
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tcg_out8(s, 0x04 | ((r & 7) << 3)); |
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tcg_out8(s, 0x24);
|
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} else {
|
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tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7)); |
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} |
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} else if ((int8_t)offset == offset) { |
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tcg_out_opc(s, opc, r, rm, 0);
|
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if ((rm & 7) == TCG_REG_RSP) { |
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tcg_out8(s, 0x44 | ((r & 7) << 3)); |
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tcg_out8(s, 0x24);
|
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} else {
|
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tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7)); |
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} |
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tcg_out8(s, offset); |
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} else {
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tcg_out_opc(s, opc, r, rm, 0);
|
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if ((rm & 7) == TCG_REG_RSP) { |
309 |
tcg_out8(s, 0x84 | ((r & 7) << 3)); |
310 |
tcg_out8(s, 0x24);
|
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} else {
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tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7)); |
313 |
} |
314 |
tcg_out32(s, offset); |
315 |
} |
316 |
} |
317 |
|
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#if defined(CONFIG_SOFTMMU)
|
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/* XXX: incomplete. index must be different from ESP */
|
320 |
static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, |
321 |
int index, int shift, |
322 |
tcg_target_long offset) |
323 |
{ |
324 |
int mod;
|
325 |
if (rm == -1) |
326 |
tcg_abort(); |
327 |
if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
328 |
mod = 0;
|
329 |
} else if (offset == (int8_t)offset) { |
330 |
mod = 0x40;
|
331 |
} else if (offset == (int32_t)offset) { |
332 |
mod = 0x80;
|
333 |
} else {
|
334 |
tcg_abort(); |
335 |
} |
336 |
if (index == -1) { |
337 |
tcg_out_opc(s, opc, r, rm, 0);
|
338 |
if ((rm & 7) == TCG_REG_RSP) { |
339 |
tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
340 |
tcg_out8(s, 0x04 | (rm & 7)); |
341 |
} else {
|
342 |
tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7)); |
343 |
} |
344 |
} else {
|
345 |
tcg_out_opc(s, opc, r, rm, index); |
346 |
tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
347 |
tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7)); |
348 |
} |
349 |
if (mod == 0x40) { |
350 |
tcg_out8(s, offset); |
351 |
} else if (mod == 0x80) { |
352 |
tcg_out32(s, offset); |
353 |
} |
354 |
} |
355 |
#endif
|
356 |
|
357 |
static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg) |
358 |
{ |
359 |
int rexw = (type == TCG_TYPE_I64 ? P_REXW : 0); |
360 |
tcg_out_modrm(s, 0x8b | rexw, ret, arg);
|
361 |
} |
362 |
|
363 |
static inline void tcg_out_movi(TCGContext *s, TCGType type, |
364 |
int ret, tcg_target_long arg)
|
365 |
{ |
366 |
if (arg == 0) { |
367 |
tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */ |
368 |
} else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { |
369 |
tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0); |
370 |
tcg_out32(s, arg); |
371 |
} else if (arg == (int32_t)arg) { |
372 |
tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret); |
373 |
tcg_out32(s, arg); |
374 |
} else {
|
375 |
tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0); |
376 |
tcg_out32(s, arg); |
377 |
tcg_out32(s, arg >> 32);
|
378 |
} |
379 |
} |
380 |
|
381 |
static void tcg_out_goto(TCGContext *s, int call, uint8_t *target) |
382 |
{ |
383 |
int32_t disp; |
384 |
|
385 |
disp = target - s->code_ptr - 5;
|
386 |
if (disp == (target - s->code_ptr - 5)) { |
387 |
tcg_out8(s, call ? 0xe8 : 0xe9); |
388 |
tcg_out32(s, disp); |
389 |
} else {
|
390 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (tcg_target_long) target); |
391 |
tcg_out_modrm(s, 0xff, call ? 2 : 4, TCG_REG_R10); |
392 |
} |
393 |
} |
394 |
|
395 |
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
396 |
int arg1, tcg_target_long arg2)
|
397 |
{ |
398 |
if (type == TCG_TYPE_I32)
|
399 |
tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */ |
400 |
else
|
401 |
tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */ |
402 |
} |
403 |
|
404 |
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
405 |
int arg1, tcg_target_long arg2)
|
406 |
{ |
407 |
if (type == TCG_TYPE_I32)
|
408 |
tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */ |
409 |
else
|
410 |
tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */ |
411 |
} |
412 |
|
413 |
static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val) |
414 |
{ |
415 |
if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) { |
416 |
/* inc */
|
417 |
tcg_out_modrm(s, 0xff, 0, r0); |
418 |
} else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) { |
419 |
/* dec */
|
420 |
tcg_out_modrm(s, 0xff, 1, r0); |
421 |
} else if (val == (int8_t)val) { |
422 |
tcg_out_modrm(s, 0x83, c, r0);
|
423 |
tcg_out8(s, val); |
424 |
} else if (c == ARITH_AND && val == 0xffu) { |
425 |
/* movzbl */
|
426 |
tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, r0, r0);
|
427 |
} else if (c == ARITH_AND && val == 0xffffu) { |
428 |
/* movzwl */
|
429 |
tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
|
430 |
} else {
|
431 |
tcg_out_modrm(s, 0x81, c, r0);
|
432 |
tcg_out32(s, val); |
433 |
} |
434 |
} |
435 |
|
436 |
static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) |
437 |
{ |
438 |
if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) { |
439 |
/* inc */
|
440 |
tcg_out_modrm(s, 0xff | P_REXW, 0, r0); |
441 |
} else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) { |
442 |
/* dec */
|
443 |
tcg_out_modrm(s, 0xff | P_REXW, 1, r0); |
444 |
} else if (c == ARITH_AND && val == 0xffffffffu) { |
445 |
/* 32-bit mov zero extends */
|
446 |
tcg_out_modrm(s, 0x8b, r0, r0);
|
447 |
} else if (c == ARITH_AND && val == (uint32_t)val) { |
448 |
/* AND with no high bits set can use a 32-bit operation. */
|
449 |
tgen_arithi32(s, c, r0, (uint32_t)val); |
450 |
} else if (val == (int8_t)val) { |
451 |
tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
|
452 |
tcg_out8(s, val); |
453 |
} else if (val == (int32_t)val) { |
454 |
tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
|
455 |
tcg_out32(s, val); |
456 |
} else {
|
457 |
tcg_abort(); |
458 |
} |
459 |
} |
460 |
|
461 |
static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
462 |
{ |
463 |
if (val != 0) |
464 |
tgen_arithi64(s, ARITH_ADD, reg, val); |
465 |
} |
466 |
|
467 |
static void tcg_out_jxx(TCGContext *s, int opc, int label_index) |
468 |
{ |
469 |
int32_t val, val1; |
470 |
TCGLabel *l = &s->labels[label_index]; |
471 |
|
472 |
if (l->has_value) {
|
473 |
val = l->u.value - (tcg_target_long)s->code_ptr; |
474 |
val1 = val - 2;
|
475 |
if ((int8_t)val1 == val1) {
|
476 |
if (opc == -1) |
477 |
tcg_out8(s, 0xeb);
|
478 |
else
|
479 |
tcg_out8(s, 0x70 + opc);
|
480 |
tcg_out8(s, val1); |
481 |
} else {
|
482 |
if (opc == -1) { |
483 |
tcg_out8(s, 0xe9);
|
484 |
tcg_out32(s, val - 5);
|
485 |
} else {
|
486 |
tcg_out8(s, 0x0f);
|
487 |
tcg_out8(s, 0x80 + opc);
|
488 |
tcg_out32(s, val - 6);
|
489 |
} |
490 |
} |
491 |
} else {
|
492 |
if (opc == -1) { |
493 |
tcg_out8(s, 0xe9);
|
494 |
} else {
|
495 |
tcg_out8(s, 0x0f);
|
496 |
tcg_out8(s, 0x80 + opc);
|
497 |
} |
498 |
tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
|
499 |
s->code_ptr += 4;
|
500 |
} |
501 |
} |
502 |
|
503 |
static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, |
504 |
int const_arg2, int rexw) |
505 |
{ |
506 |
if (const_arg2) {
|
507 |
if (arg2 == 0) { |
508 |
/* test r, r */
|
509 |
tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
|
510 |
} else {
|
511 |
if (rexw) {
|
512 |
tgen_arithi64(s, ARITH_CMP, arg1, arg2); |
513 |
} else {
|
514 |
tgen_arithi32(s, ARITH_CMP, arg1, arg2); |
515 |
} |
516 |
} |
517 |
} else {
|
518 |
tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1); |
519 |
} |
520 |
} |
521 |
|
522 |
static void tcg_out_brcond(TCGContext *s, TCGCond cond, |
523 |
TCGArg arg1, TCGArg arg2, int const_arg2,
|
524 |
int label_index, int rexw) |
525 |
{ |
526 |
tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); |
527 |
tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
528 |
} |
529 |
|
530 |
static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg dest, |
531 |
TCGArg arg1, TCGArg arg2, int const_arg2, int rexw) |
532 |
{ |
533 |
tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); |
534 |
/* setcc */
|
535 |
tcg_out_modrm(s, 0x90 | tcg_cond_to_jcc[cond] | P_EXT | P_REXB_RM, 0, dest); |
536 |
tgen_arithi32(s, ARITH_AND, dest, 0xff);
|
537 |
} |
538 |
|
539 |
#if defined(CONFIG_SOFTMMU)
|
540 |
|
541 |
#include "../../softmmu_defs.h" |
542 |
|
543 |
static void *qemu_ld_helpers[4] = { |
544 |
__ldb_mmu, |
545 |
__ldw_mmu, |
546 |
__ldl_mmu, |
547 |
__ldq_mmu, |
548 |
}; |
549 |
|
550 |
static void *qemu_st_helpers[4] = { |
551 |
__stb_mmu, |
552 |
__stw_mmu, |
553 |
__stl_mmu, |
554 |
__stq_mmu, |
555 |
}; |
556 |
#endif
|
557 |
|
558 |
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
559 |
int opc)
|
560 |
{ |
561 |
int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
562 |
int32_t offset; |
563 |
#if defined(CONFIG_SOFTMMU)
|
564 |
uint8_t *label1_ptr, *label2_ptr; |
565 |
#endif
|
566 |
|
567 |
data_reg = *args++; |
568 |
addr_reg = *args++; |
569 |
mem_index = *args; |
570 |
s_bits = opc & 3;
|
571 |
|
572 |
r0 = TCG_REG_RDI; |
573 |
r1 = TCG_REG_RSI; |
574 |
|
575 |
#if TARGET_LONG_BITS == 32 |
576 |
rexw = 0;
|
577 |
#else
|
578 |
rexw = P_REXW; |
579 |
#endif
|
580 |
#if defined(CONFIG_SOFTMMU)
|
581 |
tcg_out_mov(s, TCG_TYPE_TL, r1, addr_reg); |
582 |
tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg); |
583 |
|
584 |
tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
585 |
tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
586 |
|
587 |
tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
588 |
tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
589 |
|
590 |
tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
591 |
tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
592 |
|
593 |
/* lea offset(r1, env), r1 */
|
594 |
tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
595 |
offsetof(CPUState, tlb_table[mem_index][0].addr_read));
|
596 |
|
597 |
/* cmp 0(r1), r0 */
|
598 |
tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
599 |
|
600 |
tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg); |
601 |
|
602 |
/* je label1 */
|
603 |
tcg_out8(s, 0x70 + JCC_JE);
|
604 |
label1_ptr = s->code_ptr; |
605 |
s->code_ptr++; |
606 |
|
607 |
/* XXX: move that code at the end of the TB */
|
608 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index); |
609 |
tcg_out_goto(s, 1, qemu_ld_helpers[s_bits]);
|
610 |
|
611 |
switch(opc) {
|
612 |
case 0 | 4: |
613 |
/* movsbq */
|
614 |
tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
615 |
break;
|
616 |
case 1 | 4: |
617 |
/* movswq */
|
618 |
tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
619 |
break;
|
620 |
case 2 | 4: |
621 |
/* movslq */
|
622 |
tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
|
623 |
break;
|
624 |
case 0: |
625 |
/* movzbq */
|
626 |
tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
627 |
break;
|
628 |
case 1: |
629 |
/* movzwq */
|
630 |
tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
631 |
break;
|
632 |
case 2: |
633 |
default:
|
634 |
tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_RAX); |
635 |
break;
|
636 |
case 3: |
637 |
tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); |
638 |
break;
|
639 |
} |
640 |
|
641 |
/* jmp label2 */
|
642 |
tcg_out8(s, 0xeb);
|
643 |
label2_ptr = s->code_ptr; |
644 |
s->code_ptr++; |
645 |
|
646 |
/* label1: */
|
647 |
*label1_ptr = s->code_ptr - label1_ptr - 1;
|
648 |
|
649 |
/* add x(r1), r0 */
|
650 |
tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
651 |
offsetof(CPUTLBEntry, addr_read)); |
652 |
offset = 0;
|
653 |
#else
|
654 |
if (GUEST_BASE == (int32_t)GUEST_BASE) {
|
655 |
r0 = addr_reg; |
656 |
offset = GUEST_BASE; |
657 |
} else {
|
658 |
offset = 0;
|
659 |
/* movq $GUEST_BASE, r0 */
|
660 |
tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
661 |
tcg_out32(s, GUEST_BASE); |
662 |
tcg_out32(s, GUEST_BASE >> 32);
|
663 |
/* addq addr_reg, r0 */
|
664 |
tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
|
665 |
} |
666 |
#endif
|
667 |
|
668 |
#ifdef TARGET_WORDS_BIGENDIAN
|
669 |
bswap = 1;
|
670 |
#else
|
671 |
bswap = 0;
|
672 |
#endif
|
673 |
switch(opc) {
|
674 |
case 0: |
675 |
/* movzbl */
|
676 |
tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
|
677 |
break;
|
678 |
case 0 | 4: |
679 |
/* movsbX */
|
680 |
tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
|
681 |
break;
|
682 |
case 1: |
683 |
/* movzwl */
|
684 |
tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
|
685 |
if (bswap) {
|
686 |
/* rolw $8, data_reg */
|
687 |
tcg_out8(s, 0x66);
|
688 |
tcg_out_modrm(s, 0xc1, 0, data_reg); |
689 |
tcg_out8(s, 8);
|
690 |
} |
691 |
break;
|
692 |
case 1 | 4: |
693 |
if (bswap) {
|
694 |
/* movzwl */
|
695 |
tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
|
696 |
/* rolw $8, data_reg */
|
697 |
tcg_out8(s, 0x66);
|
698 |
tcg_out_modrm(s, 0xc1, 0, data_reg); |
699 |
tcg_out8(s, 8);
|
700 |
|
701 |
/* movswX data_reg, data_reg */
|
702 |
tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
|
703 |
} else {
|
704 |
/* movswX */
|
705 |
tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
|
706 |
} |
707 |
break;
|
708 |
case 2: |
709 |
/* movl (r0), data_reg */
|
710 |
tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
|
711 |
if (bswap) {
|
712 |
/* bswap */
|
713 |
tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
714 |
} |
715 |
break;
|
716 |
case 2 | 4: |
717 |
if (bswap) {
|
718 |
/* movl (r0), data_reg */
|
719 |
tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
|
720 |
/* bswap */
|
721 |
tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
722 |
/* movslq */
|
723 |
tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
|
724 |
} else {
|
725 |
/* movslq */
|
726 |
tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
|
727 |
} |
728 |
break;
|
729 |
case 3: |
730 |
/* movq (r0), data_reg */
|
731 |
tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
|
732 |
if (bswap) {
|
733 |
/* bswap */
|
734 |
tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0); |
735 |
} |
736 |
break;
|
737 |
default:
|
738 |
tcg_abort(); |
739 |
} |
740 |
|
741 |
#if defined(CONFIG_SOFTMMU)
|
742 |
/* label2: */
|
743 |
*label2_ptr = s->code_ptr - label2_ptr - 1;
|
744 |
#endif
|
745 |
} |
746 |
|
747 |
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
748 |
int opc)
|
749 |
{ |
750 |
int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
751 |
int32_t offset; |
752 |
#if defined(CONFIG_SOFTMMU)
|
753 |
uint8_t *label1_ptr, *label2_ptr; |
754 |
#endif
|
755 |
|
756 |
data_reg = *args++; |
757 |
addr_reg = *args++; |
758 |
mem_index = *args; |
759 |
|
760 |
s_bits = opc; |
761 |
|
762 |
r0 = TCG_REG_RDI; |
763 |
r1 = TCG_REG_RSI; |
764 |
|
765 |
#if TARGET_LONG_BITS == 32 |
766 |
rexw = 0;
|
767 |
#else
|
768 |
rexw = P_REXW; |
769 |
#endif
|
770 |
#if defined(CONFIG_SOFTMMU)
|
771 |
tcg_out_mov(s, TCG_TYPE_TL, r1, addr_reg); |
772 |
tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg); |
773 |
|
774 |
tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
775 |
tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
776 |
|
777 |
tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
778 |
tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
779 |
|
780 |
tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
781 |
tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
782 |
|
783 |
/* lea offset(r1, env), r1 */
|
784 |
tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
785 |
offsetof(CPUState, tlb_table[mem_index][0].addr_write));
|
786 |
|
787 |
/* cmp 0(r1), r0 */
|
788 |
tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
789 |
|
790 |
tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg); |
791 |
|
792 |
/* je label1 */
|
793 |
tcg_out8(s, 0x70 + JCC_JE);
|
794 |
label1_ptr = s->code_ptr; |
795 |
s->code_ptr++; |
796 |
|
797 |
/* XXX: move that code at the end of the TB */
|
798 |
switch(opc) {
|
799 |
case 0: |
800 |
/* movzbl */
|
801 |
tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, TCG_REG_RSI, data_reg);
|
802 |
break;
|
803 |
case 1: |
804 |
/* movzwl */
|
805 |
tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
|
806 |
break;
|
807 |
case 2: |
808 |
tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_RSI, data_reg); |
809 |
break;
|
810 |
default:
|
811 |
case 3: |
812 |
tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_RSI, data_reg); |
813 |
break;
|
814 |
} |
815 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index); |
816 |
tcg_out_goto(s, 1, qemu_st_helpers[s_bits]);
|
817 |
|
818 |
/* jmp label2 */
|
819 |
tcg_out8(s, 0xeb);
|
820 |
label2_ptr = s->code_ptr; |
821 |
s->code_ptr++; |
822 |
|
823 |
/* label1: */
|
824 |
*label1_ptr = s->code_ptr - label1_ptr - 1;
|
825 |
|
826 |
/* add x(r1), r0 */
|
827 |
tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
828 |
offsetof(CPUTLBEntry, addr_write)); |
829 |
offset = 0;
|
830 |
#else
|
831 |
if (GUEST_BASE == (int32_t)GUEST_BASE) {
|
832 |
r0 = addr_reg; |
833 |
offset = GUEST_BASE; |
834 |
} else {
|
835 |
offset = 0;
|
836 |
/* movq $GUEST_BASE, r0 */
|
837 |
tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
838 |
tcg_out32(s, GUEST_BASE); |
839 |
tcg_out32(s, GUEST_BASE >> 32);
|
840 |
/* addq addr_reg, r0 */
|
841 |
tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
|
842 |
} |
843 |
#endif
|
844 |
|
845 |
#ifdef TARGET_WORDS_BIGENDIAN
|
846 |
bswap = 1;
|
847 |
#else
|
848 |
bswap = 0;
|
849 |
#endif
|
850 |
switch(opc) {
|
851 |
case 0: |
852 |
/* movb */
|
853 |
tcg_out_modrm_offset(s, 0x88 | P_REXB_R, data_reg, r0, offset);
|
854 |
break;
|
855 |
case 1: |
856 |
if (bswap) {
|
857 |
tcg_out_mov(s, TCG_TYPE_I32, r1, data_reg); |
858 |
tcg_out8(s, 0x66); /* rolw $8, %ecx */ |
859 |
tcg_out_modrm(s, 0xc1, 0, r1); |
860 |
tcg_out8(s, 8);
|
861 |
data_reg = r1; |
862 |
} |
863 |
/* movw */
|
864 |
tcg_out8(s, 0x66);
|
865 |
tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
|
866 |
break;
|
867 |
case 2: |
868 |
if (bswap) {
|
869 |
tcg_out_mov(s, TCG_TYPE_I32, r1, data_reg); |
870 |
/* bswap data_reg */
|
871 |
tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0); |
872 |
data_reg = r1; |
873 |
} |
874 |
/* movl */
|
875 |
tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
|
876 |
break;
|
877 |
case 3: |
878 |
if (bswap) {
|
879 |
tcg_out_mov(s, TCG_TYPE_I64, r1, data_reg); |
880 |
/* bswap data_reg */
|
881 |
tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0); |
882 |
data_reg = r1; |
883 |
} |
884 |
/* movq */
|
885 |
tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
|
886 |
break;
|
887 |
default:
|
888 |
tcg_abort(); |
889 |
} |
890 |
|
891 |
#if defined(CONFIG_SOFTMMU)
|
892 |
/* label2: */
|
893 |
*label2_ptr = s->code_ptr - label2_ptr - 1;
|
894 |
#endif
|
895 |
} |
896 |
|
897 |
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, |
898 |
const int *const_args) |
899 |
{ |
900 |
int c;
|
901 |
|
902 |
switch(opc) {
|
903 |
case INDEX_op_exit_tb:
|
904 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
|
905 |
tcg_out_goto(s, 0, tb_ret_addr);
|
906 |
break;
|
907 |
case INDEX_op_goto_tb:
|
908 |
if (s->tb_jmp_offset) {
|
909 |
/* direct jump method */
|
910 |
tcg_out8(s, 0xe9); /* jmp im */ |
911 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
912 |
tcg_out32(s, 0);
|
913 |
} else {
|
914 |
/* indirect jump method */
|
915 |
/* jmp Ev */
|
916 |
tcg_out_modrm_offset(s, 0xff, 4, -1, |
917 |
(tcg_target_long)(s->tb_next + |
918 |
args[0]));
|
919 |
} |
920 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
921 |
break;
|
922 |
case INDEX_op_call:
|
923 |
if (const_args[0]) { |
924 |
tcg_out_goto(s, 1, (void *) args[0]); |
925 |
} else {
|
926 |
tcg_out_modrm(s, 0xff, 2, args[0]); |
927 |
} |
928 |
break;
|
929 |
case INDEX_op_jmp:
|
930 |
if (const_args[0]) { |
931 |
tcg_out_goto(s, 0, (void *) args[0]); |
932 |
} else {
|
933 |
tcg_out_modrm(s, 0xff, 4, args[0]); |
934 |
} |
935 |
break;
|
936 |
case INDEX_op_br:
|
937 |
tcg_out_jxx(s, JCC_JMP, args[0]);
|
938 |
break;
|
939 |
case INDEX_op_movi_i32:
|
940 |
tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
941 |
break;
|
942 |
case INDEX_op_movi_i64:
|
943 |
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
944 |
break;
|
945 |
case INDEX_op_ld8u_i32:
|
946 |
case INDEX_op_ld8u_i64:
|
947 |
/* movzbl */
|
948 |
tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); |
949 |
break;
|
950 |
case INDEX_op_ld8s_i32:
|
951 |
/* movsbl */
|
952 |
tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); |
953 |
break;
|
954 |
case INDEX_op_ld8s_i64:
|
955 |
/* movsbq */
|
956 |
tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]); |
957 |
break;
|
958 |
case INDEX_op_ld16u_i32:
|
959 |
case INDEX_op_ld16u_i64:
|
960 |
/* movzwl */
|
961 |
tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); |
962 |
break;
|
963 |
case INDEX_op_ld16s_i32:
|
964 |
/* movswl */
|
965 |
tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); |
966 |
break;
|
967 |
case INDEX_op_ld16s_i64:
|
968 |
/* movswq */
|
969 |
tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]); |
970 |
break;
|
971 |
case INDEX_op_ld_i32:
|
972 |
case INDEX_op_ld32u_i64:
|
973 |
/* movl */
|
974 |
tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]); |
975 |
break;
|
976 |
case INDEX_op_ld32s_i64:
|
977 |
/* movslq */
|
978 |
tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]); |
979 |
break;
|
980 |
case INDEX_op_ld_i64:
|
981 |
/* movq */
|
982 |
tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]); |
983 |
break;
|
984 |
|
985 |
case INDEX_op_st8_i32:
|
986 |
case INDEX_op_st8_i64:
|
987 |
/* movb */
|
988 |
tcg_out_modrm_offset(s, 0x88 | P_REXB_R, args[0], args[1], args[2]); |
989 |
break;
|
990 |
case INDEX_op_st16_i32:
|
991 |
case INDEX_op_st16_i64:
|
992 |
/* movw */
|
993 |
tcg_out8(s, 0x66);
|
994 |
tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
995 |
break;
|
996 |
case INDEX_op_st_i32:
|
997 |
case INDEX_op_st32_i64:
|
998 |
/* movl */
|
999 |
tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
1000 |
break;
|
1001 |
case INDEX_op_st_i64:
|
1002 |
/* movq */
|
1003 |
tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]); |
1004 |
break;
|
1005 |
|
1006 |
case INDEX_op_sub_i32:
|
1007 |
c = ARITH_SUB; |
1008 |
goto gen_arith32;
|
1009 |
case INDEX_op_and_i32:
|
1010 |
c = ARITH_AND; |
1011 |
goto gen_arith32;
|
1012 |
case INDEX_op_or_i32:
|
1013 |
c = ARITH_OR; |
1014 |
goto gen_arith32;
|
1015 |
case INDEX_op_xor_i32:
|
1016 |
c = ARITH_XOR; |
1017 |
goto gen_arith32;
|
1018 |
case INDEX_op_add_i32:
|
1019 |
c = ARITH_ADD; |
1020 |
gen_arith32:
|
1021 |
if (const_args[2]) { |
1022 |
tgen_arithi32(s, c, args[0], args[2]); |
1023 |
} else {
|
1024 |
tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]); |
1025 |
} |
1026 |
break;
|
1027 |
|
1028 |
case INDEX_op_sub_i64:
|
1029 |
c = ARITH_SUB; |
1030 |
goto gen_arith64;
|
1031 |
case INDEX_op_and_i64:
|
1032 |
c = ARITH_AND; |
1033 |
goto gen_arith64;
|
1034 |
case INDEX_op_or_i64:
|
1035 |
c = ARITH_OR; |
1036 |
goto gen_arith64;
|
1037 |
case INDEX_op_xor_i64:
|
1038 |
c = ARITH_XOR; |
1039 |
goto gen_arith64;
|
1040 |
case INDEX_op_add_i64:
|
1041 |
c = ARITH_ADD; |
1042 |
gen_arith64:
|
1043 |
if (const_args[2]) { |
1044 |
tgen_arithi64(s, c, args[0], args[2]); |
1045 |
} else {
|
1046 |
tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]); |
1047 |
} |
1048 |
break;
|
1049 |
|
1050 |
case INDEX_op_mul_i32:
|
1051 |
if (const_args[2]) { |
1052 |
int32_t val; |
1053 |
val = args[2];
|
1054 |
if (val == (int8_t)val) {
|
1055 |
tcg_out_modrm(s, 0x6b, args[0], args[0]); |
1056 |
tcg_out8(s, val); |
1057 |
} else {
|
1058 |
tcg_out_modrm(s, 0x69, args[0], args[0]); |
1059 |
tcg_out32(s, val); |
1060 |
} |
1061 |
} else {
|
1062 |
tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]); |
1063 |
} |
1064 |
break;
|
1065 |
case INDEX_op_mul_i64:
|
1066 |
if (const_args[2]) { |
1067 |
int32_t val; |
1068 |
val = args[2];
|
1069 |
if (val == (int8_t)val) {
|
1070 |
tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]); |
1071 |
tcg_out8(s, val); |
1072 |
} else {
|
1073 |
tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]); |
1074 |
tcg_out32(s, val); |
1075 |
} |
1076 |
} else {
|
1077 |
tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]); |
1078 |
} |
1079 |
break;
|
1080 |
case INDEX_op_div2_i32:
|
1081 |
tcg_out_modrm(s, 0xf7, 7, args[4]); |
1082 |
break;
|
1083 |
case INDEX_op_divu2_i32:
|
1084 |
tcg_out_modrm(s, 0xf7, 6, args[4]); |
1085 |
break;
|
1086 |
case INDEX_op_div2_i64:
|
1087 |
tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]); |
1088 |
break;
|
1089 |
case INDEX_op_divu2_i64:
|
1090 |
tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]); |
1091 |
break;
|
1092 |
|
1093 |
case INDEX_op_shl_i32:
|
1094 |
c = SHIFT_SHL; |
1095 |
gen_shift32:
|
1096 |
if (const_args[2]) { |
1097 |
if (args[2] == 1) { |
1098 |
tcg_out_modrm(s, 0xd1, c, args[0]); |
1099 |
} else {
|
1100 |
tcg_out_modrm(s, 0xc1, c, args[0]); |
1101 |
tcg_out8(s, args[2]);
|
1102 |
} |
1103 |
} else {
|
1104 |
tcg_out_modrm(s, 0xd3, c, args[0]); |
1105 |
} |
1106 |
break;
|
1107 |
case INDEX_op_shr_i32:
|
1108 |
c = SHIFT_SHR; |
1109 |
goto gen_shift32;
|
1110 |
case INDEX_op_sar_i32:
|
1111 |
c = SHIFT_SAR; |
1112 |
goto gen_shift32;
|
1113 |
case INDEX_op_rotl_i32:
|
1114 |
c = SHIFT_ROL; |
1115 |
goto gen_shift32;
|
1116 |
case INDEX_op_rotr_i32:
|
1117 |
c = SHIFT_ROR; |
1118 |
goto gen_shift32;
|
1119 |
|
1120 |
case INDEX_op_shl_i64:
|
1121 |
c = SHIFT_SHL; |
1122 |
gen_shift64:
|
1123 |
if (const_args[2]) { |
1124 |
if (args[2] == 1) { |
1125 |
tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]); |
1126 |
} else {
|
1127 |
tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]); |
1128 |
tcg_out8(s, args[2]);
|
1129 |
} |
1130 |
} else {
|
1131 |
tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]); |
1132 |
} |
1133 |
break;
|
1134 |
case INDEX_op_shr_i64:
|
1135 |
c = SHIFT_SHR; |
1136 |
goto gen_shift64;
|
1137 |
case INDEX_op_sar_i64:
|
1138 |
c = SHIFT_SAR; |
1139 |
goto gen_shift64;
|
1140 |
case INDEX_op_rotl_i64:
|
1141 |
c = SHIFT_ROL; |
1142 |
goto gen_shift64;
|
1143 |
case INDEX_op_rotr_i64:
|
1144 |
c = SHIFT_ROR; |
1145 |
goto gen_shift64;
|
1146 |
|
1147 |
case INDEX_op_brcond_i32:
|
1148 |
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1149 |
args[3], 0); |
1150 |
break;
|
1151 |
case INDEX_op_brcond_i64:
|
1152 |
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1153 |
args[3], P_REXW);
|
1154 |
break;
|
1155 |
|
1156 |
case INDEX_op_bswap16_i32:
|
1157 |
case INDEX_op_bswap16_i64:
|
1158 |
tcg_out8(s, 0x66);
|
1159 |
tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]); |
1160 |
tcg_out8(s, 8);
|
1161 |
break;
|
1162 |
case INDEX_op_bswap32_i32:
|
1163 |
case INDEX_op_bswap32_i64:
|
1164 |
tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0); |
1165 |
break;
|
1166 |
case INDEX_op_bswap64_i64:
|
1167 |
tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0); |
1168 |
break;
|
1169 |
|
1170 |
case INDEX_op_neg_i32:
|
1171 |
tcg_out_modrm(s, 0xf7, 3, args[0]); |
1172 |
break;
|
1173 |
case INDEX_op_neg_i64:
|
1174 |
tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]); |
1175 |
break;
|
1176 |
|
1177 |
case INDEX_op_not_i32:
|
1178 |
tcg_out_modrm(s, 0xf7, 2, args[0]); |
1179 |
break;
|
1180 |
case INDEX_op_not_i64:
|
1181 |
tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]); |
1182 |
break;
|
1183 |
|
1184 |
case INDEX_op_ext8s_i32:
|
1185 |
tcg_out_modrm(s, 0xbe | P_EXT | P_REXB_RM, args[0], args[1]); |
1186 |
break;
|
1187 |
case INDEX_op_ext16s_i32:
|
1188 |
tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); |
1189 |
break;
|
1190 |
case INDEX_op_ext8s_i64:
|
1191 |
tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]); |
1192 |
break;
|
1193 |
case INDEX_op_ext16s_i64:
|
1194 |
tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]); |
1195 |
break;
|
1196 |
case INDEX_op_ext32s_i64:
|
1197 |
tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]); |
1198 |
break;
|
1199 |
case INDEX_op_ext8u_i32:
|
1200 |
case INDEX_op_ext8u_i64:
|
1201 |
tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, args[0], args[1]); |
1202 |
break;
|
1203 |
case INDEX_op_ext16u_i32:
|
1204 |
case INDEX_op_ext16u_i64:
|
1205 |
tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]); |
1206 |
break;
|
1207 |
case INDEX_op_ext32u_i64:
|
1208 |
tcg_out_modrm(s, 0x8b, args[0], args[1]); |
1209 |
break;
|
1210 |
|
1211 |
case INDEX_op_setcond_i32:
|
1212 |
tcg_out_setcond(s, args[3], args[0], args[1], args[2], |
1213 |
const_args[2], 0); |
1214 |
break;
|
1215 |
case INDEX_op_setcond_i64:
|
1216 |
tcg_out_setcond(s, args[3], args[0], args[1], args[2], |
1217 |
const_args[2], P_REXW);
|
1218 |
break;
|
1219 |
|
1220 |
case INDEX_op_qemu_ld8u:
|
1221 |
tcg_out_qemu_ld(s, args, 0);
|
1222 |
break;
|
1223 |
case INDEX_op_qemu_ld8s:
|
1224 |
tcg_out_qemu_ld(s, args, 0 | 4); |
1225 |
break;
|
1226 |
case INDEX_op_qemu_ld16u:
|
1227 |
tcg_out_qemu_ld(s, args, 1);
|
1228 |
break;
|
1229 |
case INDEX_op_qemu_ld16s:
|
1230 |
tcg_out_qemu_ld(s, args, 1 | 4); |
1231 |
break;
|
1232 |
case INDEX_op_qemu_ld32:
|
1233 |
case INDEX_op_qemu_ld32u:
|
1234 |
tcg_out_qemu_ld(s, args, 2);
|
1235 |
break;
|
1236 |
case INDEX_op_qemu_ld32s:
|
1237 |
tcg_out_qemu_ld(s, args, 2 | 4); |
1238 |
break;
|
1239 |
case INDEX_op_qemu_ld64:
|
1240 |
tcg_out_qemu_ld(s, args, 3);
|
1241 |
break;
|
1242 |
|
1243 |
case INDEX_op_qemu_st8:
|
1244 |
tcg_out_qemu_st(s, args, 0);
|
1245 |
break;
|
1246 |
case INDEX_op_qemu_st16:
|
1247 |
tcg_out_qemu_st(s, args, 1);
|
1248 |
break;
|
1249 |
case INDEX_op_qemu_st32:
|
1250 |
tcg_out_qemu_st(s, args, 2);
|
1251 |
break;
|
1252 |
case INDEX_op_qemu_st64:
|
1253 |
tcg_out_qemu_st(s, args, 3);
|
1254 |
break;
|
1255 |
|
1256 |
default:
|
1257 |
tcg_abort(); |
1258 |
} |
1259 |
} |
1260 |
|
1261 |
static int tcg_target_callee_save_regs[] = { |
1262 |
TCG_REG_RBP, |
1263 |
TCG_REG_RBX, |
1264 |
TCG_REG_R12, |
1265 |
TCG_REG_R13, |
1266 |
/* TCG_REG_R14, */ /* currently used for the global env, so no |
1267 |
need to save */
|
1268 |
TCG_REG_R15, |
1269 |
}; |
1270 |
|
1271 |
static inline void tcg_out_push(TCGContext *s, int reg) |
1272 |
{ |
1273 |
tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0); |
1274 |
} |
1275 |
|
1276 |
static inline void tcg_out_pop(TCGContext *s, int reg) |
1277 |
{ |
1278 |
tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0); |
1279 |
} |
1280 |
|
1281 |
/* Generate global QEMU prologue and epilogue code */
|
1282 |
void tcg_target_qemu_prologue(TCGContext *s)
|
1283 |
{ |
1284 |
int i, frame_size, push_size, stack_addend;
|
1285 |
|
1286 |
/* TB prologue */
|
1287 |
/* save all callee saved registers */
|
1288 |
for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { |
1289 |
tcg_out_push(s, tcg_target_callee_save_regs[i]); |
1290 |
|
1291 |
} |
1292 |
/* reserve some stack space */
|
1293 |
push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8; |
1294 |
frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE; |
1295 |
frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
1296 |
~(TCG_TARGET_STACK_ALIGN - 1);
|
1297 |
stack_addend = frame_size - push_size; |
1298 |
tcg_out_addi(s, TCG_REG_RSP, -stack_addend); |
1299 |
|
1300 |
tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */ |
1301 |
|
1302 |
/* TB epilogue */
|
1303 |
tb_ret_addr = s->code_ptr; |
1304 |
tcg_out_addi(s, TCG_REG_RSP, stack_addend); |
1305 |
for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { |
1306 |
tcg_out_pop(s, tcg_target_callee_save_regs[i]); |
1307 |
} |
1308 |
tcg_out8(s, 0xc3); /* ret */ |
1309 |
} |
1310 |
|
1311 |
static const TCGTargetOpDef x86_64_op_defs[] = { |
1312 |
{ INDEX_op_exit_tb, { } }, |
1313 |
{ INDEX_op_goto_tb, { } }, |
1314 |
{ INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1315 |
{ INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1316 |
{ INDEX_op_br, { } }, |
1317 |
|
1318 |
{ INDEX_op_mov_i32, { "r", "r" } }, |
1319 |
{ INDEX_op_movi_i32, { "r" } },
|
1320 |
{ INDEX_op_ld8u_i32, { "r", "r" } }, |
1321 |
{ INDEX_op_ld8s_i32, { "r", "r" } }, |
1322 |
{ INDEX_op_ld16u_i32, { "r", "r" } }, |
1323 |
{ INDEX_op_ld16s_i32, { "r", "r" } }, |
1324 |
{ INDEX_op_ld_i32, { "r", "r" } }, |
1325 |
{ INDEX_op_st8_i32, { "r", "r" } }, |
1326 |
{ INDEX_op_st16_i32, { "r", "r" } }, |
1327 |
{ INDEX_op_st_i32, { "r", "r" } }, |
1328 |
|
1329 |
{ INDEX_op_add_i32, { "r", "0", "ri" } }, |
1330 |
{ INDEX_op_mul_i32, { "r", "0", "ri" } }, |
1331 |
{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } }, |
1332 |
{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } }, |
1333 |
{ INDEX_op_sub_i32, { "r", "0", "ri" } }, |
1334 |
{ INDEX_op_and_i32, { "r", "0", "ri" } }, |
1335 |
{ INDEX_op_or_i32, { "r", "0", "ri" } }, |
1336 |
{ INDEX_op_xor_i32, { "r", "0", "ri" } }, |
1337 |
|
1338 |
{ INDEX_op_shl_i32, { "r", "0", "ci" } }, |
1339 |
{ INDEX_op_shr_i32, { "r", "0", "ci" } }, |
1340 |
{ INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1341 |
{ INDEX_op_rotl_i32, { "r", "0", "ci" } }, |
1342 |
{ INDEX_op_rotr_i32, { "r", "0", "ci" } }, |
1343 |
|
1344 |
{ INDEX_op_brcond_i32, { "r", "ri" } }, |
1345 |
|
1346 |
{ INDEX_op_mov_i64, { "r", "r" } }, |
1347 |
{ INDEX_op_movi_i64, { "r" } },
|
1348 |
{ INDEX_op_ld8u_i64, { "r", "r" } }, |
1349 |
{ INDEX_op_ld8s_i64, { "r", "r" } }, |
1350 |
{ INDEX_op_ld16u_i64, { "r", "r" } }, |
1351 |
{ INDEX_op_ld16s_i64, { "r", "r" } }, |
1352 |
{ INDEX_op_ld32u_i64, { "r", "r" } }, |
1353 |
{ INDEX_op_ld32s_i64, { "r", "r" } }, |
1354 |
{ INDEX_op_ld_i64, { "r", "r" } }, |
1355 |
{ INDEX_op_st8_i64, { "r", "r" } }, |
1356 |
{ INDEX_op_st16_i64, { "r", "r" } }, |
1357 |
{ INDEX_op_st32_i64, { "r", "r" } }, |
1358 |
{ INDEX_op_st_i64, { "r", "r" } }, |
1359 |
|
1360 |
{ INDEX_op_add_i64, { "r", "0", "re" } }, |
1361 |
{ INDEX_op_mul_i64, { "r", "0", "re" } }, |
1362 |
{ INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } }, |
1363 |
{ INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } }, |
1364 |
{ INDEX_op_sub_i64, { "r", "0", "re" } }, |
1365 |
{ INDEX_op_and_i64, { "r", "0", "reZ" } }, |
1366 |
{ INDEX_op_or_i64, { "r", "0", "re" } }, |
1367 |
{ INDEX_op_xor_i64, { "r", "0", "re" } }, |
1368 |
|
1369 |
{ INDEX_op_shl_i64, { "r", "0", "ci" } }, |
1370 |
{ INDEX_op_shr_i64, { "r", "0", "ci" } }, |
1371 |
{ INDEX_op_sar_i64, { "r", "0", "ci" } }, |
1372 |
{ INDEX_op_rotl_i64, { "r", "0", "ci" } }, |
1373 |
{ INDEX_op_rotr_i64, { "r", "0", "ci" } }, |
1374 |
|
1375 |
{ INDEX_op_brcond_i64, { "r", "re" } }, |
1376 |
|
1377 |
{ INDEX_op_bswap16_i32, { "r", "0" } }, |
1378 |
{ INDEX_op_bswap16_i64, { "r", "0" } }, |
1379 |
{ INDEX_op_bswap32_i32, { "r", "0" } }, |
1380 |
{ INDEX_op_bswap32_i64, { "r", "0" } }, |
1381 |
{ INDEX_op_bswap64_i64, { "r", "0" } }, |
1382 |
|
1383 |
{ INDEX_op_neg_i32, { "r", "0" } }, |
1384 |
{ INDEX_op_neg_i64, { "r", "0" } }, |
1385 |
|
1386 |
{ INDEX_op_not_i32, { "r", "0" } }, |
1387 |
{ INDEX_op_not_i64, { "r", "0" } }, |
1388 |
|
1389 |
{ INDEX_op_ext8s_i32, { "r", "r"} }, |
1390 |
{ INDEX_op_ext16s_i32, { "r", "r"} }, |
1391 |
{ INDEX_op_ext8s_i64, { "r", "r"} }, |
1392 |
{ INDEX_op_ext16s_i64, { "r", "r"} }, |
1393 |
{ INDEX_op_ext32s_i64, { "r", "r"} }, |
1394 |
{ INDEX_op_ext8u_i32, { "r", "r"} }, |
1395 |
{ INDEX_op_ext16u_i32, { "r", "r"} }, |
1396 |
{ INDEX_op_ext8u_i64, { "r", "r"} }, |
1397 |
{ INDEX_op_ext16u_i64, { "r", "r"} }, |
1398 |
{ INDEX_op_ext32u_i64, { "r", "r"} }, |
1399 |
|
1400 |
{ INDEX_op_setcond_i32, { "r", "r", "ri" } }, |
1401 |
{ INDEX_op_setcond_i64, { "r", "r", "re" } }, |
1402 |
|
1403 |
{ INDEX_op_qemu_ld8u, { "r", "L" } }, |
1404 |
{ INDEX_op_qemu_ld8s, { "r", "L" } }, |
1405 |
{ INDEX_op_qemu_ld16u, { "r", "L" } }, |
1406 |
{ INDEX_op_qemu_ld16s, { "r", "L" } }, |
1407 |
{ INDEX_op_qemu_ld32, { "r", "L" } }, |
1408 |
{ INDEX_op_qemu_ld32u, { "r", "L" } }, |
1409 |
{ INDEX_op_qemu_ld32s, { "r", "L" } }, |
1410 |
{ INDEX_op_qemu_ld64, { "r", "L" } }, |
1411 |
|
1412 |
{ INDEX_op_qemu_st8, { "L", "L" } }, |
1413 |
{ INDEX_op_qemu_st16, { "L", "L" } }, |
1414 |
{ INDEX_op_qemu_st32, { "L", "L" } }, |
1415 |
{ INDEX_op_qemu_st64, { "L", "L" } }, |
1416 |
|
1417 |
{ -1 },
|
1418 |
}; |
1419 |
|
1420 |
void tcg_target_init(TCGContext *s)
|
1421 |
{ |
1422 |
#if !defined(CONFIG_USER_ONLY)
|
1423 |
/* fail safe */
|
1424 |
if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) |
1425 |
tcg_abort(); |
1426 |
#endif
|
1427 |
|
1428 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); |
1429 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); |
1430 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1431 |
(1 << TCG_REG_RDI) |
|
1432 |
(1 << TCG_REG_RSI) |
|
1433 |
(1 << TCG_REG_RDX) |
|
1434 |
(1 << TCG_REG_RCX) |
|
1435 |
(1 << TCG_REG_R8) |
|
1436 |
(1 << TCG_REG_R9) |
|
1437 |
(1 << TCG_REG_RAX) |
|
1438 |
(1 << TCG_REG_R10) |
|
1439 |
(1 << TCG_REG_R11));
|
1440 |
|
1441 |
tcg_regset_clear(s->reserved_regs); |
1442 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP); |
1443 |
|
1444 |
tcg_add_target_add_op_defs(x86_64_op_defs); |
1445 |
} |