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hw: move headers to include/
Many of these should be cleaned up with proper qdev-/QOM-ification.Right now there are many catch-all headers in include/hw/ARCH dependingon cpu.h, and this makes it necessary to compile these files per-target.However, fixing this does not belong in these patches....
hw: include hw header files with full paths
Done with this script:
cd hwfor i in `find . -name '*.h' | sed 's/^..//'`; do echo '\,^#.*include.*["<]'$i'[">], s,'$i',hw/&,'done | sed -i -f - `find . -type f`
This is so that paths remain valid as files are moved....
openpic: fix remaining issues from idr-to-destmask conversion
openpic_update_irq() was checking idr rather than destmask, treatingit as if it were a simple bitmap of cpus. Changed to use destmask.
IPI delivery was removing bits directly from .idr, without calling...
openpic: fix timer address decoding
The timer memory range begins at 0x10f0, so that address 0x1120 showsup as 0x30, 0x1130 shows up as 0x40, etc. However, the addressdecoding (other than TFRR) is not adjusted for this, causing thewrong registers to be accessed....
openpic: add basic support for MPIC v4.2
Besides the new value in the version register, this provides:- ILR support, which includes: - IDR becoming a pure CPU bitmap, allowing 32 CPUs - machine check output support (though other parts of QEMU need to...
ppc: Move Mac machines to hw/ppc/
Signed-off-by: Andreas Färber <afaerber@suse.de>[agraf: squash in MAINTAINERS fix]Signed-off-by: Alexander Graf <agraf@suse.de>
sysbus: Drop sysbus_from_qdev() cast macro
Replace by SYS_BUS_DEVICE() QOM cast macro using a scripted conversion.Avoids the old macro creeping into new code.
Resolve a Coding Style warning in openpic code.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
openpic: export e500 epr enable into a ppc.c function
Enabling and disabling the EPR capability (mpic_proxy) is a systemwide operation. As such, it belongs into the ppc.c file, since that'swhere PPC specific machine wide logic happens.
Signed-off-by: Alexander Graf <agraf@suse.de>
openpic: move gcr write into a function
The GCR register contains too much functionality to be covered insideof the register switch statement. Move it out into a separate function.
openpic: unify gcr mode mask updates
The mode mask already masks out bits we don't care about, so theactual handling code can stay intact regardless.
openpic: set mixed mode as supported
The Raven MPIC implementation supports the "Mixed" mode to work withan i8259. While we don't implement mixed mode, we should mark it asa supported mode in the mode bitmap.
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf
Make all static TypeInfos const
Since 39bffca2030950ef6efe57c2fac8327a45ae1015 (qdev: register alltypes natively through QEMU Object Model), TypeInfo as used inthe common, non-iterative pattern is no longer amended with informationand should therefore be const....
openpic: IRQ_check: search the queue a word at a time
Search the queue more efficiently by first looking for a non-zero word,and then using the common bit-searching function to find the bit withinthe word. It would be even nicer if bitops_ffsl() could be hooked up...
openpic: move IACK to its own function
Besides making the code cleaner, we will need a separate way to accessIACK in order to implement EPR (external proxy) interrupt delivery.
Signed-off-by: Scott Wood <scottwood@freescale.com>Signed-off-by: Alexander Graf <agraf@suse.de>
openpic: fix CTPR and de-assertion of interrupts
Properly implement level-triggered interrupts by withdrawing aninterrupt from the raised queue if the interrupt source de-asserts.Also withdraw from the raised queue if the interrupt becomes masked.
When CTPR is written, check whether we need to raise or lower the...
PPC: Bring EPR support closer to reality
We already used to support the external proxy facility of FSL MPICs,but only implemented it halfway correctly.
This patch adds support for
openpic: make register names correspond better with hw docs
The base openpic specification doesn't provide abbreviated registernames, so it's somewhat understandable that the QEMU code made upits own, except that most of the names that QEMU used didn't correspond...
openpic: rework critical interrupt support
Critical interrupts on FSL MPIC are not supposed to payattention to priority, IACK, EOI, etc. On the currently modeledversion it's not supposed to pay attention to the mask bit either.
Also reorganize to make it easier to implement newer FSL MPIC models,...
openpic: make ctpr signed
Other priorities are signed, so avoid comparisons betweensigned and unsigned.
openpic/fsl: critical interrupts ignore mask before v4.1
Signed-off-by: Scott Wood <scottwood@freescale.com>[agraf: make bool :1]Signed-off-by: Alexander Graf <agraf@suse.de>
openpic: always call IRQ_check from IRQ_get_next
Previously the code relied on the queue's "next" field gettingset to -1 sometime between an update to the bitmap, and the nextcall to IRQ_get_next. Sometimes this happened after the update.Sometimes it happened before the check. Sometimes it didn't happen...
Revert "openpic: Accelerate pending irq search"
This reverts commit a9bd83f4c65de0058659ede009fa1a241f379edd.
This counting approach is not robust against setting a bit thatwas already set, or clearing a bit that was already clear. Perhapsthat is considered a bug, but besides the lack of any documentation...
openpic: use standard bitmap operations
Besides the private implementation being redundant, namespace collisionsprevented the use of other things in bitops.h.
Serialization does get a bit more awkward, unfortunately, since thestandard bitmap operations are "unsigned long" rather than "uint32_t",...
openpic: add some bounds checking for IRQ numbers
The two checks with abort() guard against potential QEMU-internalproblems, but the EOI check stops the guest from causing updates to queueposition -1 and other havoc if it writes EOI with no interrupt in...
openpic: fix sense and priority bits
Previously, the sense and priority bits were masked off when writingto IVPR, and all interrupts were treated as edge-triggered (despitethe existence of code for handling level-triggered interrupts).
Polarity is implemented only as storage. We don't simulate the...
openpic: s/opp->nb_irqs 1/opp>nb_cpus - 1/
"opp->nb_irqs-1" would have been a minor coding style error,but putting in one space but not the other makes it lookconfusingly like a numeric literal "-1".
Signed-off-by: Scott Wood <scottwood@freescale.com>...
openpic: don't crash on a register access without a CPU context
If we access a register via the QEMU memory inspection commands (e.g."xp") rather than from guest code, we won't have a CPU context.Gracefully fail to access the register in that case, rather than...
openpic: fix coding style issues
This patch fixes the following coding style violations:
- structs have to be typedef and be CamelCase - if()s are always surrounded by curly braces
openpic: fix debug prints
Fix various format errors when debug prints are enabled. Alsocause error checking to happen even when debug prints are notenabled, and consistently use 0x for hex output.
Signed-off-by: Scott Wood <scottwood@freescale.com>[agraf: adjust for more recent code base, prettify DPRINTF macro]...
openpic: lower interrupt when reading the MSI register
This will stop things from breaking once it's properly treated as alevel-triggered interrupt. Note that it's the MPIC's MSI cascadeinterrupts that are level-triggered; the individual MSIs areedge-triggered....
openpic: symbolicize some magic numbers
Deefine symbolic names for some register bits, and use some thathave already been defined.
Also convert some register values from hex to decimal when it improvesreadability.
IPVP_PRIORITY_MASK is corrected from (0x1F << 16) to (0xF << 16), in...
openpic: remove pcsr (CPU sensitivity register)
I could not find this register in any spec (FSL, IBM, or OpenPIC)and the code doesn't do anything with it but initialize, save,or restore it.
openpic: support large vectors on FSL mpic
Previously only the spurious vector was sized appropriatelyto the openpic model.
Also, instances of "IPVP_VECTOR(opp->spve)" were replace withjust "opp->spve", as opp->spve is already just a vector and notan IVPR....
openpic: BRR1 is not a CPU-specific register.
It's in the address range that normally contains a magic redirectionto the CPU-specific region of the curretn CPU, but it isn't actuallya per-CPU register. On real hardware BRR1 shows up only at 0x40000,not at 0x60000 or other non-magic per-CPU areas. Plus, this makes...
Merge commit '1dd3a74d2ee2d873cde0b390b536e45420b3fe05' into HEAD
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
pci: update all users to look in pci/
update all users so we can remove the makefile hack.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
openpic: fix minor coding style issues
This patch removes all remaining occurences of spaces before functionparameter indicating parenthesis.
openpic: Accelerate pending irq search
When we're done with one interrupt, we need to search for the next pendinginterrupt in the queue. This search has grown quite big now that we havemore than 256 possible irq lines.
So let's memorize how many interrupts we have pending in our bitmaps, so...
openpic: unify memory api subregions
The only difference between the "openpic" and "mpic" memory api subregiondescriptors is the endianness. Unify them as openpic accessors with explicitendianness markers in their names.
openpic: remove unused type variable
The openpic source irqs are carrying around a type indicator thatis never accessed by anything. Remove it.
openpic: convert simple reg operations to builtin bitops
The openpic code has its own bitmap code to access bits inside of abitmap. However, that is overkill when we simply want to check for abit inside of a uint32_t.
So instead, let's use normal bit masks and C builtin shifts and ands....
openpic: rename openpic_t to OpenPICState
Rename the openpic_t struct to OpenPICState, so it adheres better tothe current coding style rules.
openpic: remove irq_out
The current openpic emulation contains half-ready code for bypass mode.Remove it, so that when someone wants to finish it they can start from aclean state.
openpic: convert to qdev
This patch converts the OpenPIC device to qdev. Along the way itrenames the "openpic" target to "raven" and the "mpic" target to"fsl_mpic_20", to better reflect the actual models they implement.
This way we have a generic OpenPIC device now that can handle...
openpic: make brr1 model specific
Now that we can properly distinguish between openpic model differences,let's move brr1 out of the raven code path.
openpic: add Shared MSI support
The OpenPIC allows MSI access through shared MSI registers. Implementthem for the MPC8544 MPIC, so we can support MSIs.
openpic: Remove unused code
The openpic code had a few WIP bits left that nobody reanimated withinthe last few years. Remove that code.
Signed-off-by: Alexander Graf <agraf@suse.de>Acked-by: Hervé Poussineau <hpoussin@reactos.org>
mpic: Unify numbering scheme
MPIC interrupt numbers in Linux (device tree) and in QEMU are different,because QEMU takes the sparseness of the IRQ number space into account.
Remove that cleverness and instead assume a flat number space. This makesthe code easier to understand, because we are actually aligned with Linux...
openpic: update to proper memory api
The openpic code was still using the old mmio memory api. Convert it tobe a generic memory api user and clean up some code that becomes redundantthat way.
openpic: combine mpic and openpic src handlers
The MPIC source irq handler suddenly became identical to the standardOpenPIC source irq handler. Combine them into the same function.
openpic: Convert subregions to memory api
The "openpic" controller is currently using one big region and doessubregion dispatching manually. Move this to the memory api.
openpic: combine mpic and openpic irq raise functions
The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical,just that the MPIC one can also raise critical interrupts.
Combine those two and check for critical raise capability during runtime....
openpic: merge mpic and openpic timer handling
The openpic and mpic timer handling code is basically the same.Merge them.
openpic: combine openpic and mpic reset functions
The openpic and mpic reset handlers are almost identical. Combinethem and extract the differences into state variables.
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
openpic: Added BRR1 register
Linux mpic driver uses (changes may be in pipeline to get upstreamed soon)BRR1. This patch adds the support to emulate readonly FSL BRR1 register.
Currently QEMU does not fully emulate any version on MPIC, so the MPICMajor number and Minor number are set to 0....
PPC: Fix openpic with relative memregions
After commit 5312bd8b3152 we got memory region relative offsets into our mmiocallbacks instead of page boundary based offsets.
This broke the OpenPIC emulation which expected offsets to be on page boundaryand substracted its region offset manually....
openpic: remove dead code to make a PCI device version
bus is always NULL so the code in this if clause is dead (and thereforeuntested).
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Merge remote-tracking branch 'upstream' into memory/batch
openpic: Unfold write_IRQreg
The helper function write_IRQreg was always called with a specific argument onthe type of register to access. Inside the function we were simply doing aswitch on that constant argument again. It's a lot easier to just unfold this...
openpic: Unfold read_IRQreg
The helper function read_IRQreg was always called with a specific argument onthe type of register to access. Inside the function we were simply doing aswitch on that constant argument again. It's a lot easier to just unfold this...
PPC: Add CPU local MMIO regions to MPIC
The MPIC exports a register set for each CPU connected to it. They can allbe accessed through specific registers or using a shadow page that is mappeddifferently depending on which CPU accesses it.
This patch implements the shadow map, making it possible for guests to access...
PPC: Extend MPIC MMIO range
The MPIC exports a page for each CPU that it controls. To support more thanone CPU, we need to also reserve the MMIO space according to the amount ofCPUs we want to support.
PPC: Fix IPI support in MPIC
The current IPI support in the MPIC code is incomplete and doesn't work. Thiscode adds proper support for IPIs in MPIC by using the IDE register to rememberwhich CPUs IPIs are still outstanding to. New triggers through the IPI trigger...
PPC: Set MPIC IDE for IPI to 0
We use the IDE register with IPIs as a mask to keep track which processorshave already acknowledged the respective interrupt. So we need to initializeit to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the...
PPC: MPIC: Remove read functionality for WO registers
The IPI dispatch registers are write only according to every MPICspec I have found. So instead of pretending you could read back somethingfrom them, better not handle them at all.
Reported-by: Elie Richa <richa@adacore.com>...
PPC: MPIC: Fix CI bit definitions
The bit definitions for critical interrupt routing are in PowerPC order(most significant bit is 0), while we end up shifting it with normal bitorder. Turn the numbers around so we actually end up fetching theright ones....
PPC: Bump MPIC up to 32 supported CPUs
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that inthe code exporting the numbers out and fix an integer overflow while at it.
v1 -> v2:...
openpic: Memory API conversion for mpic
This patch converts mpic to the new memory API (through old mmio).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Avi Kivity <avi@redhat.com>
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
pci: rename pci_register_bar_region() to pci_register_bar()
Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
ppc: convert to memory API
openpic: Replace explicit byte swap with endian hints
This patch replaces explicit bswaps with endianness hints to themmio layer.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. Thetarget endianness is not of their concern, so we need to push thingsdown a level.
This patch adds a parameter to cpu_register_io_memory that allows adevice to choose its endianness. For now, all devices simply choose...
pci: Replace unneeded type casts in calls of pci_register_bar
There is no need for these type casts (as other existingcode shows). So re-write the first argument withouttype cast (and remove a related TODO comment).
Cc: Michael S. Tsirkin <mst@redhat.com>...
pci: don't overwrite multi functio bit in pci header type.
Don't overwrite pci header type.Otherwise, multi function bit which pci_init_header_type() setsappropriately is lost.Anyway PCI_HEADER_TYPE_NORMAL is zero, so it is unnecessary to zerowhich is already zero cleared....
savevm: Add DeviceState param
When available, we'd like to be able to access the DeviceStatewhen registering a savevm. For buses with a get_dev_path()function, this will allow us to create more unique savevmid strings.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>...
Compile openpic only once
Replace TARGET_PAGE_SIZE with 4096. Make byte swapping unconditionalsince PPC is big endian.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: Initialize OpenPIC properly
When lowering an IRQ line, we search for the line we're supposed to lower.
Usually we run into an optimization there that queues up interrupts. Thisqueue ends with -1. Unfortunately we didn't set the first item to -1....
hw/openpic.c: replace tabs by spaces
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
PCI: make duplicate devfn allocation fatal
Only two callers of pci_create_simple/pci_register_device botheredto check the return value. Other cases were prone to crashing withspurious NULL pointer dereferences.
Make QEMU exit with an error message when devfn is attempted to...
pci: introduce pcibus_t to represent pci bus address/size instead of uint32_t
This patch is preliminary for 64 bit BAR support.Introduce dedicated type, pcibus_t, to represent pci bus address/sizeinstead of uint32_t.Later this type will be changed to uint64_t....
pci: s/PCI_ADDRESS_SPACE_/PCI_BASE_ADDRESS_SPACE_/ to match pci_regs.h
make constants for pci base address match pci_regs.h byrenaming PCI_ADDRESS_SPACE_xxx to PCI_BASE_ADDRESS_SPACE_xxx.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>Acked-by: Michael S. Tsirkin <mst@redhat.com>...
PPC: remove unneeded calls to device reset
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Make CPURead/WriteFunc structure 'const'
Fix most warnings (errors with -Werror) when debugging is enabled
I used the following command to enable debugging:perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*
Revert "Introduce reset notifier order"
This reverts commit 8217606e6edb49591b4a6fd5a0d1229cebe470a9 (andupdates later added users of qemu_register_reset), we solved theproblem it originally addressed less invasively.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Rename pci_register_io_region() to pci_register_bar()
This function is used to manage a PCI BAR, so make the more genericpci_register_io_region() available to other uses.
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove io_index argument from cpu_register_io_memory()
The parameter is always zero except when registering the three internalio regions (ROM, unassigned, notdirty). Remove the parameter to reducethe API's power, thus facilitating future change.
Signed-off-by: Avi Kivity <avi@redhat.com>...
Introduce reset notifier order
Add the parameter 'order' to qemu_register_reset and sort callbacks onregistration. On system reset, callbacks with lower order will beinvoked before those with higher order. Update all existing users to thestandard order 0....
Replace gcc variadic macro extension with C99 version
use PCI_HEADER_TYPE.
use symbolic value instead of 0x0e and related value.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Delete some unused macros detected with -Wp,-Wunused-macros use
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
hw/openpic: define list in mpic_init() const
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6660 c046a42c-6fe2-441c-8c8c-71466251a162
kvm/powerpc: Enable MPIC for E500 platform.
MPIC and OpenPIC have very similar design.So a lot of code can be reused.
Signed-off-by: Liu Yu <yu.liu@freescale.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6659 c046a42c-6fe2-441c-8c8c-71466251a162
Add savevm and reset support for OpenPic
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6544 c046a42c-6fe2-441c-8c8c-71466251a162