Revision 3bd88451

b/default-configs/arm-softmmu.mak
34 34
CONFIG_USB_MUSB=y
35 35

  
36 36
CONFIG_ARM_TIMER=y
37
CONFIG_ARM_MPTIMER=y
37 38
CONFIG_PL011=y
38 39
CONFIG_PL022=y
39 40
CONFIG_PL031=y
......
53 54
CONFIG_BITBANG_I2C=y
54 55
CONFIG_FRAMEBUFFER=y
55 56
CONFIG_XILINX_SPIPS=y
57

  
56 58
CONFIG_MARVELL_88W8618=y
57 59
CONFIG_OMAP=y
60
CONFIG_TSC210X=y
58 61
CONFIG_BLIZZARD=y
59 62
CONFIG_ONENAND=y
63
CONFIG_TUSB6010=y
60 64
CONFIG_IMX=y
61 65
CONFIG_ZAURUS=y
62 66

  
b/default-configs/sparc-softmmu.mak
10 10
CONFIG_PCNET_COMMON=y
11 11
CONFIG_LANCE=y
12 12
CONFIG_TCX=y
13
CONFIG_SLAVIO=y
13 14
CONFIG_CS4231=y
14 15
CONFIG_GRLIB=y
b/hw/arm/Makefile.objs
3 3
obj-y += a9scu.o
4 4
obj-y += realview_gic.o arm_sysctl.o arm11mpcore.o a9mpcore.o
5 5
obj-y += exynos4210_gic.o exynos4210_combiner.o
6
obj-y += exynos4210_pwm.o
7
obj-y += exynos4210_pmu.o exynos4210_mct.o
8
obj-y += exynos4210_rtc.o
9
obj-y += arm_mptimer.o a15mpcore.o
6
obj-y += exynos4210_pmu.o
7
obj-y += a15mpcore.o
10 8
obj-y += armv7m_nvic.o
11
obj-y += pxa2xx_timer.o pxa2xx_dma.o
12
obj-y += pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
9
obj-y += pxa2xx_dma.o
10
obj-y += pxa2xx_mmci.o pxa2xx_pcmcia.o
13 11
obj-y += zaurus.o
14 12
obj-y += omap_dma.o omap_clk.o omap_mmc.o \
15 13
                omap_gpio.o omap_intc.o
16
obj-y += soc_dma.o omap_gptimer.o omap_synctimer.o \
14
obj-y += soc_dma.o \
17 15
                omap_gpmc.o omap_sdrc.o omap_tap.o omap_l4.o
18
obj-y += tsc210x.o
19
obj-y += cbus.o tusb6010.o
16
obj-y += cbus.o
20 17
obj-y += mst_fpga.o
21 18
obj-y += strongarm.o
22
obj-y += imx_ccm.o imx_timer.o imx_avic.o
19
obj-y += imx_ccm.o imx_avic.o
23 20
obj-$(CONFIG_KVM) += kvm/arm_gic.o
24 21

  
25 22
obj-y := $(addprefix ../,$(obj-y))
/dev/null
1
/*
2
 * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
3
 *
4
 * Copyright (c) 2006-2007 CodeSourcery.
5
 * Copyright (c) 2011 Linaro Limited
6
 * Written by Paul Brook, Peter Maydell
7
 *
8
 * This program is free software; you can redistribute it and/or
9
 * modify it under the terms of the GNU General Public License
10
 * as published by the Free Software Foundation; either version
11
 * 2 of the License, or (at your option) any later version.
12
 *
13
 * This program is distributed in the hope that it will be useful,
14
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
 * GNU General Public License for more details.
17
 *
18
 * You should have received a copy of the GNU General Public License along
19
 * with this program; if not, see <http://www.gnu.org/licenses/>.
20
 */
21

  
22
#include "hw/sysbus.h"
23
#include "qemu/timer.h"
24

  
25
/* This device implements the per-cpu private timer and watchdog block
26
 * which is used in both the ARM11MPCore and Cortex-A9MP.
27
 */
28

  
29
#define MAX_CPUS 4
30

  
31
/* State of a single timer or watchdog block */
32
typedef struct {
33
    uint32_t count;
34
    uint32_t load;
35
    uint32_t control;
36
    uint32_t status;
37
    int64_t tick;
38
    QEMUTimer *timer;
39
    qemu_irq irq;
40
    MemoryRegion iomem;
41
} TimerBlock;
42

  
43
typedef struct {
44
    SysBusDevice busdev;
45
    uint32_t num_cpu;
46
    TimerBlock timerblock[MAX_CPUS];
47
    MemoryRegion iomem;
48
} ARMMPTimerState;
49

  
50
static inline int get_current_cpu(ARMMPTimerState *s)
51
{
52
    CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env);
53

  
54
    if (cpu_single_cpu->cpu_index >= s->num_cpu) {
55
        hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
56
                 s->num_cpu, cpu_single_cpu->cpu_index);
57
    }
58
    return cpu_single_cpu->cpu_index;
59
}
60

  
61
static inline void timerblock_update_irq(TimerBlock *tb)
62
{
63
    qemu_set_irq(tb->irq, tb->status);
64
}
65

  
66
/* Return conversion factor from mpcore timer ticks to qemu timer ticks.  */
67
static inline uint32_t timerblock_scale(TimerBlock *tb)
68
{
69
    return (((tb->control >> 8) & 0xff) + 1) * 10;
70
}
71

  
72
static void timerblock_reload(TimerBlock *tb, int restart)
73
{
74
    if (tb->count == 0) {
75
        return;
76
    }
77
    if (restart) {
78
        tb->tick = qemu_get_clock_ns(vm_clock);
79
    }
80
    tb->tick += (int64_t)tb->count * timerblock_scale(tb);
81
    qemu_mod_timer(tb->timer, tb->tick);
82
}
83

  
84
static void timerblock_tick(void *opaque)
85
{
86
    TimerBlock *tb = (TimerBlock *)opaque;
87
    tb->status = 1;
88
    if (tb->control & 2) {
89
        tb->count = tb->load;
90
        timerblock_reload(tb, 0);
91
    } else {
92
        tb->count = 0;
93
    }
94
    timerblock_update_irq(tb);
95
}
96

  
97
static uint64_t timerblock_read(void *opaque, hwaddr addr,
98
                                unsigned size)
99
{
100
    TimerBlock *tb = (TimerBlock *)opaque;
101
    int64_t val;
102
    switch (addr) {
103
    case 0: /* Load */
104
        return tb->load;
105
    case 4: /* Counter.  */
106
        if (((tb->control & 1) == 0) || (tb->count == 0)) {
107
            return 0;
108
        }
109
        /* Slow and ugly, but hopefully won't happen too often.  */
110
        val = tb->tick - qemu_get_clock_ns(vm_clock);
111
        val /= timerblock_scale(tb);
112
        if (val < 0) {
113
            val = 0;
114
        }
115
        return val;
116
    case 8: /* Control.  */
117
        return tb->control;
118
    case 12: /* Interrupt status.  */
119
        return tb->status;
120
    default:
121
        return 0;
122
    }
123
}
124

  
125
static void timerblock_write(void *opaque, hwaddr addr,
126
                             uint64_t value, unsigned size)
127
{
128
    TimerBlock *tb = (TimerBlock *)opaque;
129
    int64_t old;
130
    switch (addr) {
131
    case 0: /* Load */
132
        tb->load = value;
133
        /* Fall through.  */
134
    case 4: /* Counter.  */
135
        if ((tb->control & 1) && tb->count) {
136
            /* Cancel the previous timer.  */
137
            qemu_del_timer(tb->timer);
138
        }
139
        tb->count = value;
140
        if (tb->control & 1) {
141
            timerblock_reload(tb, 1);
142
        }
143
        break;
144
    case 8: /* Control.  */
145
        old = tb->control;
146
        tb->control = value;
147
        if (((old & 1) == 0) && (value & 1)) {
148
            if (tb->count == 0 && (tb->control & 2)) {
149
                tb->count = tb->load;
150
            }
151
            timerblock_reload(tb, 1);
152
        }
153
        break;
154
    case 12: /* Interrupt status.  */
155
        tb->status &= ~value;
156
        timerblock_update_irq(tb);
157
        break;
158
    }
159
}
160

  
161
/* Wrapper functions to implement the "read timer/watchdog for
162
 * the current CPU" memory regions.
163
 */
164
static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
165
                                   unsigned size)
166
{
167
    ARMMPTimerState *s = (ARMMPTimerState *)opaque;
168
    int id = get_current_cpu(s);
169
    return timerblock_read(&s->timerblock[id], addr, size);
170
}
171

  
172
static void arm_thistimer_write(void *opaque, hwaddr addr,
173
                                uint64_t value, unsigned size)
174
{
175
    ARMMPTimerState *s = (ARMMPTimerState *)opaque;
176
    int id = get_current_cpu(s);
177
    timerblock_write(&s->timerblock[id], addr, value, size);
178
}
179

  
180
static const MemoryRegionOps arm_thistimer_ops = {
181
    .read = arm_thistimer_read,
182
    .write = arm_thistimer_write,
183
    .valid = {
184
        .min_access_size = 4,
185
        .max_access_size = 4,
186
    },
187
    .endianness = DEVICE_NATIVE_ENDIAN,
188
};
189

  
190
static const MemoryRegionOps timerblock_ops = {
191
    .read = timerblock_read,
192
    .write = timerblock_write,
193
    .valid = {
194
        .min_access_size = 4,
195
        .max_access_size = 4,
196
    },
197
    .endianness = DEVICE_NATIVE_ENDIAN,
198
};
199

  
200
static void timerblock_reset(TimerBlock *tb)
201
{
202
    tb->count = 0;
203
    tb->load = 0;
204
    tb->control = 0;
205
    tb->status = 0;
206
    tb->tick = 0;
207
    if (tb->timer) {
208
        qemu_del_timer(tb->timer);
209
    }
210
}
211

  
212
static void arm_mptimer_reset(DeviceState *dev)
213
{
214
    ARMMPTimerState *s =
215
        FROM_SYSBUS(ARMMPTimerState, SYS_BUS_DEVICE(dev));
216
    int i;
217
    for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
218
        timerblock_reset(&s->timerblock[i]);
219
    }
220
}
221

  
222
static int arm_mptimer_init(SysBusDevice *dev)
223
{
224
    ARMMPTimerState *s = FROM_SYSBUS(ARMMPTimerState, dev);
225
    int i;
226
    if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {
227
        hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
228
    }
229
    /* We implement one timer block per CPU, and expose multiple MMIO regions:
230
     *  * region 0 is "timer for this core"
231
     *  * region 1 is "timer for core 0"
232
     *  * region 2 is "timer for core 1"
233
     * and so on.
234
     * The outgoing interrupt lines are
235
     *  * timer for core 0
236
     *  * timer for core 1
237
     * and so on.
238
     */
239
    memory_region_init_io(&s->iomem, &arm_thistimer_ops, s,
240
                          "arm_mptimer_timer", 0x20);
241
    sysbus_init_mmio(dev, &s->iomem);
242
    for (i = 0; i < s->num_cpu; i++) {
243
        TimerBlock *tb = &s->timerblock[i];
244
        tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
245
        sysbus_init_irq(dev, &tb->irq);
246
        memory_region_init_io(&tb->iomem, &timerblock_ops, tb,
247
                              "arm_mptimer_timerblock", 0x20);
248
        sysbus_init_mmio(dev, &tb->iomem);
249
    }
250

  
251
    return 0;
252
}
253

  
254
static const VMStateDescription vmstate_timerblock = {
255
    .name = "arm_mptimer_timerblock",
256
    .version_id = 2,
257
    .minimum_version_id = 2,
258
    .fields = (VMStateField[]) {
259
        VMSTATE_UINT32(count, TimerBlock),
260
        VMSTATE_UINT32(load, TimerBlock),
261
        VMSTATE_UINT32(control, TimerBlock),
262
        VMSTATE_UINT32(status, TimerBlock),
263
        VMSTATE_INT64(tick, TimerBlock),
264
        VMSTATE_TIMER(timer, TimerBlock),
265
        VMSTATE_END_OF_LIST()
266
    }
267
};
268

  
269
static const VMStateDescription vmstate_arm_mptimer = {
270
    .name = "arm_mptimer",
271
    .version_id = 2,
272
    .minimum_version_id = 2,
273
    .fields = (VMStateField[]) {
274
        VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu,
275
                                     2, vmstate_timerblock, TimerBlock),
276
        VMSTATE_END_OF_LIST()
277
    }
278
};
279

  
280
static Property arm_mptimer_properties[] = {
281
    DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
282
    DEFINE_PROP_END_OF_LIST()
283
};
284

  
285
static void arm_mptimer_class_init(ObjectClass *klass, void *data)
286
{
287
    DeviceClass *dc = DEVICE_CLASS(klass);
288
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
289

  
290
    sbc->init = arm_mptimer_init;
291
    dc->vmsd = &vmstate_arm_mptimer;
292
    dc->reset = arm_mptimer_reset;
293
    dc->no_user = 1;
294
    dc->props = arm_mptimer_properties;
295
}
296

  
297
static const TypeInfo arm_mptimer_info = {
298
    .name          = "arm_mptimer",
299
    .parent        = TYPE_SYS_BUS_DEVICE,
300
    .instance_size = sizeof(ARMMPTimerState),
301
    .class_init    = arm_mptimer_class_init,
302
};
303

  
304
static void arm_mptimer_register_types(void)
305
{
306
    type_register_static(&arm_mptimer_info);
307
}
308

  
309
type_init(arm_mptimer_register_types)
b/hw/cris/Makefile.objs
1 1
# IO blocks
2 2
obj-y += etraxfs_dma.o
3 3
obj-y += etraxfs_pic.o
4
obj-y += etraxfs_timer.o
5 4

  
6 5
obj-y := $(addprefix ../,$(obj-y))
7 6

  
/dev/null
1
/*
2
 * QEMU ETRAX Timers
3
 *
4
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24
#include "hw/sysbus.h"
25
#include "sysemu/sysemu.h"
26
#include "qemu/timer.h"
27
#include "hw/ptimer.h"
28

  
29
#define D(x)
30

  
31
#define RW_TMR0_DIV   0x00
32
#define R_TMR0_DATA   0x04
33
#define RW_TMR0_CTRL  0x08
34
#define RW_TMR1_DIV   0x10
35
#define R_TMR1_DATA   0x14
36
#define RW_TMR1_CTRL  0x18
37
#define R_TIME        0x38
38
#define RW_WD_CTRL    0x40
39
#define R_WD_STAT     0x44
40
#define RW_INTR_MASK  0x48
41
#define RW_ACK_INTR   0x4c
42
#define R_INTR        0x50
43
#define R_MASKED_INTR 0x54
44

  
45
struct etrax_timer {
46
    SysBusDevice busdev;
47
    MemoryRegion mmio;
48
    qemu_irq irq;
49
    qemu_irq nmi;
50

  
51
    QEMUBH *bh_t0;
52
    QEMUBH *bh_t1;
53
    QEMUBH *bh_wd;
54
    ptimer_state *ptimer_t0;
55
    ptimer_state *ptimer_t1;
56
    ptimer_state *ptimer_wd;
57

  
58
    int wd_hits;
59

  
60
    /* Control registers.  */
61
    uint32_t rw_tmr0_div;
62
    uint32_t r_tmr0_data;
63
    uint32_t rw_tmr0_ctrl;
64

  
65
    uint32_t rw_tmr1_div;
66
    uint32_t r_tmr1_data;
67
    uint32_t rw_tmr1_ctrl;
68

  
69
    uint32_t rw_wd_ctrl;
70

  
71
    uint32_t rw_intr_mask;
72
    uint32_t rw_ack_intr;
73
    uint32_t r_intr;
74
    uint32_t r_masked_intr;
75
};
76

  
77
static uint64_t
78
timer_read(void *opaque, hwaddr addr, unsigned int size)
79
{
80
    struct etrax_timer *t = opaque;
81
    uint32_t r = 0;
82

  
83
    switch (addr) {
84
    case R_TMR0_DATA:
85
        r = ptimer_get_count(t->ptimer_t0);
86
        break;
87
    case R_TMR1_DATA:
88
        r = ptimer_get_count(t->ptimer_t1);
89
        break;
90
    case R_TIME:
91
        r = qemu_get_clock_ns(vm_clock) / 10;
92
        break;
93
    case RW_INTR_MASK:
94
        r = t->rw_intr_mask;
95
        break;
96
    case R_MASKED_INTR:
97
        r = t->r_intr & t->rw_intr_mask;
98
        break;
99
    default:
100
        D(printf ("%s %x\n", __func__, addr));
101
        break;
102
    }
103
    return r;
104
}
105

  
106
static void update_ctrl(struct etrax_timer *t, int tnum)
107
{
108
    unsigned int op;
109
    unsigned int freq;
110
    unsigned int freq_hz;
111
    unsigned int div;
112
    uint32_t ctrl;
113

  
114
    ptimer_state *timer;
115

  
116
    if (tnum == 0) {
117
        ctrl = t->rw_tmr0_ctrl;
118
        div = t->rw_tmr0_div;
119
        timer = t->ptimer_t0;
120
    } else {
121
        ctrl = t->rw_tmr1_ctrl;
122
        div = t->rw_tmr1_div;
123
        timer = t->ptimer_t1;
124
    }
125

  
126

  
127
    op = ctrl & 3;
128
    freq = ctrl >> 2;
129
    freq_hz = 32000000;
130

  
131
    switch (freq)
132
    {
133
    case 0:
134
    case 1:
135
        D(printf ("extern or disabled timer clock?\n"));
136
        break;
137
    case 4: freq_hz =  29493000; break;
138
    case 5: freq_hz =  32000000; break;
139
    case 6: freq_hz =  32768000; break;
140
    case 7: freq_hz = 100000000; break;
141
    default:
142
        abort();
143
        break;
144
    }
145

  
146
    D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
147
    ptimer_set_freq(timer, freq_hz);
148
    ptimer_set_limit(timer, div, 0);
149

  
150
    switch (op)
151
    {
152
        case 0:
153
            /* Load.  */
154
            ptimer_set_limit(timer, div, 1);
155
            break;
156
        case 1:
157
            /* Hold.  */
158
            ptimer_stop(timer);
159
            break;
160
        case 2:
161
            /* Run.  */
162
            ptimer_run(timer, 0);
163
            break;
164
        default:
165
            abort();
166
            break;
167
    }
168
}
169

  
170
static void timer_update_irq(struct etrax_timer *t)
171
{
172
    t->r_intr &= ~(t->rw_ack_intr);
173
    t->r_masked_intr = t->r_intr & t->rw_intr_mask;
174

  
175
    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
176
    qemu_set_irq(t->irq, !!t->r_masked_intr);
177
}
178

  
179
static void timer0_hit(void *opaque)
180
{
181
    struct etrax_timer *t = opaque;
182
    t->r_intr |= 1;
183
    timer_update_irq(t);
184
}
185

  
186
static void timer1_hit(void *opaque)
187
{
188
    struct etrax_timer *t = opaque;
189
    t->r_intr |= 2;
190
    timer_update_irq(t);
191
}
192

  
193
static void watchdog_hit(void *opaque)
194
{
195
    struct etrax_timer *t = opaque;
196
    if (t->wd_hits == 0) {
197
        /* real hw gives a single tick before reseting but we are
198
           a bit friendlier to compensate for our slower execution.  */
199
        ptimer_set_count(t->ptimer_wd, 10);
200
        ptimer_run(t->ptimer_wd, 1);
201
        qemu_irq_raise(t->nmi);
202
    }
203
    else
204
        qemu_system_reset_request();
205

  
206
    t->wd_hits++;
207
}
208

  
209
static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
210
{
211
    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
212
    unsigned int wd_key = t->rw_wd_ctrl >> 9;
213
    unsigned int wd_cnt = t->rw_wd_ctrl & 511;
214
    unsigned int new_key = value >> 9 & ((1 << 7) - 1);
215
    unsigned int new_cmd = (value >> 8) & 1;
216

  
217
    /* If the watchdog is enabled, they written key must match the
218
       complement of the previous.  */
219
    wd_key = ~wd_key & ((1 << 7) - 1);
220

  
221
    if (wd_en && wd_key != new_key)
222
        return;
223

  
224
    D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 
225
         wd_en, new_key, wd_key, new_cmd, wd_cnt));
226

  
227
    if (t->wd_hits)
228
        qemu_irq_lower(t->nmi);
229

  
230
    t->wd_hits = 0;
231

  
232
    ptimer_set_freq(t->ptimer_wd, 760);
233
    if (wd_cnt == 0)
234
        wd_cnt = 256;
235
    ptimer_set_count(t->ptimer_wd, wd_cnt);
236
    if (new_cmd)
237
        ptimer_run(t->ptimer_wd, 1);
238
    else
239
        ptimer_stop(t->ptimer_wd);
240

  
241
    t->rw_wd_ctrl = value;
242
}
243

  
244
static void
245
timer_write(void *opaque, hwaddr addr,
246
            uint64_t val64, unsigned int size)
247
{
248
    struct etrax_timer *t = opaque;
249
    uint32_t value = val64;
250

  
251
    switch (addr)
252
    {
253
        case RW_TMR0_DIV:
254
            t->rw_tmr0_div = value;
255
            break;
256
        case RW_TMR0_CTRL:
257
            D(printf ("RW_TMR0_CTRL=%x\n", value));
258
            t->rw_tmr0_ctrl = value;
259
            update_ctrl(t, 0);
260
            break;
261
        case RW_TMR1_DIV:
262
            t->rw_tmr1_div = value;
263
            break;
264
        case RW_TMR1_CTRL:
265
            D(printf ("RW_TMR1_CTRL=%x\n", value));
266
            t->rw_tmr1_ctrl = value;
267
            update_ctrl(t, 1);
268
            break;
269
        case RW_INTR_MASK:
270
            D(printf ("RW_INTR_MASK=%x\n", value));
271
            t->rw_intr_mask = value;
272
            timer_update_irq(t);
273
            break;
274
        case RW_WD_CTRL:
275
            timer_watchdog_update(t, value);
276
            break;
277
        case RW_ACK_INTR:
278
            t->rw_ack_intr = value;
279
            timer_update_irq(t);
280
            t->rw_ack_intr = 0;
281
            break;
282
        default:
283
            printf ("%s " TARGET_FMT_plx " %x\n",
284
                __func__, addr, value);
285
            break;
286
    }
287
}
288

  
289
static const MemoryRegionOps timer_ops = {
290
    .read = timer_read,
291
    .write = timer_write,
292
    .endianness = DEVICE_LITTLE_ENDIAN,
293
    .valid = {
294
        .min_access_size = 4,
295
        .max_access_size = 4
296
    }
297
};
298

  
299
static void etraxfs_timer_reset(void *opaque)
300
{
301
    struct etrax_timer *t = opaque;
302

  
303
    ptimer_stop(t->ptimer_t0);
304
    ptimer_stop(t->ptimer_t1);
305
    ptimer_stop(t->ptimer_wd);
306
    t->rw_wd_ctrl = 0;
307
    t->r_intr = 0;
308
    t->rw_intr_mask = 0;
309
    qemu_irq_lower(t->irq);
310
}
311

  
312
static int etraxfs_timer_init(SysBusDevice *dev)
313
{
314
    struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
315

  
316
    t->bh_t0 = qemu_bh_new(timer0_hit, t);
317
    t->bh_t1 = qemu_bh_new(timer1_hit, t);
318
    t->bh_wd = qemu_bh_new(watchdog_hit, t);
319
    t->ptimer_t0 = ptimer_init(t->bh_t0);
320
    t->ptimer_t1 = ptimer_init(t->bh_t1);
321
    t->ptimer_wd = ptimer_init(t->bh_wd);
322

  
323
    sysbus_init_irq(dev, &t->irq);
324
    sysbus_init_irq(dev, &t->nmi);
325

  
326
    memory_region_init_io(&t->mmio, &timer_ops, t, "etraxfs-timer", 0x5c);
327
    sysbus_init_mmio(dev, &t->mmio);
328
    qemu_register_reset(etraxfs_timer_reset, t);
329
    return 0;
330
}
331

  
332
static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
333
{
334
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
335

  
336
    sdc->init = etraxfs_timer_init;
337
}
338

  
339
static const TypeInfo etraxfs_timer_info = {
340
    .name          = "etraxfs,timer",
341
    .parent        = TYPE_SYS_BUS_DEVICE,
342
    .instance_size = sizeof (struct etrax_timer),
343
    .class_init    = etraxfs_timer_class_init,
344
};
345

  
346
static void etraxfs_timer_register_types(void)
347
{
348
    type_register_static(&etraxfs_timer_info);
349
}
350

  
351
type_init(etraxfs_timer_register_types)
/dev/null
1
/*
2
 * Samsung exynos4210 Multi Core timer
3
 *
4
 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5
 * All rights reserved.
6
 *
7
 * Evgeny Voevodin <e.voevodin@samsung.com>
8
 *
9
 * This program is free software; you can redistribute it and/or modify it
10
 * under the terms of the GNU General Public License as published by the
11
 * Free Software Foundation; either version 2 of the License, or (at your
12
 * option) any later version.
13
 *
14
 * This program is distributed in the hope that it will be useful,
15
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17
 * See the GNU General Public License for more details.
18
 *
19
 * You should have received a copy of the GNU General Public License along
20
 * with this program; if not, see <http://www.gnu.org/licenses/>.
21
 */
22

  
23
/*
24
 * Global Timer:
25
 *
26
 * Consists of two timers. First represents Free Running Counter and second
27
 * is used to measure interval from FRC to nearest comparator.
28
 *
29
 *        0                                                           UINT64_MAX
30
 *        |                              timer0                             |
31
 *        | <-------------------------------------------------------------- |
32
 *        | --------------------------------------------frc---------------> |
33
 *        |______________________________________________|__________________|
34
 *                CMP0          CMP1             CMP2    |           CMP3
35
 *                                                     __|            |_
36
 *                                                     |     timer1     |
37
 *                                                     | -------------> |
38
 *                                                    frc              CMPx
39
 *
40
 * Problem: when implementing global timer as is, overflow arises.
41
 * next_time = cur_time + period * count;
42
 * period and count are 64 bits width.
43
 * Lets arm timer for MCT_GT_COUNTER_STEP count and update internal G_CNT
44
 * register during each event.
45
 *
46
 * Problem: both timers need to be implemented using MCT_XT_COUNTER_STEP because
47
 * local timer contains two counters: TCNT and ICNT. TCNT == 0 -> ICNT--.
48
 * IRQ is generated when ICNT riches zero. Implementation where TCNT == 0
49
 * generates IRQs suffers from too frequently events. Better to have one
50
 * uint64_t counter equal to TCNT*ICNT and arm ptimer.c for a minimum(TCNT*ICNT,
51
 * MCT_GT_COUNTER_STEP); (yes, if target tunes ICNT * TCNT to be too low values,
52
 * there is no way to avoid frequently events).
53
 */
54

  
55
#include "hw/sysbus.h"
56
#include "qemu/timer.h"
57
#include "qemu-common.h"
58
#include "hw/ptimer.h"
59

  
60
#include "hw/arm/exynos4210.h"
61

  
62
//#define DEBUG_MCT
63

  
64
#ifdef DEBUG_MCT
65
#define DPRINTF(fmt, ...) \
66
        do { fprintf(stdout, "MCT: [%24s:%5d] " fmt, __func__, __LINE__, \
67
                     ## __VA_ARGS__); } while (0)
68
#else
69
#define DPRINTF(fmt, ...) do {} while (0)
70
#endif
71

  
72
#define    MCT_CFG          0x000
73
#define    G_CNT_L          0x100
74
#define    G_CNT_U          0x104
75
#define    G_CNT_WSTAT      0x110
76
#define    G_COMP0_L        0x200
77
#define    G_COMP0_U        0x204
78
#define    G_COMP0_ADD_INCR 0x208
79
#define    G_COMP1_L        0x210
80
#define    G_COMP1_U        0x214
81
#define    G_COMP1_ADD_INCR 0x218
82
#define    G_COMP2_L        0x220
83
#define    G_COMP2_U        0x224
84
#define    G_COMP2_ADD_INCR 0x228
85
#define    G_COMP3_L        0x230
86
#define    G_COMP3_U        0x234
87
#define    G_COMP3_ADD_INCR 0x238
88
#define    G_TCON           0x240
89
#define    G_INT_CSTAT      0x244
90
#define    G_INT_ENB        0x248
91
#define    G_WSTAT          0x24C
92
#define    L0_TCNTB         0x300
93
#define    L0_TCNTO         0x304
94
#define    L0_ICNTB         0x308
95
#define    L0_ICNTO         0x30C
96
#define    L0_FRCNTB        0x310
97
#define    L0_FRCNTO        0x314
98
#define    L0_TCON          0x320
99
#define    L0_INT_CSTAT     0x330
100
#define    L0_INT_ENB       0x334
101
#define    L0_WSTAT         0x340
102
#define    L1_TCNTB         0x400
103
#define    L1_TCNTO         0x404
104
#define    L1_ICNTB         0x408
105
#define    L1_ICNTO         0x40C
106
#define    L1_FRCNTB        0x410
107
#define    L1_FRCNTO        0x414
108
#define    L1_TCON          0x420
109
#define    L1_INT_CSTAT     0x430
110
#define    L1_INT_ENB       0x434
111
#define    L1_WSTAT         0x440
112

  
113
#define MCT_CFG_GET_PRESCALER(x)    ((x) & 0xFF)
114
#define MCT_CFG_GET_DIVIDER(x)      (1 << ((x) >> 8 & 7))
115

  
116
#define GET_G_COMP_IDX(offset)          (((offset) - G_COMP0_L) / 0x10)
117
#define GET_G_COMP_ADD_INCR_IDX(offset) (((offset) - G_COMP0_ADD_INCR) / 0x10)
118

  
119
#define G_COMP_L(x) (G_COMP0_L + (x) * 0x10)
120
#define G_COMP_U(x) (G_COMP0_U + (x) * 0x10)
121

  
122
#define G_COMP_ADD_INCR(x)  (G_COMP0_ADD_INCR + (x) * 0x10)
123

  
124
/* MCT bits */
125
#define G_TCON_COMP_ENABLE(x)   (1 << 2 * (x))
126
#define G_TCON_AUTO_ICREMENT(x) (1 << (2 * (x) + 1))
127
#define G_TCON_TIMER_ENABLE     (1 << 8)
128

  
129
#define G_INT_ENABLE(x)         (1 << (x))
130
#define G_INT_CSTAT_COMP(x)     (1 << (x))
131

  
132
#define G_CNT_WSTAT_L           1
133
#define G_CNT_WSTAT_U           2
134

  
135
#define G_WSTAT_COMP_L(x)       (1 << 4 * (x))
136
#define G_WSTAT_COMP_U(x)       (1 << ((4 * (x)) + 1))
137
#define G_WSTAT_COMP_ADDINCR(x) (1 << ((4 * (x)) + 2))
138
#define G_WSTAT_TCON_WRITE      (1 << 16)
139

  
140
#define GET_L_TIMER_IDX(offset) ((((offset) & 0xF00) - L0_TCNTB) / 0x100)
141
#define GET_L_TIMER_CNT_REG_IDX(offset, lt_i) \
142
        (((offset) - (L0_TCNTB + 0x100 * (lt_i))) >> 2)
143

  
144
#define L_ICNTB_MANUAL_UPDATE   (1 << 31)
145

  
146
#define L_TCON_TICK_START       (1)
147
#define L_TCON_INT_START        (1 << 1)
148
#define L_TCON_INTERVAL_MODE    (1 << 2)
149
#define L_TCON_FRC_START        (1 << 3)
150

  
151
#define L_INT_CSTAT_INTCNT      (1 << 0)
152
#define L_INT_CSTAT_FRCCNT      (1 << 1)
153

  
154
#define L_INT_INTENB_ICNTEIE    (1 << 0)
155
#define L_INT_INTENB_FRCEIE     (1 << 1)
156

  
157
#define L_WSTAT_TCNTB_WRITE     (1 << 0)
158
#define L_WSTAT_ICNTB_WRITE     (1 << 1)
159
#define L_WSTAT_FRCCNTB_WRITE   (1 << 2)
160
#define L_WSTAT_TCON_WRITE      (1 << 3)
161

  
162
enum LocalTimerRegCntIndexes {
163
    L_REG_CNT_TCNTB,
164
    L_REG_CNT_TCNTO,
165
    L_REG_CNT_ICNTB,
166
    L_REG_CNT_ICNTO,
167
    L_REG_CNT_FRCCNTB,
168
    L_REG_CNT_FRCCNTO,
169

  
170
    L_REG_CNT_AMOUNT
171
};
172

  
173
#define MCT_NIRQ                6
174
#define MCT_SFR_SIZE            0x444
175

  
176
#define MCT_GT_CMP_NUM          4
177

  
178
#define MCT_GT_MAX_VAL          UINT64_MAX
179

  
180
#define MCT_GT_COUNTER_STEP     0x100000000ULL
181
#define MCT_LT_COUNTER_STEP     0x100000000ULL
182
#define MCT_LT_CNT_LOW_LIMIT    0x100
183

  
184
/* global timer */
185
typedef struct {
186
    qemu_irq  irq[MCT_GT_CMP_NUM];
187

  
188
    struct gregs {
189
        uint64_t cnt;
190
        uint32_t cnt_wstat;
191
        uint32_t tcon;
192
        uint32_t int_cstat;
193
        uint32_t int_enb;
194
        uint32_t wstat;
195
        uint64_t comp[MCT_GT_CMP_NUM];
196
        uint32_t comp_add_incr[MCT_GT_CMP_NUM];
197
    } reg;
198

  
199
    uint64_t count;            /* Value FRC was armed with */
200
    int32_t curr_comp;             /* Current comparator FRC is running to */
201

  
202
    ptimer_state *ptimer_frc;                   /* FRC timer */
203

  
204
} Exynos4210MCTGT;
205

  
206
/* local timer */
207
typedef struct {
208
    int         id;             /* timer id */
209
    qemu_irq    irq;            /* local timer irq */
210

  
211
    struct tick_timer {
212
        uint32_t cnt_run;           /* cnt timer is running */
213
        uint32_t int_run;           /* int timer is running */
214

  
215
        uint32_t last_icnto;
216
        uint32_t last_tcnto;
217
        uint32_t tcntb;             /* initial value for TCNTB */
218
        uint32_t icntb;             /* initial value for ICNTB */
219

  
220
        /* for step mode */
221
        uint64_t    distance;       /* distance to count to the next event */
222
        uint64_t    progress;       /* progress when counting by steps */
223
        uint64_t    count;          /* count to arm timer with */
224

  
225
        ptimer_state *ptimer_tick;  /* timer for tick counter */
226
    } tick_timer;
227

  
228
    /* use ptimer.c to represent count down timer */
229

  
230
    ptimer_state *ptimer_frc;   /* timer for free running counter */
231

  
232
    /* registers */
233
    struct lregs {
234
        uint32_t    cnt[L_REG_CNT_AMOUNT];
235
        uint32_t    tcon;
236
        uint32_t    int_cstat;
237
        uint32_t    int_enb;
238
        uint32_t    wstat;
239
    } reg;
240

  
241
} Exynos4210MCTLT;
242

  
243
typedef struct Exynos4210MCTState {
244
    SysBusDevice busdev;
245
    MemoryRegion iomem;
246

  
247
    /* Registers */
248
    uint32_t    reg_mct_cfg;
249

  
250
    Exynos4210MCTLT l_timer[2];
251
    Exynos4210MCTGT g_timer;
252

  
253
    uint32_t    freq;                   /* all timers tick frequency, TCLK */
254
} Exynos4210MCTState;
255

  
256
/*** VMState ***/
257
static const VMStateDescription vmstate_tick_timer = {
258
    .name = "exynos4210.mct.tick_timer",
259
    .version_id = 1,
260
    .minimum_version_id = 1,
261
    .minimum_version_id_old = 1,
262
    .fields = (VMStateField[]) {
263
        VMSTATE_UINT32(cnt_run, struct tick_timer),
264
        VMSTATE_UINT32(int_run, struct tick_timer),
265
        VMSTATE_UINT32(last_icnto, struct tick_timer),
266
        VMSTATE_UINT32(last_tcnto, struct tick_timer),
267
        VMSTATE_UINT32(tcntb, struct tick_timer),
268
        VMSTATE_UINT32(icntb, struct tick_timer),
269
        VMSTATE_UINT64(distance, struct tick_timer),
270
        VMSTATE_UINT64(progress, struct tick_timer),
271
        VMSTATE_UINT64(count, struct tick_timer),
272
        VMSTATE_PTIMER(ptimer_tick, struct tick_timer),
273
        VMSTATE_END_OF_LIST()
274
    }
275
};
276

  
277
static const VMStateDescription vmstate_lregs = {
278
    .name = "exynos4210.mct.lregs",
279
    .version_id = 1,
280
    .minimum_version_id = 1,
281
    .minimum_version_id_old = 1,
282
    .fields = (VMStateField[]) {
283
        VMSTATE_UINT32_ARRAY(cnt, struct lregs, L_REG_CNT_AMOUNT),
284
        VMSTATE_UINT32(tcon, struct lregs),
285
        VMSTATE_UINT32(int_cstat, struct lregs),
286
        VMSTATE_UINT32(int_enb, struct lregs),
287
        VMSTATE_UINT32(wstat, struct lregs),
288
        VMSTATE_END_OF_LIST()
289
    }
290
};
291

  
292
static const VMStateDescription vmstate_exynos4210_mct_lt = {
293
    .name = "exynos4210.mct.lt",
294
    .version_id = 1,
295
    .minimum_version_id = 1,
296
    .minimum_version_id_old = 1,
297
    .fields = (VMStateField[]) {
298
        VMSTATE_INT32(id, Exynos4210MCTLT),
299
        VMSTATE_STRUCT(tick_timer, Exynos4210MCTLT, 0,
300
                vmstate_tick_timer,
301
                struct tick_timer),
302
        VMSTATE_PTIMER(ptimer_frc, Exynos4210MCTLT),
303
        VMSTATE_STRUCT(reg, Exynos4210MCTLT, 0,
304
                vmstate_lregs,
305
                struct lregs),
306
        VMSTATE_END_OF_LIST()
307
    }
308
};
309

  
310
static const VMStateDescription vmstate_gregs = {
311
    .name = "exynos4210.mct.lregs",
312
    .version_id = 1,
313
    .minimum_version_id = 1,
314
    .minimum_version_id_old = 1,
315
    .fields = (VMStateField[]) {
316
        VMSTATE_UINT64(cnt, struct gregs),
317
        VMSTATE_UINT32(cnt_wstat, struct gregs),
318
        VMSTATE_UINT32(tcon, struct gregs),
319
        VMSTATE_UINT32(int_cstat, struct gregs),
320
        VMSTATE_UINT32(int_enb, struct gregs),
321
        VMSTATE_UINT32(wstat, struct gregs),
322
        VMSTATE_UINT64_ARRAY(comp, struct gregs, MCT_GT_CMP_NUM),
323
        VMSTATE_UINT32_ARRAY(comp_add_incr, struct gregs,
324
                MCT_GT_CMP_NUM),
325
        VMSTATE_END_OF_LIST()
326
    }
327
};
328

  
329
static const VMStateDescription vmstate_exynos4210_mct_gt = {
330
    .name = "exynos4210.mct.lt",
331
    .version_id = 1,
332
    .minimum_version_id = 1,
333
    .minimum_version_id_old = 1,
334
    .fields = (VMStateField[]) {
335
        VMSTATE_STRUCT(reg, Exynos4210MCTGT, 0, vmstate_gregs,
336
                struct gregs),
337
        VMSTATE_UINT64(count, Exynos4210MCTGT),
338
        VMSTATE_INT32(curr_comp, Exynos4210MCTGT),
339
        VMSTATE_PTIMER(ptimer_frc, Exynos4210MCTGT),
340
        VMSTATE_END_OF_LIST()
341
    }
342
};
343

  
344
static const VMStateDescription vmstate_exynos4210_mct_state = {
345
    .name = "exynos4210.mct",
346
    .version_id = 1,
347
    .minimum_version_id = 1,
348
    .minimum_version_id_old = 1,
349
    .fields = (VMStateField[]) {
350
        VMSTATE_UINT32(reg_mct_cfg, Exynos4210MCTState),
351
        VMSTATE_STRUCT_ARRAY(l_timer, Exynos4210MCTState, 2, 0,
352
            vmstate_exynos4210_mct_lt, Exynos4210MCTLT),
353
        VMSTATE_STRUCT(g_timer, Exynos4210MCTState, 0,
354
            vmstate_exynos4210_mct_gt, Exynos4210MCTGT),
355
        VMSTATE_UINT32(freq, Exynos4210MCTState),
356
        VMSTATE_END_OF_LIST()
357
    }
358
};
359

  
360
static void exynos4210_mct_update_freq(Exynos4210MCTState *s);
361

  
362
/*
363
 * Set counter of FRC global timer.
364
 */
365
static void exynos4210_gfrc_set_count(Exynos4210MCTGT *s, uint64_t count)
366
{
367
    s->count = count;
368
    DPRINTF("global timer frc set count 0x%llx\n", count);
369
    ptimer_set_count(s->ptimer_frc, count);
370
}
371

  
372
/*
373
 * Get counter of FRC global timer.
374
 */
375
static uint64_t exynos4210_gfrc_get_count(Exynos4210MCTGT *s)
376
{
377
    uint64_t count = 0;
378
    count = ptimer_get_count(s->ptimer_frc);
379
    count = s->count - count;
380
    return s->reg.cnt + count;
381
}
382

  
383
/*
384
 * Stop global FRC timer
385
 */
386
static void exynos4210_gfrc_stop(Exynos4210MCTGT *s)
387
{
388
    DPRINTF("global timer frc stop\n");
389

  
390
    ptimer_stop(s->ptimer_frc);
391
}
392

  
393
/*
394
 * Start global FRC timer
395
 */
396
static void exynos4210_gfrc_start(Exynos4210MCTGT *s)
397
{
398
    DPRINTF("global timer frc start\n");
399

  
400
    ptimer_run(s->ptimer_frc, 1);
401
}
402

  
403
/*
404
 * Find next nearest Comparator. If current Comparator value equals to other
405
 * Comparator value, skip them both
406
 */
407
static int32_t exynos4210_gcomp_find(Exynos4210MCTState *s)
408
{
409
    int res;
410
    int i;
411
    int enabled;
412
    uint64_t min;
413
    int min_comp_i;
414
    uint64_t gfrc;
415
    uint64_t distance;
416
    uint64_t distance_min;
417
    int comp_i;
418

  
419
    /* get gfrc count */
420
    gfrc = exynos4210_gfrc_get_count(&s->g_timer);
421

  
422
    min = UINT64_MAX;
423
    distance_min = UINT64_MAX;
424
    comp_i = MCT_GT_CMP_NUM;
425
    min_comp_i = MCT_GT_CMP_NUM;
426
    enabled = 0;
427

  
428
    /* lookup for nearest comparator */
429
    for (i = 0; i < MCT_GT_CMP_NUM; i++) {
430

  
431
        if (s->g_timer.reg.tcon & G_TCON_COMP_ENABLE(i)) {
432

  
433
            enabled = 1;
434

  
435
            if (s->g_timer.reg.comp[i] > gfrc) {
436
                /* Comparator is upper then FRC */
437
                distance = s->g_timer.reg.comp[i] - gfrc;
438

  
439
                if (distance <= distance_min) {
440
                    distance_min = distance;
441
                    comp_i = i;
442
                }
443
            } else {
444
                /* Comparator is below FRC, find the smallest */
445

  
446
                if (s->g_timer.reg.comp[i] <= min) {
447
                    min = s->g_timer.reg.comp[i];
448
                    min_comp_i = i;
449
                }
450
            }
451
        }
452
    }
453

  
454
    if (!enabled) {
455
        /* All Comparators disabled */
456
        res = -1;
457
    } else if (comp_i < MCT_GT_CMP_NUM) {
458
        /* Found upper Comparator */
459
        res = comp_i;
460
    } else {
461
        /* All Comparators are below or equal to FRC  */
462
        res = min_comp_i;
463
    }
464

  
465
    DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
466
            res,
467
            s->g_timer.reg.comp[res],
468
            distance_min,
469
            gfrc);
470

  
471
    return res;
472
}
473

  
474
/*
475
 * Get distance to nearest Comparator
476
 */
477
static uint64_t exynos4210_gcomp_get_distance(Exynos4210MCTState *s, int32_t id)
478
{
479
    if (id == -1) {
480
        /* no enabled Comparators, choose max distance */
481
        return MCT_GT_COUNTER_STEP;
482
    }
483
    if (s->g_timer.reg.comp[id] - s->g_timer.reg.cnt < MCT_GT_COUNTER_STEP) {
484
        return s->g_timer.reg.comp[id] - s->g_timer.reg.cnt;
485
    } else {
486
        return MCT_GT_COUNTER_STEP;
487
    }
488
}
489

  
490
/*
491
 * Restart global FRC timer
492
 */
493
static void exynos4210_gfrc_restart(Exynos4210MCTState *s)
494
{
495
    uint64_t distance;
496

  
497
    exynos4210_gfrc_stop(&s->g_timer);
498

  
499
    s->g_timer.curr_comp = exynos4210_gcomp_find(s);
500

  
501
    distance = exynos4210_gcomp_get_distance(s, s->g_timer.curr_comp);
502

  
503
    if (distance > MCT_GT_COUNTER_STEP || !distance) {
504
        distance = MCT_GT_COUNTER_STEP;
505
    }
506

  
507
    exynos4210_gfrc_set_count(&s->g_timer, distance);
508
    exynos4210_gfrc_start(&s->g_timer);
509
}
510

  
511
/*
512
 * Raise global timer CMP IRQ
513
 */
514
static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
515
{
516
    Exynos4210MCTGT *s = opaque;
517

  
518
    /* If CSTAT is pending and IRQ is enabled */
519
    if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
520
            (s->reg.int_enb & G_INT_ENABLE(id))) {
521
        DPRINTF("gcmp timer[%d] IRQ\n", id);
522
        qemu_irq_raise(s->irq[id]);
523
    }
524
}
525

  
526
/*
527
 * Lower global timer CMP IRQ
528
 */
529
static void exynos4210_gcomp_lower_irq(void *opaque, uint32_t id)
530
{
531
    Exynos4210MCTGT *s = opaque;
532
    qemu_irq_lower(s->irq[id]);
533
}
534

  
535
/*
536
 * Global timer FRC event handler.
537
 * Each event occurs when internal counter reaches counter + MCT_GT_COUNTER_STEP
538
 * Every time we arm global FRC timer to count for MCT_GT_COUNTER_STEP value
539
 */
540
static void exynos4210_gfrc_event(void *opaque)
541
{
542
    Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
543
    int i;
544
    uint64_t distance;
545

  
546
    DPRINTF("\n");
547

  
548
    s->g_timer.reg.cnt += s->g_timer.count;
549

  
550
    /* Process all comparators */
551
    for (i = 0; i < MCT_GT_CMP_NUM; i++) {
552

  
553
        if (s->g_timer.reg.cnt == s->g_timer.reg.comp[i]) {
554
            /* reached nearest comparator */
555

  
556
            s->g_timer.reg.int_cstat |= G_INT_CSTAT_COMP(i);
557

  
558
            /* Auto increment */
559
            if (s->g_timer.reg.tcon & G_TCON_AUTO_ICREMENT(i)) {
560
                s->g_timer.reg.comp[i] += s->g_timer.reg.comp_add_incr[i];
561
            }
562

  
563
            /* IRQ */
564
            exynos4210_gcomp_raise_irq(&s->g_timer, i);
565
        }
566
    }
567

  
568
    /* Reload FRC to reach nearest comparator */
569
    s->g_timer.curr_comp = exynos4210_gcomp_find(s);
570
    distance = exynos4210_gcomp_get_distance(s, s->g_timer.curr_comp);
571
    if (distance > MCT_GT_COUNTER_STEP || !distance) {
572
        distance = MCT_GT_COUNTER_STEP;
573
    }
574
    exynos4210_gfrc_set_count(&s->g_timer, distance);
575

  
576
    exynos4210_gfrc_start(&s->g_timer);
577
}
578

  
579
/*
580
 * Get counter of FRC local timer.
581
 */
582
static uint64_t exynos4210_lfrc_get_count(Exynos4210MCTLT *s)
583
{
584
    return ptimer_get_count(s->ptimer_frc);
585
}
586

  
587
/*
588
 * Set counter of FRC local timer.
589
 */
590
static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s)
591
{
592
    if (!s->reg.cnt[L_REG_CNT_FRCCNTB]) {
593
        ptimer_set_count(s->ptimer_frc, MCT_LT_COUNTER_STEP);
594
    } else {
595
        ptimer_set_count(s->ptimer_frc, s->reg.cnt[L_REG_CNT_FRCCNTB]);
596
    }
597
}
598

  
599
/*
600
 * Start local FRC timer
601
 */
602
static void exynos4210_lfrc_start(Exynos4210MCTLT *s)
603
{
604
    ptimer_run(s->ptimer_frc, 1);
605
}
606

  
607
/*
608
 * Stop local FRC timer
609
 */
610
static void exynos4210_lfrc_stop(Exynos4210MCTLT *s)
611
{
612
    ptimer_stop(s->ptimer_frc);
613
}
614

  
615
/*
616
 * Local timer free running counter tick handler
617
 */
618
static void exynos4210_lfrc_event(void *opaque)
619
{
620
    Exynos4210MCTLT * s = (Exynos4210MCTLT *)opaque;
621

  
622
    /* local frc expired */
623

  
624
    DPRINTF("\n");
625

  
626
    s->reg.int_cstat |= L_INT_CSTAT_FRCCNT;
627

  
628
    /* update frc counter */
629
    exynos4210_lfrc_update_count(s);
630

  
631
    /* raise irq */
632
    if (s->reg.int_enb & L_INT_INTENB_FRCEIE) {
633
        qemu_irq_raise(s->irq);
634
    }
635

  
636
    /*  we reached here, this means that timer is enabled */
637
    exynos4210_lfrc_start(s);
638
}
639

  
640
static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s);
641
static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s);
642
static void exynos4210_ltick_recalc_count(struct tick_timer *s);
643

  
644
/*
645
 * Action on enabling local tick int timer
646
 */
647
static void exynos4210_ltick_int_start(struct tick_timer *s)
648
{
649
    if (!s->int_run) {
650
        s->int_run = 1;
651
    }
652
}
653

  
654
/*
655
 * Action on disabling local tick int timer
656
 */
657
static void exynos4210_ltick_int_stop(struct tick_timer *s)
658
{
659
    if (s->int_run) {
660
        s->last_icnto = exynos4210_ltick_int_get_cnto(s);
661
        s->int_run = 0;
662
    }
663
}
664

  
665
/*
666
 * Get count for INT timer
667
 */
668
static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s)
669
{
670
    uint32_t icnto;
671
    uint64_t remain;
672
    uint64_t count;
673
    uint64_t counted;
674
    uint64_t cur_progress;
675

  
676
    count = ptimer_get_count(s->ptimer_tick);
677
    if (count) {
678
        /* timer is still counting, called not from event */
679
        counted = s->count - ptimer_get_count(s->ptimer_tick);
680
        cur_progress = s->progress + counted;
681
    } else {
682
        /* timer expired earlier */
683
        cur_progress = s->progress;
684
    }
685

  
686
    remain = s->distance - cur_progress;
687

  
688
    if (!s->int_run) {
689
        /* INT is stopped. */
690
        icnto = s->last_icnto;
691
    } else {
692
        /* Both are counting */
693
        icnto = remain / s->tcntb;
694
    }
695

  
696
    return icnto;
697
}
698

  
699
/*
700
 * Start local tick cnt timer.
701
 */
702
static void exynos4210_ltick_cnt_start(struct tick_timer *s)
703
{
704
    if (!s->cnt_run) {
705

  
706
        exynos4210_ltick_recalc_count(s);
707
        ptimer_set_count(s->ptimer_tick, s->count);
708
        ptimer_run(s->ptimer_tick, 1);
709

  
710
        s->cnt_run = 1;
711
    }
712
}
713

  
714
/*
715
 * Stop local tick cnt timer.
716
 */
717
static void exynos4210_ltick_cnt_stop(struct tick_timer *s)
718
{
719
    if (s->cnt_run) {
720

  
721
        s->last_tcnto = exynos4210_ltick_cnt_get_cnto(s);
722

  
723
        if (s->int_run) {
724
            exynos4210_ltick_int_stop(s);
725
        }
726

  
727
        ptimer_stop(s->ptimer_tick);
728

  
729
        s->cnt_run = 0;
730
    }
731
}
... This diff was truncated because it exceeds the maximum size that can be displayed.

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