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/*
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 * QEMU GRLIB GPTimer Emulator
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 *
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 * Copyright (c) 2010-2011 AdaCore
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "hw/ptimer.h"
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#include "trace.h"
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#define UNIT_REG_SIZE    16     /* Size of memory mapped regs for the unit */
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#define GPTIMER_REG_SIZE 16     /* Size of memory mapped regs for a GPTimer */
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#define GPTIMER_MAX_TIMERS 8
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/* GPTimer Config register fields */
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#define GPTIMER_ENABLE      (1 << 0)
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#define GPTIMER_RESTART     (1 << 1)
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#define GPTIMER_LOAD        (1 << 2)
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#define GPTIMER_INT_ENABLE  (1 << 3)
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#define GPTIMER_INT_PENDING (1 << 4)
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#define GPTIMER_CHAIN       (1 << 5) /* Not supported */
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#define GPTIMER_DEBUG_HALT  (1 << 6) /* Not supported */
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/* Memory mapped register offsets */
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#define SCALER_OFFSET         0x00
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#define SCALER_RELOAD_OFFSET  0x04
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#define CONFIG_OFFSET         0x08
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#define COUNTER_OFFSET        0x00
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#define COUNTER_RELOAD_OFFSET 0x04
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#define TIMER_BASE            0x10
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typedef struct GPTimer     GPTimer;
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typedef struct GPTimerUnit GPTimerUnit;
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struct GPTimer {
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    QEMUBH *bh;
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    struct ptimer_state *ptimer;
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    qemu_irq     irq;
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    int          id;
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    GPTimerUnit *unit;
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    /* registers */
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    uint32_t counter;
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    uint32_t reload;
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    uint32_t config;
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};
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struct GPTimerUnit {
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    SysBusDevice  busdev;
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    MemoryRegion iomem;
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    uint32_t nr_timers;         /* Number of timers available */
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    uint32_t freq_hz;           /* System frequency */
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    uint32_t irq_line;          /* Base irq line */
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    GPTimer *timers;
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    /* registers */
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    uint32_t scaler;
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    uint32_t reload;
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    uint32_t config;
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};
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static void grlib_gptimer_enable(GPTimer *timer)
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{
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    assert(timer != NULL);
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    ptimer_stop(timer->ptimer);
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    if (!(timer->config & GPTIMER_ENABLE)) {
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        /* Timer disabled */
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        trace_grlib_gptimer_disabled(timer->id, timer->config);
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        return;
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    }
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    /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
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       underflow. Set count + 1 to simulate the GPTimer behavior. */
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    trace_grlib_gptimer_enable(timer->id, timer->counter + 1);
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    ptimer_set_count(timer->ptimer, timer->counter + 1);
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    ptimer_run(timer->ptimer, 1);
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}
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static void grlib_gptimer_restart(GPTimer *timer)
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{
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    assert(timer != NULL);
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    trace_grlib_gptimer_restart(timer->id, timer->reload);
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    timer->counter = timer->reload;
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    grlib_gptimer_enable(timer);
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}
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static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
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{
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    int i = 0;
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    uint32_t value = 0;
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    assert(unit != NULL);
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    if (scaler > 0) {
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        value = unit->freq_hz / (scaler + 1);
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    } else {
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        value = unit->freq_hz;
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    }
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    trace_grlib_gptimer_set_scaler(scaler, value);
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    for (i = 0; i < unit->nr_timers; i++) {
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        ptimer_set_freq(unit->timers[i].ptimer, value);
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    }
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}
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static void grlib_gptimer_hit(void *opaque)
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{
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    GPTimer *timer = opaque;
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    assert(timer != NULL);
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    trace_grlib_gptimer_hit(timer->id);
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    /* Timer expired */
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    if (timer->config & GPTIMER_INT_ENABLE) {
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        /* Set the pending bit (only unset by write in the config register) */
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        timer->config |= GPTIMER_INT_PENDING;
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        qemu_irq_pulse(timer->irq);
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    }
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    if (timer->config & GPTIMER_RESTART) {
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        grlib_gptimer_restart(timer);
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    }
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}
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static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
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                                   unsigned size)
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{
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    GPTimerUnit        *unit  = opaque;
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    hwaddr  timer_addr;
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    int                 id;
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    uint32_t            value = 0;
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    addr &= 0xff;
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    /* Unit registers */
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    switch (addr) {
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    case SCALER_OFFSET:
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        trace_grlib_gptimer_readl(-1, addr, unit->scaler);
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        return unit->scaler;
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    case SCALER_RELOAD_OFFSET:
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        trace_grlib_gptimer_readl(-1, addr, unit->reload);
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        return unit->reload;
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    case CONFIG_OFFSET:
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        trace_grlib_gptimer_readl(-1, addr, unit->config);
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        return unit->config;
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    default:
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        break;
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    }
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    timer_addr = (addr % TIMER_BASE);
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    id         = (addr - TIMER_BASE) / TIMER_BASE;
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    if (id >= 0 && id < unit->nr_timers) {
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        /* GPTimer registers */
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        switch (timer_addr) {
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        case COUNTER_OFFSET:
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            value = ptimer_get_count(unit->timers[id].ptimer);
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            trace_grlib_gptimer_readl(id, addr, value);
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            return value;
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        case COUNTER_RELOAD_OFFSET:
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            value = unit->timers[id].reload;
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            trace_grlib_gptimer_readl(id, addr, value);
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            return value;
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        case CONFIG_OFFSET:
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            trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
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            return unit->timers[id].config;
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        default:
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            break;
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        }
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    }
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    trace_grlib_gptimer_readl(-1, addr, 0);
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    return 0;
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}
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static void grlib_gptimer_write(void *opaque, hwaddr addr,
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                                uint64_t value, unsigned size)
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{
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    GPTimerUnit        *unit = opaque;
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    hwaddr  timer_addr;
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    int                 id;
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    addr &= 0xff;
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    /* Unit registers */
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    switch (addr) {
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    case SCALER_OFFSET:
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        value &= 0xFFFF; /* clean up the value */
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        unit->scaler = value;
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        trace_grlib_gptimer_writel(-1, addr, unit->scaler);
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        return;
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    case SCALER_RELOAD_OFFSET:
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        value &= 0xFFFF; /* clean up the value */
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        unit->reload = value;
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        trace_grlib_gptimer_writel(-1, addr, unit->reload);
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        grlib_gptimer_set_scaler(unit, value);
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        return;
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    case CONFIG_OFFSET:
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        /* Read Only (disable timer freeze not supported) */
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        trace_grlib_gptimer_writel(-1, addr, 0);
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        return;
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    default:
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        break;
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    }
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    timer_addr = (addr % TIMER_BASE);
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    id         = (addr - TIMER_BASE) / TIMER_BASE;
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    if (id >= 0 && id < unit->nr_timers) {
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        /* GPTimer registers */
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        switch (timer_addr) {
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        case COUNTER_OFFSET:
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            trace_grlib_gptimer_writel(id, addr, value);
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            unit->timers[id].counter = value;
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            grlib_gptimer_enable(&unit->timers[id]);
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            return;
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        case COUNTER_RELOAD_OFFSET:
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            trace_grlib_gptimer_writel(id, addr, value);
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            unit->timers[id].reload = value;
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            return;
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        case CONFIG_OFFSET:
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            trace_grlib_gptimer_writel(id, addr, value);
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            if (value & GPTIMER_INT_PENDING) {
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                /* clear pending bit */
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                value &= ~GPTIMER_INT_PENDING;
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            } else {
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                /* keep pending bit */
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                value |= unit->timers[id].config & GPTIMER_INT_PENDING;
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            }
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            unit->timers[id].config = value;
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            /* gptimer_restart calls gptimer_enable, so if "enable" and "load"
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               bits are present, we just have to call restart. */
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            if (value & GPTIMER_LOAD) {
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                grlib_gptimer_restart(&unit->timers[id]);
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            } else if (value & GPTIMER_ENABLE) {
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                grlib_gptimer_enable(&unit->timers[id]);
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            }
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            /* These fields must always be read as 0 */
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            value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);
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            unit->timers[id].config = value;
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            return;
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        default:
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            break;
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        }
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    }
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    trace_grlib_gptimer_writel(-1, addr, value);
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}
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static const MemoryRegionOps grlib_gptimer_ops = {
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    .read = grlib_gptimer_read,
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    .write = grlib_gptimer_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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};
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static void grlib_gptimer_reset(DeviceState *d)
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{
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    GPTimerUnit *unit = container_of(d, GPTimerUnit, busdev.qdev);
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    int          i    = 0;
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    assert(unit != NULL);
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    unit->scaler = 0;
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    unit->reload = 0;
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    unit->config = 0;
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    unit->config  = unit->nr_timers;
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    unit->config |= unit->irq_line << 3;
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    unit->config |= 1 << 8;     /* separate interrupt */
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    unit->config |= 1 << 9;     /* Disable timer freeze */
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    for (i = 0; i < unit->nr_timers; i++) {
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        GPTimer *timer = &unit->timers[i];
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        timer->counter = 0;
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        timer->reload = 0;
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        timer->config = 0;
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        ptimer_stop(timer->ptimer);
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        ptimer_set_count(timer->ptimer, 0);
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        ptimer_set_freq(timer->ptimer, unit->freq_hz);
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    }
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}
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static int grlib_gptimer_init(SysBusDevice *dev)
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{
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    GPTimerUnit  *unit = FROM_SYSBUS(typeof(*unit), dev);
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    unsigned int  i;
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    assert(unit->nr_timers > 0);
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    assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
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    unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);
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    for (i = 0; i < unit->nr_timers; i++) {
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        GPTimer *timer = &unit->timers[i];
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        timer->unit   = unit;
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        timer->bh     = qemu_bh_new(grlib_gptimer_hit, timer);
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        timer->ptimer = ptimer_init(timer->bh);
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        timer->id     = i;
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        /* One IRQ line for each timer */
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        sysbus_init_irq(dev, &timer->irq);
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        ptimer_set_freq(timer->ptimer, unit->freq_hz);
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    }
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    memory_region_init_io(&unit->iomem, &grlib_gptimer_ops, unit, "gptimer",
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                          UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
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    sysbus_init_mmio(dev, &unit->iomem);
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    return 0;
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}
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static Property grlib_gptimer_properties[] = {
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    DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz,   40000000),
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    DEFINE_PROP_UINT32("irq-line",  GPTimerUnit, irq_line,  8),
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    DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void grlib_gptimer_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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    k->init = grlib_gptimer_init;
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    dc->reset = grlib_gptimer_reset;
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    dc->props = grlib_gptimer_properties;
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}
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static const TypeInfo grlib_gptimer_info = {
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    .name          = "grlib,gptimer",
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(GPTimerUnit),
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    .class_init    = grlib_gptimer_class_init,
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};
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static void grlib_gptimer_register_types(void)
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{
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    type_register_static(&grlib_gptimer_info);
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}
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type_init(grlib_gptimer_register_types)