root / hw / timer / tusb6010.c @ 3bd88451
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/*
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* Texas Instruments TUSB6010 emulation.
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* Based on reverse-engineering of a linux driver.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h" |
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#include "qemu/timer.h" |
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#include "hw/usb.h" |
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#include "hw/arm/omap.h" |
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#include "hw/irq.h" |
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#include "hw/arm/devices.h" |
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#include "hw/sysbus.h" |
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typedef struct TUSBState { |
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SysBusDevice busdev; |
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MemoryRegion iomem[2];
|
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qemu_irq irq; |
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MUSBState *musb; |
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QEMUTimer *otg_timer; |
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QEMUTimer *pwr_timer; |
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|
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int power;
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uint32_t scratch; |
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uint16_t test_reset; |
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uint32_t prcm_config; |
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uint32_t prcm_mngmt; |
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uint16_t otg_status; |
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uint32_t dev_config; |
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int host_mode;
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uint32_t intr; |
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uint32_t intr_ok; |
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uint32_t mask; |
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uint32_t usbip_intr; |
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uint32_t usbip_mask; |
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uint32_t gpio_intr; |
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uint32_t gpio_mask; |
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uint32_t gpio_config; |
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uint32_t dma_intr; |
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uint32_t dma_mask; |
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uint32_t dma_map; |
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uint32_t dma_config; |
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uint32_t ep0_config; |
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uint32_t rx_config[15];
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uint32_t tx_config[15];
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uint32_t wkup_mask; |
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uint32_t pullup[2];
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uint32_t control_config; |
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uint32_t otg_timer_val; |
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} TUSBState; |
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#define TUSB_DEVCLOCK 60000000 /* 60 MHz */ |
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#define TUSB_VLYNQ_CTRL 0x004 |
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/* Mentor Graphics OTG core registers. */
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#define TUSB_BASE_OFFSET 0x400 |
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/* FIFO registers, 32-bit. */
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#define TUSB_FIFO_BASE 0x600 |
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/* Device System & Control registers, 32-bit. */
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#define TUSB_SYS_REG_BASE 0x800 |
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#define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) |
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#define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) |
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#define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) |
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#define TUSB_DEV_CONF_SOFT_ID (1 << 1) |
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#define TUSB_DEV_CONF_ID_SEL (1 << 0) |
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#define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) |
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#define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) |
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#define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) |
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#define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23) |
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#define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19) |
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#define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18) |
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#define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) |
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#define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) |
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#define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) |
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#define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) |
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#define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) |
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#define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) |
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#define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) |
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#define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) |
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#define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) |
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#define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7) |
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#define TUSB_PHY_OTG_CTRL_PD (1 << 6) |
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#define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) |
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#define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) |
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#define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) |
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#define TUSB_PHY_OTG_CTRL_RESET (1 << 2) |
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#define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) |
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#define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) |
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/* OTG status register */
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#define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) |
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#define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) |
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#define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) |
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#define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) |
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#define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) |
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#define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) |
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#define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) |
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#define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) |
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#define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) |
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#define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) |
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#define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) |
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|
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#define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) |
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#define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) |
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#define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) |
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#define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) |
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/* PRCM configuration register */
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#define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) |
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#define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) |
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#define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) |
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/* PRCM management register */
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#define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) |
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#define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25) |
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#define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) |
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#define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20) |
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#define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19) |
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#define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) |
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#define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) |
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#define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) |
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#define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) |
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#define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) |
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#define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) |
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#define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) |
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#define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) |
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#define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) |
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#define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) |
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/* Wake-up source clear and mask registers */
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#define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) |
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#define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) |
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#define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) |
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#define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) |
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#define TUSB_PRCM_WGPIO_7 (1 << 12) |
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#define TUSB_PRCM_WGPIO_6 (1 << 11) |
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#define TUSB_PRCM_WGPIO_5 (1 << 10) |
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#define TUSB_PRCM_WGPIO_4 (1 << 9) |
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#define TUSB_PRCM_WGPIO_3 (1 << 8) |
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#define TUSB_PRCM_WGPIO_2 (1 << 7) |
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#define TUSB_PRCM_WGPIO_1 (1 << 6) |
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#define TUSB_PRCM_WGPIO_0 (1 << 5) |
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#define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ |
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#define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ |
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#define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ |
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#define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ |
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#define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ |
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|
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#define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) |
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#define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) |
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#define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) |
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#define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) |
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#define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) |
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#define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) |
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#define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) |
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#define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) |
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#define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) |
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#define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) |
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#define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) |
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#define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) |
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#define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) |
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#define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) |
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#define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) |
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#define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) |
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|
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/* NOR flash interrupt source registers */
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#define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) |
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#define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) |
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#define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) |
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#define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) |
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#define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) |
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#define TUSB_INT_SRC_USB_IP_CORE (1 << 17) |
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#define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) |
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#define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) |
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#define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) |
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#define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) |
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#define TUSB_INT_SRC_DEV_READY (1 << 12) |
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#define TUSB_INT_SRC_USB_IP_TX (1 << 9) |
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#define TUSB_INT_SRC_USB_IP_RX (1 << 8) |
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#define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) |
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#define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) |
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#define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) |
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#define TUSB_INT_SRC_USB_IP_CONN (1 << 4) |
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#define TUSB_INT_SRC_USB_IP_SOF (1 << 3) |
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#define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) |
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#define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) |
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#define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) |
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|
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#define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) |
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#define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) |
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#define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) |
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#define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) |
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#define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) |
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#define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c) |
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#define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) |
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#define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c) |
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#define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188) |
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#define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) |
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#define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) |
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#define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) |
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|
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#define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) |
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#define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) |
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|
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/* Device System & Control register bitfields */
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#define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18) |
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#define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) |
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#define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) |
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#define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) |
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#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) |
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#define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20) |
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#define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16) |
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#define TUSB_EP0_CONFIG_SW_EN (1 << 8) |
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#define TUSB_EP0_CONFIG_DIR_TX (1 << 7) |
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#define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) |
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#define TUSB_EP_CONFIG_SW_EN (1 << 31) |
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#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) |
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#define TUSB_PROD_TEST_RESET_VAL 0xa596 |
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|
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static void tusb_intr_update(TUSBState *s) |
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{ |
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if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
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qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); |
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else
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qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); |
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} |
246 |
|
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static void tusb_usbip_intr_update(TUSBState *s) |
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{ |
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/* TX interrupt in the MUSB */
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if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) |
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s->intr |= TUSB_INT_SRC_USB_IP_TX; |
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else
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s->intr &= ~TUSB_INT_SRC_USB_IP_TX; |
254 |
|
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/* RX interrupt in the MUSB */
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if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) |
257 |
s->intr |= TUSB_INT_SRC_USB_IP_RX; |
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else
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s->intr &= ~TUSB_INT_SRC_USB_IP_RX; |
260 |
|
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/* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */
|
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|
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tusb_intr_update(s); |
264 |
} |
265 |
|
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static void tusb_dma_intr_update(TUSBState *s) |
267 |
{ |
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if (s->dma_intr & ~s->dma_mask)
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s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; |
270 |
else
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s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE; |
272 |
|
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tusb_intr_update(s); |
274 |
} |
275 |
|
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static void tusb_gpio_intr_update(TUSBState *s) |
277 |
{ |
278 |
/* TODO: How is this signalled? */
|
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} |
280 |
|
281 |
extern CPUReadMemoryFunc * const musb_read[]; |
282 |
extern CPUWriteMemoryFunc * const musb_write[]; |
283 |
|
284 |
static uint32_t tusb_async_readb(void *opaque, hwaddr addr) |
285 |
{ |
286 |
TUSBState *s = (TUSBState *) opaque; |
287 |
|
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switch (addr & 0xfff) { |
289 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
290 |
return musb_read[0](s->musb, addr & 0x1ff); |
291 |
|
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case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
293 |
return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
294 |
} |
295 |
|
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printf("%s: unknown register at %03x\n",
|
297 |
__FUNCTION__, (int) (addr & 0xfff)); |
298 |
return 0; |
299 |
} |
300 |
|
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static uint32_t tusb_async_readh(void *opaque, hwaddr addr) |
302 |
{ |
303 |
TUSBState *s = (TUSBState *) opaque; |
304 |
|
305 |
switch (addr & 0xfff) { |
306 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
307 |
return musb_read[1](s->musb, addr & 0x1ff); |
308 |
|
309 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
310 |
return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
311 |
} |
312 |
|
313 |
printf("%s: unknown register at %03x\n",
|
314 |
__FUNCTION__, (int) (addr & 0xfff)); |
315 |
return 0; |
316 |
} |
317 |
|
318 |
static uint32_t tusb_async_readw(void *opaque, hwaddr addr) |
319 |
{ |
320 |
TUSBState *s = (TUSBState *) opaque; |
321 |
int offset = addr & 0xfff; |
322 |
int epnum;
|
323 |
uint32_t ret; |
324 |
|
325 |
switch (offset) {
|
326 |
case TUSB_DEV_CONF:
|
327 |
return s->dev_config;
|
328 |
|
329 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
330 |
return musb_read[2](s->musb, offset & 0x1ff); |
331 |
|
332 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
333 |
return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
334 |
|
335 |
case TUSB_PHY_OTG_CTRL_ENABLE:
|
336 |
case TUSB_PHY_OTG_CTRL:
|
337 |
return 0x00; /* TODO */ |
338 |
|
339 |
case TUSB_DEV_OTG_STAT:
|
340 |
ret = s->otg_status; |
341 |
#if 0
|
342 |
if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
|
343 |
ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
|
344 |
#endif
|
345 |
return ret;
|
346 |
case TUSB_DEV_OTG_TIMER:
|
347 |
return s->otg_timer_val;
|
348 |
|
349 |
case TUSB_PRCM_REV:
|
350 |
return 0x20; |
351 |
case TUSB_PRCM_CONF:
|
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return s->prcm_config;
|
353 |
case TUSB_PRCM_MNGMT:
|
354 |
return s->prcm_mngmt;
|
355 |
case TUSB_PRCM_WAKEUP_SOURCE:
|
356 |
case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */ |
357 |
return 0x00000000; |
358 |
case TUSB_PRCM_WAKEUP_MASK:
|
359 |
return s->wkup_mask;
|
360 |
|
361 |
case TUSB_PULLUP_1_CTRL:
|
362 |
return s->pullup[0]; |
363 |
case TUSB_PULLUP_2_CTRL:
|
364 |
return s->pullup[1]; |
365 |
|
366 |
case TUSB_INT_CTRL_REV:
|
367 |
return 0x20; |
368 |
case TUSB_INT_CTRL_CONF:
|
369 |
return s->control_config;
|
370 |
|
371 |
case TUSB_USBIP_INT_SRC:
|
372 |
case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */ |
373 |
case TUSB_USBIP_INT_CLEAR:
|
374 |
return s->usbip_intr;
|
375 |
case TUSB_USBIP_INT_MASK:
|
376 |
return s->usbip_mask;
|
377 |
|
378 |
case TUSB_DMA_INT_SRC:
|
379 |
case TUSB_DMA_INT_SET: /* TODO: What do these two return? */ |
380 |
case TUSB_DMA_INT_CLEAR:
|
381 |
return s->dma_intr;
|
382 |
case TUSB_DMA_INT_MASK:
|
383 |
return s->dma_mask;
|
384 |
|
385 |
case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */ |
386 |
case TUSB_GPIO_INT_SET:
|
387 |
case TUSB_GPIO_INT_CLEAR:
|
388 |
return s->gpio_intr;
|
389 |
case TUSB_GPIO_INT_MASK:
|
390 |
return s->gpio_mask;
|
391 |
|
392 |
case TUSB_INT_SRC:
|
393 |
case TUSB_INT_SRC_SET: /* TODO: What do these two return? */ |
394 |
case TUSB_INT_SRC_CLEAR:
|
395 |
return s->intr;
|
396 |
case TUSB_INT_MASK:
|
397 |
return s->mask;
|
398 |
|
399 |
case TUSB_GPIO_REV:
|
400 |
return 0x30; |
401 |
case TUSB_GPIO_CONF:
|
402 |
return s->gpio_config;
|
403 |
|
404 |
case TUSB_DMA_CTRL_REV:
|
405 |
return 0x30; |
406 |
case TUSB_DMA_REQ_CONF:
|
407 |
return s->dma_config;
|
408 |
case TUSB_EP0_CONF:
|
409 |
return s->ep0_config;
|
410 |
case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
411 |
epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
412 |
return s->tx_config[epnum];
|
413 |
case TUSB_DMA_EP_MAP:
|
414 |
return s->dma_map;
|
415 |
case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
416 |
epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
417 |
return s->rx_config[epnum];
|
418 |
case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
419 |
(TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
420 |
return 0x00000000; /* TODO */ |
421 |
case TUSB_WAIT_COUNT:
|
422 |
return 0x00; /* TODO */ |
423 |
|
424 |
case TUSB_SCRATCH_PAD:
|
425 |
return s->scratch;
|
426 |
|
427 |
case TUSB_PROD_TEST_RESET:
|
428 |
return s->test_reset;
|
429 |
|
430 |
/* DIE IDs */
|
431 |
case TUSB_DIDR1_LO:
|
432 |
return 0xa9453c59; |
433 |
case TUSB_DIDR1_HI:
|
434 |
return 0x54059adf; |
435 |
} |
436 |
|
437 |
printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
438 |
return 0; |
439 |
} |
440 |
|
441 |
static void tusb_async_writeb(void *opaque, hwaddr addr, |
442 |
uint32_t value) |
443 |
{ |
444 |
TUSBState *s = (TUSBState *) opaque; |
445 |
|
446 |
switch (addr & 0xfff) { |
447 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
448 |
musb_write[0](s->musb, addr & 0x1ff, value); |
449 |
break;
|
450 |
|
451 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
452 |
musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
453 |
break;
|
454 |
|
455 |
default:
|
456 |
printf("%s: unknown register at %03x\n",
|
457 |
__FUNCTION__, (int) (addr & 0xfff)); |
458 |
return;
|
459 |
} |
460 |
} |
461 |
|
462 |
static void tusb_async_writeh(void *opaque, hwaddr addr, |
463 |
uint32_t value) |
464 |
{ |
465 |
TUSBState *s = (TUSBState *) opaque; |
466 |
|
467 |
switch (addr & 0xfff) { |
468 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
469 |
musb_write[1](s->musb, addr & 0x1ff, value); |
470 |
break;
|
471 |
|
472 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
473 |
musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
474 |
break;
|
475 |
|
476 |
default:
|
477 |
printf("%s: unknown register at %03x\n",
|
478 |
__FUNCTION__, (int) (addr & 0xfff)); |
479 |
return;
|
480 |
} |
481 |
} |
482 |
|
483 |
static void tusb_async_writew(void *opaque, hwaddr addr, |
484 |
uint32_t value) |
485 |
{ |
486 |
TUSBState *s = (TUSBState *) opaque; |
487 |
int offset = addr & 0xfff; |
488 |
int epnum;
|
489 |
|
490 |
switch (offset) {
|
491 |
case TUSB_VLYNQ_CTRL:
|
492 |
break;
|
493 |
|
494 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
495 |
musb_write[2](s->musb, offset & 0x1ff, value); |
496 |
break;
|
497 |
|
498 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
499 |
musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
500 |
break;
|
501 |
|
502 |
case TUSB_DEV_CONF:
|
503 |
s->dev_config = value; |
504 |
s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); |
505 |
if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
|
506 |
hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
|
507 |
break;
|
508 |
|
509 |
case TUSB_PHY_OTG_CTRL_ENABLE:
|
510 |
case TUSB_PHY_OTG_CTRL:
|
511 |
return; /* TODO */ |
512 |
case TUSB_DEV_OTG_TIMER:
|
513 |
s->otg_timer_val = value; |
514 |
if (value & TUSB_DEV_OTG_TIMER_ENABLE)
|
515 |
qemu_mod_timer(s->otg_timer, qemu_get_clock_ns(vm_clock) + |
516 |
muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), |
517 |
get_ticks_per_sec(), TUSB_DEVCLOCK)); |
518 |
else
|
519 |
qemu_del_timer(s->otg_timer); |
520 |
break;
|
521 |
|
522 |
case TUSB_PRCM_CONF:
|
523 |
s->prcm_config = value; |
524 |
break;
|
525 |
case TUSB_PRCM_MNGMT:
|
526 |
s->prcm_mngmt = value; |
527 |
break;
|
528 |
case TUSB_PRCM_WAKEUP_CLEAR:
|
529 |
break;
|
530 |
case TUSB_PRCM_WAKEUP_MASK:
|
531 |
s->wkup_mask = value; |
532 |
break;
|
533 |
|
534 |
case TUSB_PULLUP_1_CTRL:
|
535 |
s->pullup[0] = value;
|
536 |
break;
|
537 |
case TUSB_PULLUP_2_CTRL:
|
538 |
s->pullup[1] = value;
|
539 |
break;
|
540 |
case TUSB_INT_CTRL_CONF:
|
541 |
s->control_config = value; |
542 |
tusb_intr_update(s); |
543 |
break;
|
544 |
|
545 |
case TUSB_USBIP_INT_SET:
|
546 |
s->usbip_intr |= value; |
547 |
tusb_usbip_intr_update(s); |
548 |
break;
|
549 |
case TUSB_USBIP_INT_CLEAR:
|
550 |
s->usbip_intr &= ~value; |
551 |
tusb_usbip_intr_update(s); |
552 |
musb_core_intr_clear(s->musb, ~value); |
553 |
break;
|
554 |
case TUSB_USBIP_INT_MASK:
|
555 |
s->usbip_mask = value; |
556 |
tusb_usbip_intr_update(s); |
557 |
break;
|
558 |
|
559 |
case TUSB_DMA_INT_SET:
|
560 |
s->dma_intr |= value; |
561 |
tusb_dma_intr_update(s); |
562 |
break;
|
563 |
case TUSB_DMA_INT_CLEAR:
|
564 |
s->dma_intr &= ~value; |
565 |
tusb_dma_intr_update(s); |
566 |
break;
|
567 |
case TUSB_DMA_INT_MASK:
|
568 |
s->dma_mask = value; |
569 |
tusb_dma_intr_update(s); |
570 |
break;
|
571 |
|
572 |
case TUSB_GPIO_INT_SET:
|
573 |
s->gpio_intr |= value; |
574 |
tusb_gpio_intr_update(s); |
575 |
break;
|
576 |
case TUSB_GPIO_INT_CLEAR:
|
577 |
s->gpio_intr &= ~value; |
578 |
tusb_gpio_intr_update(s); |
579 |
break;
|
580 |
case TUSB_GPIO_INT_MASK:
|
581 |
s->gpio_mask = value; |
582 |
tusb_gpio_intr_update(s); |
583 |
break;
|
584 |
|
585 |
case TUSB_INT_SRC_SET:
|
586 |
s->intr |= value; |
587 |
tusb_intr_update(s); |
588 |
break;
|
589 |
case TUSB_INT_SRC_CLEAR:
|
590 |
s->intr &= ~value; |
591 |
tusb_intr_update(s); |
592 |
break;
|
593 |
case TUSB_INT_MASK:
|
594 |
s->mask = value; |
595 |
tusb_intr_update(s); |
596 |
break;
|
597 |
|
598 |
case TUSB_GPIO_CONF:
|
599 |
s->gpio_config = value; |
600 |
break;
|
601 |
case TUSB_DMA_REQ_CONF:
|
602 |
s->dma_config = value; |
603 |
break;
|
604 |
case TUSB_EP0_CONF:
|
605 |
s->ep0_config = value & 0x1ff;
|
606 |
musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
|
607 |
value & TUSB_EP0_CONFIG_DIR_TX); |
608 |
break;
|
609 |
case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
610 |
epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
611 |
s->tx_config[epnum] = value; |
612 |
musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); |
613 |
break;
|
614 |
case TUSB_DMA_EP_MAP:
|
615 |
s->dma_map = value; |
616 |
break;
|
617 |
case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
618 |
epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
619 |
s->rx_config[epnum] = value; |
620 |
musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); |
621 |
break;
|
622 |
case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
623 |
(TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
624 |
return; /* TODO */ |
625 |
case TUSB_WAIT_COUNT:
|
626 |
return; /* TODO */ |
627 |
|
628 |
case TUSB_SCRATCH_PAD:
|
629 |
s->scratch = value; |
630 |
break;
|
631 |
|
632 |
case TUSB_PROD_TEST_RESET:
|
633 |
s->test_reset = value; |
634 |
break;
|
635 |
|
636 |
default:
|
637 |
printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
638 |
return;
|
639 |
} |
640 |
} |
641 |
|
642 |
static const MemoryRegionOps tusb_async_ops = { |
643 |
.old_mmio = { |
644 |
.read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, }, |
645 |
.write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, }, |
646 |
}, |
647 |
.endianness = DEVICE_NATIVE_ENDIAN, |
648 |
}; |
649 |
|
650 |
static void tusb_otg_tick(void *opaque) |
651 |
{ |
652 |
TUSBState *s = (TUSBState *) opaque; |
653 |
|
654 |
s->otg_timer_val = 0;
|
655 |
s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; |
656 |
tusb_intr_update(s); |
657 |
} |
658 |
|
659 |
static void tusb_power_tick(void *opaque) |
660 |
{ |
661 |
TUSBState *s = (TUSBState *) opaque; |
662 |
|
663 |
if (s->power) {
|
664 |
s->intr_ok = ~0;
|
665 |
tusb_intr_update(s); |
666 |
} |
667 |
} |
668 |
|
669 |
static void tusb_musb_core_intr(void *opaque, int source, int level) |
670 |
{ |
671 |
TUSBState *s = (TUSBState *) opaque; |
672 |
uint16_t otg_status = s->otg_status; |
673 |
|
674 |
switch (source) {
|
675 |
case musb_set_vbus:
|
676 |
if (level)
|
677 |
otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID; |
678 |
else
|
679 |
otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; |
680 |
|
681 |
/* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */
|
682 |
/* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */
|
683 |
if (s->otg_status != otg_status) {
|
684 |
s->otg_status = otg_status; |
685 |
s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG; |
686 |
tusb_intr_update(s); |
687 |
} |
688 |
break;
|
689 |
|
690 |
case musb_set_session:
|
691 |
/* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */
|
692 |
/* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */
|
693 |
if (level) {
|
694 |
s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID; |
695 |
s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END; |
696 |
} else {
|
697 |
s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID; |
698 |
s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END; |
699 |
} |
700 |
|
701 |
/* XXX: some IRQ or anything? */
|
702 |
break;
|
703 |
|
704 |
case musb_irq_tx:
|
705 |
case musb_irq_rx:
|
706 |
s->usbip_intr = musb_core_intr_get(s->musb); |
707 |
/* Fall through. */
|
708 |
default:
|
709 |
if (level)
|
710 |
s->intr |= 1 << source;
|
711 |
else
|
712 |
s->intr &= ~(1 << source);
|
713 |
tusb_intr_update(s); |
714 |
break;
|
715 |
} |
716 |
} |
717 |
|
718 |
static void tusb6010_power(TUSBState *s, int on) |
719 |
{ |
720 |
if (!on) {
|
721 |
s->power = 0;
|
722 |
} else if (!s->power && on) { |
723 |
s->power = 1;
|
724 |
/* Pull the interrupt down after TUSB6010 comes up. */
|
725 |
s->intr_ok = 0;
|
726 |
tusb_intr_update(s); |
727 |
qemu_mod_timer(s->pwr_timer, |
728 |
qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 2);
|
729 |
} |
730 |
} |
731 |
|
732 |
static void tusb6010_irq(void *opaque, int source, int level) |
733 |
{ |
734 |
if (source) {
|
735 |
tusb_musb_core_intr(opaque, source - 1, level);
|
736 |
} else {
|
737 |
tusb6010_power(opaque, level); |
738 |
} |
739 |
} |
740 |
|
741 |
static void tusb6010_reset(DeviceState *dev) |
742 |
{ |
743 |
TUSBState *s = FROM_SYSBUS(TUSBState, SYS_BUS_DEVICE(dev)); |
744 |
int i;
|
745 |
|
746 |
s->test_reset = TUSB_PROD_TEST_RESET_VAL; |
747 |
s->host_mode = 0;
|
748 |
s->dev_config = 0;
|
749 |
s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ |
750 |
s->power = 0;
|
751 |
s->mask = 0xffffffff;
|
752 |
s->intr = 0x00000000;
|
753 |
s->otg_timer_val = 0;
|
754 |
s->scratch = 0;
|
755 |
s->prcm_config = 0;
|
756 |
s->prcm_mngmt = 0;
|
757 |
s->intr_ok = 0;
|
758 |
s->usbip_intr = 0;
|
759 |
s->usbip_mask = 0;
|
760 |
s->gpio_intr = 0;
|
761 |
s->gpio_mask = 0;
|
762 |
s->gpio_config = 0;
|
763 |
s->dma_intr = 0;
|
764 |
s->dma_mask = 0;
|
765 |
s->dma_map = 0;
|
766 |
s->dma_config = 0;
|
767 |
s->ep0_config = 0;
|
768 |
s->wkup_mask = 0;
|
769 |
s->pullup[0] = s->pullup[1] = 0; |
770 |
s->control_config = 0;
|
771 |
for (i = 0; i < 15; i++) { |
772 |
s->rx_config[i] = s->tx_config[i] = 0;
|
773 |
} |
774 |
musb_reset(s->musb); |
775 |
} |
776 |
|
777 |
static int tusb6010_init(SysBusDevice *dev) |
778 |
{ |
779 |
TUSBState *s = FROM_SYSBUS(TUSBState, dev); |
780 |
s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s); |
781 |
s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s); |
782 |
memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async", |
783 |
UINT32_MAX); |
784 |
sysbus_init_mmio(dev, &s->iomem[0]);
|
785 |
sysbus_init_mmio(dev, &s->iomem[1]);
|
786 |
sysbus_init_irq(dev, &s->irq); |
787 |
qdev_init_gpio_in(&dev->qdev, tusb6010_irq, musb_irq_max + 1);
|
788 |
s->musb = musb_init(&dev->qdev, 1);
|
789 |
return 0; |
790 |
} |
791 |
|
792 |
static void tusb6010_class_init(ObjectClass *klass, void *data) |
793 |
{ |
794 |
DeviceClass *dc = DEVICE_CLASS(klass); |
795 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
796 |
|
797 |
k->init = tusb6010_init; |
798 |
dc->reset = tusb6010_reset; |
799 |
} |
800 |
|
801 |
static const TypeInfo tusb6010_info = { |
802 |
.name = "tusb6010",
|
803 |
.parent = TYPE_SYS_BUS_DEVICE, |
804 |
.instance_size = sizeof(TUSBState),
|
805 |
.class_init = tusb6010_class_init, |
806 |
}; |
807 |
|
808 |
static void tusb6010_register_types(void) |
809 |
{ |
810 |
type_register_static(&tusb6010_info); |
811 |
} |
812 |
|
813 |
type_init(tusb6010_register_types) |