Revision 3bf73a49 target-sh4/translate.c
| b/target-sh4/translate.c | ||
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| 79 | 79 |
} |
| 80 | 80 |
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| 81 | 81 |
/* General purpose registers moves. */ |
| 82 |
static inline void gen_movl_imm_rN(target_ulong arg, int reg)
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static inline void gen_movl_imm_rN(uint32_t arg, int reg)
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| 83 | 83 |
{
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TCGv tmp = tcg_const_tl(arg);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
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TCGv tmp = tcg_const_i32(arg);
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tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
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| 86 | 86 |
tcg_temp_free(tmp); |
| 87 | 87 |
} |
| 88 | 88 |
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| 89 | 89 |
static always_inline void gen_movl_T_rN (TCGv t, int reg) |
| 90 | 90 |
{
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tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, gregs[reg]));
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tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
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| 92 | 92 |
} |
| 93 | 93 |
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| 94 | 94 |
static always_inline void gen_movl_rN_T (TCGv t, int reg) |
| 95 | 95 |
{
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tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, gregs[reg]));
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tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
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| 97 | 97 |
} |
| 98 | 98 |
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| 99 | 99 |
#ifdef CONFIG_USER_ONLY |
| ... | ... | |
| 355 | 355 |
gen_movl_imm_rN(B7_0s, REG(B11_8)); |
| 356 | 356 |
return; |
| 357 | 357 |
case 0x9000: /* mov.w @(disp,PC),Rn */ |
| 358 |
tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
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| 358 |
tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
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| 359 | 359 |
gen_op_ldw_T0_T0(ctx); |
| 360 | 360 |
gen_movl_T_rN(cpu_T[0], REG(B11_8)); |
| 361 | 361 |
return; |
| 362 | 362 |
case 0xd000: /* mov.l @(disp,PC),Rn */ |
| 363 |
tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
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tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
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| 364 | 364 |
gen_op_ldl_T0_T0(ctx); |
| 365 | 365 |
gen_movl_T_rN(cpu_T[0], REG(B11_8)); |
| 366 | 366 |
return; |
| ... | ... | |
| 585 | 585 |
return; |
| 586 | 586 |
case 0x600e: /* exts.b Rm,Rn */ |
| 587 | 587 |
gen_movl_rN_T(cpu_T[0], REG(B7_4)); |
| 588 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
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| 589 |
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
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| 588 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
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| 589 |
tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
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| 590 | 590 |
gen_movl_T_rN(cpu_T[0], REG(B11_8)); |
| 591 | 591 |
return; |
| 592 | 592 |
case 0x600f: /* exts.w Rm,Rn */ |
| 593 | 593 |
gen_movl_rN_T(cpu_T[0], REG(B7_4)); |
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
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| 596 | 596 |
gen_movl_T_rN(cpu_T[0], REG(B11_8)); |
| 597 | 597 |
return; |
| 598 | 598 |
case 0x600c: /* extu.b Rm,Rn */ |
| 599 | 599 |
gen_movl_rN_T(cpu_T[0], REG(B7_4)); |
| 600 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
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| 601 | 601 |
gen_movl_T_rN(cpu_T[0], REG(B11_8)); |
| 602 | 602 |
return; |
| 603 | 603 |
case 0x600d: /* extu.w Rm,Rn */ |
| 604 | 604 |
gen_movl_rN_T(cpu_T[0], REG(B7_4)); |
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
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| 606 | 606 |
gen_movl_T_rN(cpu_T[0], REG(B11_8)); |
| 607 | 607 |
return; |
| 608 | 608 |
case 0x000f: /* mac.l @Rm+,@Rn+ */ |
| 609 | 609 |
gen_movl_rN_T(cpu_T[0], REG(B11_8)); |
| 610 | 610 |
gen_op_ldl_T0_T0(ctx); |
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 612 | 612 |
gen_movl_rN_T(cpu_T[0], REG(B7_4)); |
| 613 | 613 |
gen_op_ldl_T0_T0(ctx); |
| 614 | 614 |
gen_op_macl_T0_T1(); |
| ... | ... | |
| 618 | 618 |
case 0x400f: /* mac.w @Rm+,@Rn+ */ |
| 619 | 619 |
gen_movl_rN_T(cpu_T[0], REG(B11_8)); |
| 620 | 620 |
gen_op_ldl_T0_T0(ctx); |
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 622 | 622 |
gen_movl_rN_T(cpu_T[0], REG(B7_4)); |
| 623 | 623 |
gen_op_ldl_T0_T0(ctx); |
| 624 | 624 |
gen_op_macw_T0_T1(); |
| ... | ... | |
| 632 | 632 |
return; |
| 633 | 633 |
case 0x200f: /* muls.w Rm,Rn */ |
| 634 | 634 |
gen_movl_rN_T(cpu_T[0], REG(B7_4)); |
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
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| 637 | 637 |
gen_movl_rN_T(cpu_T[1], REG(B11_8)); |
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tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);
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tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
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tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
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tcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]);
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| 640 | 640 |
gen_op_mulsw_T0_T1(); |
| 641 | 641 |
return; |
| 642 | 642 |
case 0x200e: /* mulu.w Rm,Rn */ |
| 643 | 643 |
gen_movl_rN_T(cpu_T[0], REG(B7_4)); |
| 644 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
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| 645 | 645 |
gen_movl_rN_T(cpu_T[1], REG(B11_8)); |
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tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);
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tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
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| 647 | 647 |
gen_op_muluw_T0_T1(); |
| 648 | 648 |
return; |
| 649 | 649 |
case 0x600b: /* neg Rm,Rn */ |
| ... | ... | |
| 843 | 843 |
case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
| 844 | 844 |
gen_movl_rN_T(cpu_T[0], REG(0)); |
| 845 | 845 |
gen_op_addl_GBR_T0(); |
| 846 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 847 | 847 |
gen_op_ldub_T0_T0(ctx); |
| 848 | 848 |
gen_op_and_imm_T0(B7_0); |
| 849 | 849 |
gen_op_stb_T0_T1(ctx); |
| ... | ... | |
| 895 | 895 |
case 0xc000: /* mov.b R0,@(disp,GBR) */ |
| 896 | 896 |
gen_op_stc_gbr_T0(); |
| 897 | 897 |
gen_op_addl_imm_T0(B7_0); |
| 898 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 899 | 899 |
gen_movl_rN_T(cpu_T[0], REG(0)); |
| 900 | 900 |
gen_op_stb_T0_T1(ctx); |
| 901 | 901 |
return; |
| 902 | 902 |
case 0xc100: /* mov.w R0,@(disp,GBR) */ |
| 903 | 903 |
gen_op_stc_gbr_T0(); |
| 904 | 904 |
gen_op_addl_imm_T0(B7_0 * 2); |
| 905 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 906 | 906 |
gen_movl_rN_T(cpu_T[0], REG(0)); |
| 907 | 907 |
gen_op_stw_T0_T1(ctx); |
| 908 | 908 |
return; |
| 909 | 909 |
case 0xc200: /* mov.l R0,@(disp,GBR) */ |
| 910 | 910 |
gen_op_stc_gbr_T0(); |
| 911 | 911 |
gen_op_addl_imm_T0(B7_0 * 4); |
| 912 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 913 | 913 |
gen_movl_rN_T(cpu_T[0], REG(0)); |
| 914 | 914 |
gen_op_stl_T0_T1(ctx); |
| 915 | 915 |
return; |
| ... | ... | |
| 947 | 947 |
case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
| 948 | 948 |
gen_movl_rN_T(cpu_T[0], REG(0)); |
| 949 | 949 |
gen_op_addl_GBR_T0(); |
| 950 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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| 950 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 951 | 951 |
gen_op_ldub_T0_T0(ctx); |
| 952 | 952 |
gen_op_or_imm_T0(B7_0); |
| 953 | 953 |
gen_op_stb_T0_T1(ctx); |
| ... | ... | |
| 972 | 972 |
case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
| 973 | 973 |
gen_movl_rN_T(cpu_T[0], REG(0)); |
| 974 | 974 |
gen_op_addl_GBR_T0(); |
| 975 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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| 975 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 976 | 976 |
gen_op_ldub_T0_T0(ctx); |
| 977 | 977 |
gen_op_xor_imm_T0(B7_0); |
| 978 | 978 |
gen_op_stb_T0_T1(ctx); |
| ... | ... | |
| 1142 | 1142 |
return; |
| 1143 | 1143 |
case 0x401b: /* tas.b @Rn */ |
| 1144 | 1144 |
gen_movl_rN_T(cpu_T[0], REG(B11_8)); |
| 1145 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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| 1145 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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| 1146 | 1146 |
gen_op_ldub_T0_T0(ctx); |
| 1147 | 1147 |
gen_op_cmp_eq_imm_T0(0); |
| 1148 | 1148 |
gen_op_or_imm_T0(0x80); |
| ... | ... | |
| 1213 | 1213 |
break; |
| 1214 | 1214 |
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
| 1215 | 1215 |
if (!(ctx->fpscr & FPSCR_PR)) {
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| 1216 |
tcg_gen_movi_tl(cpu_T[0], 0);
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| 1216 |
tcg_gen_movi_i32(cpu_T[0], 0);
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| 1217 | 1217 |
gen_op_fmov_T0_frN(FREG(B11_8)); |
| 1218 | 1218 |
return; |
| 1219 | 1219 |
} |
| 1220 | 1220 |
break; |
| 1221 | 1221 |
case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
| 1222 | 1222 |
if (!(ctx->fpscr & FPSCR_PR)) {
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| 1223 |
tcg_gen_movi_tl(cpu_T[0], 0x3f800000);
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| 1223 |
tcg_gen_movi_i32(cpu_T[0], 0x3f800000);
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| 1224 | 1224 |
gen_op_fmov_T0_frN(FREG(B11_8)); |
| 1225 | 1225 |
return; |
| 1226 | 1226 |
} |
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