Revision 3c4c9f9f
| b/target-ppc/cpu.h | ||
|---|---|---|
| 693 | 693 |
/* temporary fixed-point registers |
| 694 | 694 |
* used to emulate 64 bits target on 32 bits hosts |
| 695 | 695 |
*/ |
| 696 |
target_ulong t0, t1, t2;
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|
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ppc_gpr_t t0, t1, t2;
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|
| 697 | 697 |
#endif |
| 698 | 698 |
ppc_avr_t t0_avr, t1_avr, t2_avr; |
| 699 | 699 |
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| b/target-ppc/exec.h | ||
|---|---|---|
| 43 | 43 |
register unsigned long T2 asm(AREG3); |
| 44 | 44 |
#endif |
| 45 | 45 |
/* We may, sometime, need 64 bits registers on 32 bits target */ |
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#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64) |
|
| 47 |
#define T0_64 T0 |
|
| 48 |
#define T1_64 T1 |
|
| 49 |
#define T2_64 T2 |
|
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#else |
|
| 46 |
#if TARGET_GPR_BITS > HOST_LONG_BITS |
|
| 51 | 47 |
/* no registers can be used */ |
| 52 | 48 |
#define T0_64 (env->t0) |
| 53 | 49 |
#define T1_64 (env->t1) |
| 54 | 50 |
#define T2_64 (env->t2) |
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#else |
|
| 52 |
#define T0_64 T0 |
|
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#define T1_64 T1 |
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#define T2_64 T2 |
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| 55 | 55 |
#endif |
| 56 | 56 |
/* Provision for Altivec */ |
| 57 | 57 |
#define T0_avr (env->t0_avr) |
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