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target-ppc: simpler definitions for microcontrollers based on e300
No need to alias e300 core for each CPU package.Differences between microcontrollers have to be implemented in a higher layerthan translate_init.c
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>...
target-ppc: add declarations of microcontrollers based on e300
Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: better support of e300 CPU core
Declare HID2 register.
Use high BATs for e300 (8 instead of 4).
Fix index of high BATs registers.Before the fix, IBAT4-7 were overwriting IBAT0-3.
Signed-off-by: François Armand <francois.armand@os4i.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Update to a hopefully more future proof FSF address
target-ppc: enable PPC_MFTB for 44x
According to PPC440 user manual, PPC 440 supports ``mftb'' even it's apreserved instruction:
PPC440_UM2013.pdf, p.445, table A-3
when I compile a kernel (2.6.30, bamboo_defconfig/440EP &canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump...
target-ppc: permit linux-user to read PVR
Access to the PVR SPR is normally forbidden from userspace apps. TheLinux kernel, however, fixes up reads in the appropriate trap handler.To permit applications that read PVR to run on QEMU, then, we need toimplement the same handling of PVR reads....
Replace ELF section hack with normal table
target-ppc: expose cpu capability flags
Do this so other pieces of code can make decisions based on thecapabilities of the CPU we're emulating.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: malc <av1474@comtv.ru>
Fix powerpc 604 reset vector
According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is setfor hreset and the vector is at offset 0x100 from the exception prefix.
No difference in this area between 604 and 604e.
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Fix PPC reset
target-ppc: fix commit r6789
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: free a tcg temp variable
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add support for reading/writing spefscr
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one errors for Altivec and SPE registers
Altivec and SPE both have 34 registers in their register sets, not 35with a missing register 32.
GDB would ask for register 32 of the Altivec (resp. SPE) registers andthe code would claim it had zero width. The QEMU GDB stub code would...
Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.This breaks bridge mode for 970 for now, but at least keeps us fromoverwriting physical addresses 0x0 - 0x300, rendering our interrupthandlers useless.
I put in a stub for bridge mode operation that could be enabled...
Nop some SPRs on 970fx
Linux tries to access some SPRs on PPC64 boot. Let's just ignore thosefor the 970fx for now to make it happy.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: improve mfcr/mtcrf
- use ctz32 instead of ffs - 1- small optimisation of mtcrf- add the name of both opcodes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
kvm/powerpc: Add irq support for E500 core
Signed-off-by: Liu Yu <yu.liu@freescale.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
Implement HIOR
A real 970 CPU starts up with HIOR=0xfff00000 and triggers a resetexception, basically ending up at IP 0xfff001000.
Later on this HIOR has to be set to 0 by the firmware in order toenable the OS to handle interrupts on its own.
This patch maps HIOR to exec_prefix, which does the same thing...
target-ppc: Model e500v{1,2} CPUs more accurately
The e500v1 chips only have single-precision floating point; don't say wesupport the double-precision floating-point instructions on such chips.Also add an e500v1 -cpu argument for a generic e500v1.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions shouldbe separated into their own categories, since some chips only supportsingle-precision instructions.
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Add calls to initialize VSCR on appropriate machines
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6507 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add SPE register read/write using XML
Don't read/write SPEFSCR until we figure out what to do about exceptions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add Altivec register read/write using XML
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6424 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add float register read/write using XML
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Include gdbstub.h
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6422 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: rework exception code
... also remove two warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SPR accesses to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
Attached patch fixes a series of this warningwhen compiling on NetBSD:
warning: array subscript has type 'char'
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5727 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually toavoid defining 5 32-bit registers (TCG doesn't permit to map 8-bitregisters).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: Convert ctr, lr moves to TCG
Introduce TCG variables cpu_{ctr,lr} and replace op_{load,store}_{lr,ctr}with tcg_gen_mov_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5217 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
Fix PowerPC 74xx definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162
Fix PowerPC 7xx definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162
Remove shared macro used to define PowerPC implementations instructions sets: tend more to propagate bugged definition than simplify the code.Check and fix PowerPC 6xx implementations definitions.Misc fixes in PowerPC CPU list.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC 620 MMU do not have the same exact behavior as standard 64 bits PowerPC ones.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162
New PowerPC CPU flag to define the decrementer and time-base source clock.Use it to properly initialize the clock for the PreP target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3701 c046a42c-6fe2-441c-8c8c-71466251a162
Improve PowerPC instructions set dump.Remove meaningless define from cpu.hMisc cleanups.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162
Add definitions for Freescale PowerPC implementations, ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.Make those CPUs and PowerPC 440 available for user-mode emulation, thus providing a way of testing their implementation specific instructions.
...
Define Freescale cores specific MMU model, exceptions and input bus. (but do not provide any actual implementation).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162
A little more granularity in PowerPC instructions definition is needed in order to implement Freescale cores.Fix efsadd / efssub opcodes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3679 c046a42c-6fe2-441c-8c8c-71466251a162
Make the PowerPC MMU model, exception model and input bus model typedefed enums.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162
Always make all PowerPC exception definitions visible.Always make the hypervisor timers available.Remove all TARGET_PPC64H checks, keeping a few if (0) tests for casesthat cannot be properly handled with the current PowerPC CPU definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
Reorganize PowerPC instructions categories, add icbi separate case.Fix frsqrtes instruction opcode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3636 c046a42c-6fe2-441c-8c8c-71466251a162
Add PVR and SPR definition for most embedded PowerPC from Freescale.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3632 c046a42c-6fe2-441c-8c8c-71466251a162
Allow selection of PowerPC CPU giving a PVR.Remove unused pvr_mask field from CPU definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3571 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC 601 need specific callbacks for its BATs setup.Implement PowerPC 601 HID0 register, needed for little-endian mode support.As a consequence, we need to merge hflags coming from MSR with other ones.Use little-endian mode from hflags instead of MSR during code translation....
Fix PowerPC high BATs access: BAT number was incorrect.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3519 c046a42c-6fe2-441c-8c8c-71466251a162
Implement power-management for all defined PowerPC CPUs.Fix PowerPC 970MP definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3440 c046a42c-6fe2-441c-8c8c-71466251a162
Allow selection of all defined PowerPC 74xx (aka G4) CPUs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3437 c046a42c-6fe2-441c-8c8c-71466251a162
There is no need of a specific MMU model for PowerPC 601.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162
Remove synonymous in PowerPC MSR bits definitions.Fix MSR EP bit buggy definition.Remove unuseful MSR flags.Fix MSR bits and flags definitions for most supported PowerPC implementations.Add MSR definitions/flags constistency checks and optional dump....
Real-mode only PowerPC 40x do not have any TLBs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3353 c046a42c-6fe2-441c-8c8c-71466251a162
Implement exception prefix feature for PowerPC 601.Fix PowerPC 601 hardware reset vector.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3352 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing exception vectors for PowerPC 7x5.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3351 c046a42c-6fe2-441c-8c8c-71466251a162
Work-around C89 and/or "old" gcc unspecified behavior (#if in macro calls).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3350 c046a42c-6fe2-441c-8c8c-71466251a162
Reorganize the CPUPPCState structure to group features.Add #ifdef to avoid compiling not relevant resources:- MMU related stuff for user-mode only targets- PowerPC 64 only resources for PowerPC 32 targets- embedded PowerPC extensions for non-ppcemb targets....
Add MSR bits signification per PowerPC implementation flags (to be continued).As a side effect, single step and branch step are available again.Remove irrelevant MSR bits definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3342 c046a42c-6fe2-441c-8c8c-71466251a162
Full implementation of PowerPC 64 MMU, just missing support for 1 TB memory segments.Remove the PowerPC 64 "bridge" MMU model and implement segment registers emulation using SLB entries instead.Make SLB area size implementation dependant.Improve TLB & SLB search debug traces....
Rename PowerPC MMUCSR0 and MMUCFG SPRs: those are not BookE specific.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3333 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC hardware reset vector is now considered as part of the exception model.Use it at CPU initialisation time.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3332 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3322 c046a42c-6fe2-441c-8c8c-71466251a162
Make PowerPC cache line size implementation dependant.Implement dcbz tunable cache line size for PowerPC 970.Make hardware reset vector implementation dependant.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162
HID0 is a write-clear register on 970 (DBSR).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3320 c046a42c-6fe2-441c-8c8c-71466251a162
We never have to export ppc_set_irq.Protect PowerPC 64 only features with #ifdef (TARGET_PPC64)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3316 c046a42c-6fe2-441c-8c8c-71466251a162
More comments about unimplemented SPRs.Tag unused functions with unused attribute instead of using #ifdef (TODO) to ease tests: just have to enable the implementation in the cpu_defs table.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3306 c046a42c-6fe2-441c-8c8c-71466251a162
Share more SPR instanciations between all PowerPC 401 incarnations.Add comments about some unimplemented storage control dedicated SPRs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3301 c046a42c-6fe2-441c-8c8c-71466251a162
Implement embedded PowerPC exceptions prefix and vectors registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3300 c046a42c-6fe2-441c-8c8c-71466251a162
Share input pins and internal interrupt controller between all PowerPC 40x.Fix critical input interrupt generation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3299 c046a42c-6fe2-441c-8c8c-71466251a162
Fix inconsistent end conditions in ppc_find_xxx functions. (crash reported by Andreas Farber when using default CPU).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3293 c046a42c-6fe2-441c-8c8c-71466251a162
Implement the PowerPC alternate time-base, following the 2.04 specification.Share most code with the time-base management routines.Remove time-base write routines from user-mode emulation environments.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3277 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC emulation optimization:avoid stopping translation after most SPR updateswhen a context-synchronization instruction is also needed.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3265 c046a42c-6fe2-441c-8c8c-71466251a162
Define the proper bfd_mach to be used by the disassembler for eachPowerPC emulated CPU.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3257 c046a42c-6fe2-441c-8c8c-71466251a162
Change POWERPC_PPC_GENERIC to POWERPC_DEFAULT.Use it as default for workstation targets.Fix PowerPC 750fl and 750gl definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3256 c046a42c-6fe2-441c-8c8c-71466251a162
Build fix for PowerPC hosts, where "PPC" is a predefined macro name.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3251 c046a42c-6fe2-441c-8c8c-71466251a162
New ppc64-linux-user target.Allow use of PowerPC 970 for debugging (softmmu would not run, for now).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3246 c046a42c-6fe2-441c-8c8c-71466251a162
More PowerPC definitions, from POWER 2.04 specifications and misc sources.Check that at least instructions set and SPRs are correct for PowerPC 401, 403, 405 and 440 cores.Implement PowerPC 401 MMU model (real-mode only).Improve INSNs and SPRs dump to ease parse with standard shell tools....
Coding style fixes in PowerPC related code (no functional change):- avoid useless blanks at EOL.- avoid tabs.- fix wrapping lines on 80 chars terminals.- add missing ';' at macros EOL to avoid confusing auto-identers.- fix identation.- Remove historical macros in micro-ops (PARAM, SPARAM, PPC_OP, regs)...
find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Disable dead code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3071 c046a42c-6fe2-441c-8c8c-71466251a162
Improve PowerPC 405 MMU model / share more code for other embedded targetssupport.Fix PowerPC 405 MSR mask.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2717 c046a42c-6fe2-441c-8c8c-71466251a162
Duplicated SPR fix for BookE PowerPC by Guglielmo Morandin
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2704 c046a42c-6fe2-441c-8c8c-71466251a162
Move PowerPC 405 specific definitions into a separate filePreliminary code for -kernel option support for PowerPC 405 boardsFix DBSR in case of PowerPC 405 chip resetAdd enums for PowerPC 405 clocks.Fix IRQ numbers (IBM reversed bits numbering...)Fix SPRG4-7 read access right...
Add callbacks to allow dynamic change of PowerPC clocks (to be improved)Fix embedded PowerPC watchdog and timersFix PowerPC 405 SPRAdd generic PowerPC 405 core instanciation code + resets support.Implement simple peripherals shared by most PowerPC 405 implementations...
Cleanup and add more PowerPC core definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2684 c046a42c-6fe2-441c-8c8c-71466251a162
Add reset callbacks for PowerPC CPU.Move cpu_ppc_init, cpu_ppc_close, cpu_ppc_reset and ppc_tlb_invalidateinto helper.c as they are to be called from outside of the translated code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2682 c046a42c-6fe2-441c-8c8c-71466251a162
Add bus model (or input pins) into PowerPC CPU flags.Add PowerPC 970 bus and exceptions model.Add code provision for PowerPC 970 instanciation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2680 c046a42c-6fe2-441c-8c8c-71466251a162