Archipelago » qemu

    *flags = env->iflags & IFLAGS_TB_MASK;

}

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

                          int is_asi, int size);

#endif

{

    mmu_write(env, rn, v);

}

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

                          int is_asi, int size)

    }

    env = saved_env;

}

    target_ulong PFN[2];

};

typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;

struct CPUMIPSTLBContext {

    uint32_t nb_tlb;

        } r4k;

    } mmu;

};

typedef union fpr_t fpr_t;

union fpr_t {

    CPU_COMMON

    CPUMIPSMVPContext *mvp;

    CPUMIPSTLBContext *tlb;

    const mips_def_t *cpu_model;

    void *irq[8];

    struct QEMUTimer *timer; /* Internal timer */

};

int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,

                        target_ulong address, int rw, int access_type);

int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,

void r4k_helper_tlbwr (void);

void r4k_helper_tlbp (void);

void r4k_helper_tlbr (void);

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

                          int unused, int size);

#define cpu_init cpu_mips_init

#define cpu_exec cpu_mips_exec

                               int mmu_idx, int is_softmmu);

#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault

void do_interrupt (CPUState *env);

void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);

target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,

		                               int rw);

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)

{

    TLBRET_MATCH = 0

};

/* no MMU emulation */

int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,

                        target_ulong address, int rw, int access_type)

    return TLBRET_NOMATCH;

}

static int get_physical_address (CPUState *env, target_phys_addr_t *physical,

                                int *prot, target_ulong address,

                                int rw, int access_type)

    env->exception_index = EXCP_NONE;

}

void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)

{

    r4k_tlb_t *tlb;

        }

    }

}

    uint64_t u64[2];

};

/* Software TLB cache */

typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;

struct ppc6xx_tlb_t {

    ppc6xx_tlb_t tlb6;

    ppcemb_tlb_t tlbe;

};

typedef struct ppc_slb_t ppc_slb_t;

struct ppc_slb_t {

    int (*osi_call)(struct CPUPPCState *env);

};

/* Context used internally during MMU translations */

typedef struct mmu_ctx_t mmu_ctx_t;

struct mmu_ctx_t {

    int key;                       /* Access key                */

    int nx;                        /* Non-execute area          */

};

/*****************************************************************************/

CPUPPCState *cpu_ppc_init (const char *cpu_model);

int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,

                              int mmu_idx, int is_softmmu);

#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault

int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,

                          int rw, int access_type);

void do_interrupt (CPUPPCState *env);

void ppc_hw_interrupt (CPUPPCState *env);

void do_interrupt(CPUSH4State * env);

void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

void cpu_sh4_invalidate_tlb(CPUSH4State *s);

void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,

				    uint32_t mem_value);

int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);

#endif

/* cpu-exec.c */

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

                          int is_asi, int size);

int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

#define cpu_init cpu_sparc_init

#endif

#endif

#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)

// Calculates TSB pointer value for fault page size 8k or 64k

static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,

    env = saved_env;

}

#ifndef TARGET_SPARC64

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

                          int is_asi, int size)

{

    env = saved_env;

}

#else

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

                          int is_asi, int size)

{

    CPUState *saved_env;

}

#endif

#ifdef TARGET_SPARC64

void helper_tick_set_count(void *opaque, uint64_t count)

{