Archipelago » qemu

    target_ulong PFN[2];

};

typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;

struct CPUMIPSTLBContext {

    uint32_t nb_tlb;

        } r4k;

    } mmu;

};

typedef union fpr_t fpr_t;

union fpr_t {

    CPU_COMMON

    CPUMIPSMVPContext *mvp;

    CPUMIPSTLBContext *tlb;

    const mips_def_t *cpu_model;

    void *irq[8];

    struct QEMUTimer *timer; /* Internal timer */

};

int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,

                        target_ulong address, int rw, int access_type);

int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,

void r4k_helper_tlbwr (void);

void r4k_helper_tlbp (void);

void r4k_helper_tlbr (void);

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

                          int unused, int size);

#define cpu_init cpu_mips_init

#define cpu_exec cpu_mips_exec

                               int mmu_idx, int is_softmmu);

#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault

void do_interrupt (CPUState *env);

void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);

target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,

		                               int rw);

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)

{