Revision 3cbee15b hw/ppc_chrp.c
b/hw/ppc_chrp.c | ||
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1 | 1 |
/* |
2 |
* QEMU PPC CHRP/PMAC hardware System Emulator
|
|
2 |
* QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
|
|
3 | 3 |
* |
4 | 4 |
* Copyright (c) 2004-2007 Fabrice Bellard |
5 |
* Copyright (c) 2007 Jocelyn Mayer |
|
5 | 6 |
* |
6 | 7 |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | 8 |
* of this software and associated documentation files (the "Software"), to deal |
... | ... | |
22 | 23 |
* THE SOFTWARE. |
23 | 24 |
*/ |
24 | 25 |
#include "vl.h" |
25 |
|
|
26 |
/* SMP is not enabled, for now */ |
|
27 |
#define MAX_CPUS 1 |
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28 |
|
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#define BIOS_FILENAME "ppc_rom.bin" |
|
30 |
#define VGABIOS_FILENAME "video.x" |
|
31 |
#define NVRAM_SIZE 0x2000 |
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32 |
|
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#define KERNEL_LOAD_ADDR 0x01000000 |
|
34 |
#define INITRD_LOAD_ADDR 0x01800000 |
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35 |
|
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/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA, |
|
37 |
NVRAM */ |
|
38 |
|
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39 |
static int dbdma_mem_index; |
|
40 |
static int cuda_mem_index; |
|
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static int ide0_mem_index = -1; |
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42 |
static int ide1_mem_index = -1; |
|
43 |
static int openpic_mem_index = -1; |
|
44 |
static int heathrow_pic_mem_index = -1; |
|
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static int macio_nvram_mem_index = -1; |
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46 |
|
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/* DBDMA: currently no op - should suffice right now */ |
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48 |
|
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49 |
static void dbdma_writeb (void *opaque, |
|
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target_phys_addr_t addr, uint32_t value) |
|
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{ |
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printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value); |
|
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} |
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54 |
|
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55 |
static void dbdma_writew (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
|
57 |
{ |
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58 |
} |
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59 |
|
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60 |
static void dbdma_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
|
62 |
{ |
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63 |
} |
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64 |
|
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65 |
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) |
|
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{ |
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printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr); |
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68 |
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return 0; |
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70 |
} |
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71 |
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72 |
static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) |
|
73 |
{ |
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74 |
return 0; |
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75 |
} |
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76 |
|
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static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) |
|
78 |
{ |
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79 |
return 0; |
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80 |
} |
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81 |
|
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82 |
static CPUWriteMemoryFunc *dbdma_write[] = { |
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83 |
&dbdma_writeb, |
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&dbdma_writew, |
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85 |
&dbdma_writel, |
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86 |
}; |
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87 |
|
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88 |
static CPUReadMemoryFunc *dbdma_read[] = { |
|
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&dbdma_readb, |
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&dbdma_readw, |
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&dbdma_readl, |
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}; |
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93 |
|
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94 |
/* macio style NVRAM device */ |
|
95 |
typedef struct MacIONVRAMState { |
|
96 |
uint8_t data[0x2000]; |
|
97 |
} MacIONVRAMState; |
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98 |
|
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static void macio_nvram_writeb (void *opaque, |
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100 |
target_phys_addr_t addr, uint32_t value) |
|
101 |
{ |
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102 |
MacIONVRAMState *s = opaque; |
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103 |
addr = (addr >> 4) & 0x1fff; |
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s->data[addr] = value; |
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105 |
// printf("macio_nvram_writeb %04x = %02x\n", addr, value); |
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} |
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107 |
|
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108 |
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) |
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109 |
{ |
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MacIONVRAMState *s = opaque; |
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uint32_t value; |
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112 |
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addr = (addr >> 4) & 0x1fff; |
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value = s->data[addr]; |
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115 |
// printf("macio_nvram_readb %04x = %02x\n", addr, value); |
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116 |
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117 |
return value; |
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118 |
} |
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119 |
|
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120 |
static CPUWriteMemoryFunc *macio_nvram_write[] = { |
|
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&macio_nvram_writeb, |
|
122 |
&macio_nvram_writeb, |
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&macio_nvram_writeb, |
|
124 |
}; |
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125 |
|
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126 |
static CPUReadMemoryFunc *macio_nvram_read[] = { |
|
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&macio_nvram_readb, |
|
128 |
&macio_nvram_readb, |
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129 |
&macio_nvram_readb, |
|
130 |
}; |
|
131 |
|
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132 |
static MacIONVRAMState *macio_nvram_init (void) |
|
133 |
{ |
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134 |
MacIONVRAMState *s; |
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135 |
s = qemu_mallocz(sizeof(MacIONVRAMState)); |
|
136 |
if (!s) |
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137 |
return NULL; |
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138 |
macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read, |
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139 |
macio_nvram_write, s); |
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140 |
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141 |
return s; |
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142 |
} |
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143 |
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144 |
static void macio_map (PCIDevice *pci_dev, int region_num, |
|
145 |
uint32_t addr, uint32_t size, int type) |
|
146 |
{ |
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147 |
if (heathrow_pic_mem_index >= 0) { |
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148 |
cpu_register_physical_memory(addr + 0x00000, 0x1000, |
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149 |
heathrow_pic_mem_index); |
|
150 |
} |
|
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cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index); |
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cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index); |
|
153 |
if (ide0_mem_index >= 0) |
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154 |
cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index); |
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155 |
if (ide1_mem_index >= 0) |
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156 |
cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index); |
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157 |
if (openpic_mem_index >= 0) { |
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158 |
cpu_register_physical_memory(addr + 0x40000, 0x40000, |
|
159 |
openpic_mem_index); |
|
160 |
} |
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161 |
if (macio_nvram_mem_index >= 0) |
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162 |
cpu_register_physical_memory(addr + 0x60000, 0x20000, |
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163 |
macio_nvram_mem_index); |
|
164 |
} |
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165 |
|
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166 |
static void macio_init (PCIBus *bus, int device_id) |
|
167 |
{ |
|
168 |
PCIDevice *d; |
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169 |
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170 |
d = pci_register_device(bus, "macio", sizeof(PCIDevice), |
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171 |
-1, NULL, NULL); |
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172 |
/* Note: this code is strongly inspirated from the corresponding code |
|
173 |
in PearPC */ |
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174 |
d->config[0x00] = 0x6b; // vendor_id |
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175 |
d->config[0x01] = 0x10; |
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176 |
d->config[0x02] = device_id; |
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177 |
d->config[0x03] = device_id >> 8; |
|
178 |
|
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179 |
d->config[0x0a] = 0x00; // class_sub = pci2pci |
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180 |
d->config[0x0b] = 0xff; // class_base = bridge |
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181 |
d->config[0x0e] = 0x00; // header_type |
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182 |
|
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183 |
d->config[0x3d] = 0x01; // interrupt on pin 1 |
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184 |
|
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185 |
dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL); |
|
186 |
|
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187 |
pci_register_io_region(d, 0, 0x80000, |
|
188 |
PCI_ADDRESS_SPACE_MEM, macio_map); |
|
189 |
} |
|
26 |
#include "ppc_mac.h" |
|
190 | 27 |
|
191 | 28 |
/* UniN device */ |
192 | 29 |
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
... | ... | |
210 | 47 |
&unin_readl, |
211 | 48 |
}; |
212 | 49 |
|
213 |
/* temporary frame buffer OSI calls for the video.x driver. The right |
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214 |
solution is to modify the driver to use VGA PCI I/Os */ |
|
215 |
/* XXX: to be removed. This is no way related to emulation */ |
|
216 |
static int vga_osi_call (CPUState *env) |
|
217 |
{ |
|
218 |
static int vga_vbl_enabled; |
|
219 |
int linesize; |
|
220 |
|
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221 |
// printf("osi_call R5=%d\n", env->gpr[5]); |
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222 |
|
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223 |
/* same handler as PearPC, coming from the original MOL video |
|
224 |
driver. */ |
|
225 |
switch(env->gpr[5]) { |
|
226 |
case 4: |
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227 |
break; |
|
228 |
case 28: /* set_vmode */ |
|
229 |
if (env->gpr[6] != 1 || env->gpr[7] != 0) |
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230 |
env->gpr[3] = 1; |
|
231 |
else |
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232 |
env->gpr[3] = 0; |
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233 |
break; |
|
234 |
case 29: /* get_vmode_info */ |
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235 |
if (env->gpr[6] != 0) { |
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236 |
if (env->gpr[6] != 1 || env->gpr[7] != 0) { |
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237 |
env->gpr[3] = 1; |
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238 |
break; |
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239 |
} |
|
240 |
} |
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241 |
env->gpr[3] = 0; |
|
242 |
env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ |
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243 |
env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ |
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244 |
env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ |
|
245 |
env->gpr[7] = 85 << 16; /* refresh rate */ |
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env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ |
|
247 |
linesize = ((graphic_depth + 7) >> 3) * graphic_width; |
|
248 |
linesize = (linesize + 3) & ~3; |
|
249 |
env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ |
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250 |
break; |
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251 |
case 31: /* set_video power */ |
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252 |
env->gpr[3] = 0; |
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253 |
break; |
|
254 |
case 39: /* video_ctrl */ |
|
255 |
if (env->gpr[6] == 0 || env->gpr[6] == 1) |
|
256 |
vga_vbl_enabled = env->gpr[6]; |
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257 |
env->gpr[3] = 0; |
|
258 |
break; |
|
259 |
case 47: |
|
260 |
break; |
|
261 |
case 59: /* set_color */ |
|
262 |
/* R6 = index, R7 = RGB */ |
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263 |
env->gpr[3] = 0; |
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264 |
break; |
|
265 |
case 64: /* get color */ |
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266 |
/* R6 = index */ |
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267 |
env->gpr[3] = 0; |
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268 |
break; |
|
269 |
case 116: /* set hwcursor */ |
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270 |
/* R6 = x, R7 = y, R8 = visible, R9 = data */ |
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271 |
break; |
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default: |
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273 |
fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]); |
|
274 |
break; |
|
275 |
} |
|
276 |
|
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277 |
return 1; /* osi_call handled */ |
|
278 |
} |
|
279 |
|
|
280 |
static uint8_t nvram_chksum (const uint8_t *buf, int n) |
|
281 |
{ |
|
282 |
int sum, i; |
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283 |
sum = 0; |
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284 |
for(i = 0; i < n; i++) |
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285 |
sum += buf[i]; |
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286 |
return (sum & 0xff) + (sum >> 8); |
|
287 |
} |
|
288 |
|
|
289 |
/* set a free Mac OS NVRAM partition */ |
|
290 |
void pmac_format_nvram_partition (uint8_t *buf, int len) |
|
291 |
{ |
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292 |
char partition_name[12] = "wwwwwwwwwwww"; |
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293 |
|
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294 |
buf[0] = 0x7f; /* free partition magic */ |
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295 |
buf[1] = 0; /* checksum */ |
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296 |
buf[2] = len >> 8; |
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297 |
buf[3] = len; |
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298 |
memcpy(buf + 4, partition_name, 12); |
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299 |
buf[1] = nvram_chksum(buf, 16); |
|
300 |
} |
|
301 |
|
|
302 |
/* PowerPC CHRP hardware initialisation */ |
|
303 |
static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, |
|
304 |
DisplayState *ds, const char **fd_filename, |
|
305 |
int snapshot, |
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306 |
const char *kernel_filename, |
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307 |
const char *kernel_cmdline, |
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308 |
const char *initrd_filename, |
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309 |
const char *cpu_model, |
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310 |
int is_heathrow) |
|
50 |
/* PowerPC Mac99 hardware initialisation */ |
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51 |
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device, |
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52 |
DisplayState *ds, const char **fd_filename, |
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53 |
int snapshot, |
|
54 |
const char *kernel_filename, |
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55 |
const char *kernel_cmdline, |
|
56 |
const char *initrd_filename, |
|
57 |
const char *cpu_model) |
|
311 | 58 |
{ |
312 | 59 |
CPUState *env, *envs[MAX_CPUS]; |
313 | 60 |
char buf[1024]; |
314 | 61 |
qemu_irq *pic, **openpic_irqs; |
315 |
m48t59_t *nvram; |
|
316 | 62 |
int unin_memory; |
317 | 63 |
int linux_boot, i; |
318 | 64 |
unsigned long bios_offset, vga_bios_offset; |
319 | 65 |
uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
320 | 66 |
ppc_def_t *def; |
321 | 67 |
PCIBus *pci_bus; |
322 |
const char *arch_name; |
|
68 |
nvram_t nvram; |
|
69 |
#if 0 |
|
70 |
MacIONVRAMState *nvr; |
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71 |
int nvram_mem_index; |
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72 |
#endif |
|
73 |
m48t59_t *m48t59; |
|
323 | 74 |
int vga_bios_size, bios_size; |
324 | 75 |
qemu_irq *dummy_irq; |
76 |
int pic_mem_index, dbdma_mem_index, cuda_mem_index; |
|
77 |
int ide_mem_index[2]; |
|
325 | 78 |
|
326 | 79 |
linux_boot = (kernel_filename != NULL); |
327 | 80 |
|
... | ... | |
338 | 91 |
cpu_ppc_reset(env); |
339 | 92 |
/* Set time-base frequency to 100 Mhz */ |
340 | 93 |
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
94 |
#if 0 |
|
341 | 95 |
env->osi_call = vga_osi_call; |
96 |
#endif |
|
342 | 97 |
qemu_register_reset(&cpu_ppc_reset, env); |
343 | 98 |
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
344 | 99 |
envs[i] = env; |
... | ... | |
413 | 168 |
initrd_size = 0; |
414 | 169 |
} |
415 | 170 |
|
416 |
if (is_heathrow) { |
|
417 |
isa_mem_base = 0x80000000; |
|
418 |
|
|
419 |
/* Register 2 MB of ISA IO space */ |
|
420 |
isa_mmio_init(0xfe000000, 0x00200000); |
|
171 |
isa_mem_base = 0x80000000; |
|
421 | 172 |
|
422 |
/* init basic PC hardware */ |
|
423 |
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
|
424 |
cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n"); |
|
425 |
exit(1); |
|
426 |
} |
|
427 |
pic = heathrow_pic_init(&heathrow_pic_mem_index); |
|
428 |
pci_bus = pci_grackle_init(0xfec00000, pic); |
|
429 |
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
|
430 |
ram_size, vga_ram_size, |
|
431 |
vga_bios_offset, vga_bios_size); |
|
432 |
|
|
433 |
/* XXX: suppress that */ |
|
434 |
dummy_irq = i8259_init(NULL); |
|
435 |
|
|
436 |
/* XXX: use Mac Serial port */ |
|
437 |
serial_init(0x3f8, dummy_irq[4], serial_hds[0]); |
|
438 |
|
|
439 |
for(i = 0; i < nb_nics; i++) { |
|
440 |
if (!nd_table[i].model) |
|
441 |
nd_table[i].model = "ne2k_pci"; |
|
442 |
pci_nic_init(pci_bus, &nd_table[i], -1); |
|
443 |
} |
|
173 |
/* Register 8 MB of ISA IO space */ |
|
174 |
isa_mmio_init(0xf2000000, 0x00800000); |
|
444 | 175 |
|
445 |
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
|
446 |
|
|
447 |
/* cuda also initialize ADB */ |
|
448 |
cuda_mem_index = cuda_init(pic[0x12]); |
|
449 |
|
|
450 |
adb_kbd_init(&adb_bus); |
|
451 |
adb_mouse_init(&adb_bus); |
|
452 |
|
|
453 |
{ |
|
454 |
MacIONVRAMState *nvr; |
|
455 |
nvr = macio_nvram_init(); |
|
456 |
pmac_format_nvram_partition(nvr->data, 0x2000); |
|
457 |
} |
|
458 |
|
|
459 |
macio_init(pci_bus, 0x0017); |
|
460 |
|
|
461 |
nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
|
462 |
|
|
463 |
arch_name = "HEATHROW"; |
|
464 |
} else { |
|
465 |
isa_mem_base = 0x80000000; |
|
176 |
/* UniN init */ |
|
177 |
unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); |
|
178 |
cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); |
|
466 | 179 |
|
467 |
/* Register 8 MB of ISA IO space */ |
|
468 |
isa_mmio_init(0xf2000000, 0x00800000); |
|
469 |
|
|
470 |
/* UniN init */ |
|
471 |
unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); |
|
472 |
cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); |
|
473 |
|
|
474 |
openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); |
|
475 |
openpic_irqs[0] = |
|
476 |
qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); |
|
477 |
for (i = 0; i < smp_cpus; i++) { |
|
478 |
/* Mac99 IRQ connection between OpenPIC outputs pins |
|
479 |
* and PowerPC input pins |
|
480 |
*/ |
|
481 |
switch (PPC_INPUT(env)) { |
|
482 |
case PPC_FLAGS_INPUT_6xx: |
|
483 |
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); |
|
484 |
openpic_irqs[i][OPENPIC_OUTPUT_INT] = |
|
485 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
|
486 |
openpic_irqs[i][OPENPIC_OUTPUT_CINT] = |
|
487 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
|
488 |
openpic_irqs[i][OPENPIC_OUTPUT_MCK] = |
|
489 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; |
|
490 |
/* Not connected ? */ |
|
491 |
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; |
|
492 |
/* Check this */ |
|
493 |
openpic_irqs[i][OPENPIC_OUTPUT_RESET] = |
|
494 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; |
|
495 |
break; |
|
180 |
openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); |
|
181 |
openpic_irqs[0] = |
|
182 |
qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); |
|
183 |
for (i = 0; i < smp_cpus; i++) { |
|
184 |
/* Mac99 IRQ connection between OpenPIC outputs pins |
|
185 |
* and PowerPC input pins |
|
186 |
*/ |
|
187 |
switch (PPC_INPUT(env)) { |
|
188 |
case PPC_FLAGS_INPUT_6xx: |
|
189 |
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); |
|
190 |
openpic_irqs[i][OPENPIC_OUTPUT_INT] = |
|
191 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
|
192 |
openpic_irqs[i][OPENPIC_OUTPUT_CINT] = |
|
193 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
|
194 |
openpic_irqs[i][OPENPIC_OUTPUT_MCK] = |
|
195 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; |
|
196 |
/* Not connected ? */ |
|
197 |
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; |
|
198 |
/* Check this */ |
|
199 |
openpic_irqs[i][OPENPIC_OUTPUT_RESET] = |
|
200 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; |
|
201 |
break; |
|
496 | 202 |
#if defined(TARGET_PPC64) |
497 |
case PPC_FLAGS_INPUT_970:
|
|
498 |
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
|
|
499 |
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
|
|
500 |
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
|
|
501 |
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
|
|
502 |
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
|
|
503 |
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
|
|
504 |
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
|
|
505 |
/* Not connected ? */
|
|
506 |
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
|
|
507 |
/* Check this */
|
|
508 |
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
|
|
509 |
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
|
|
510 |
break;
|
|
203 |
case PPC_FLAGS_INPUT_970: |
|
204 |
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); |
|
205 |
openpic_irqs[i][OPENPIC_OUTPUT_INT] = |
|
206 |
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; |
|
207 |
openpic_irqs[i][OPENPIC_OUTPUT_CINT] = |
|
208 |
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; |
|
209 |
openpic_irqs[i][OPENPIC_OUTPUT_MCK] = |
|
210 |
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; |
|
211 |
/* Not connected ? */ |
|
212 |
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; |
|
213 |
/* Check this */ |
|
214 |
openpic_irqs[i][OPENPIC_OUTPUT_RESET] = |
|
215 |
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; |
|
216 |
break; |
|
511 | 217 |
#endif /* defined(TARGET_PPC64) */ |
512 |
default: |
|
513 |
cpu_abort(env, "Bus model not supported on mac99 machine\n"); |
|
514 |
exit(1); |
|
515 |
} |
|
516 |
} |
|
517 |
pic = openpic_init(NULL, &openpic_mem_index, smp_cpus, |
|
518 |
openpic_irqs, NULL); |
|
519 |
pci_bus = pci_pmac_init(pic); |
|
520 |
/* init basic PC hardware */ |
|
521 |
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
|
522 |
ram_size, vga_ram_size, |
|
523 |
vga_bios_offset, vga_bios_size); |
|
524 |
|
|
525 |
/* XXX: suppress that */ |
|
526 |
dummy_irq = i8259_init(NULL); |
|
527 |
|
|
528 |
/* XXX: use Mac Serial port */ |
|
529 |
serial_init(0x3f8, dummy_irq[4], serial_hds[0]); |
|
530 |
for(i = 0; i < nb_nics; i++) { |
|
531 |
if (!nd_table[i].model) |
|
532 |
nd_table[i].model = "ne2k_pci"; |
|
533 |
pci_nic_init(pci_bus, &nd_table[i], -1); |
|
218 |
default: |
|
219 |
cpu_abort(env, "Bus model not supported on mac99 machine\n"); |
|
220 |
exit(1); |
|
534 | 221 |
} |
222 |
} |
|
223 |
pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); |
|
224 |
pci_bus = pci_pmac_init(pic); |
|
225 |
/* init basic PC hardware */ |
|
226 |
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
|
227 |
ram_size, vga_ram_size, |
|
228 |
vga_bios_offset, vga_bios_size); |
|
229 |
|
|
230 |
/* XXX: suppress that */ |
|
231 |
dummy_irq = i8259_init(NULL); |
|
232 |
|
|
233 |
/* XXX: use Mac Serial port */ |
|
234 |
serial_init(0x3f8, dummy_irq[4], serial_hds[0]); |
|
235 |
for(i = 0; i < nb_nics; i++) { |
|
236 |
if (!nd_table[i].model) |
|
237 |
nd_table[i].model = "ne2k_pci"; |
|
238 |
pci_nic_init(pci_bus, &nd_table[i], -1); |
|
239 |
} |
|
535 | 240 |
#if 1 |
536 |
ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]);
|
|
537 |
ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]);
|
|
241 |
ide_mem_index[0] = pmac_ide_init(&bs_table[0], pic[0x13]);
|
|
242 |
ide_mem_index[1] = pmac_ide_init(&bs_table[2], pic[0x14]);
|
|
538 | 243 |
#else |
539 |
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
|
|
244 |
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
|
540 | 245 |
#endif |
541 |
/* cuda also initialize ADB */ |
|
542 |
cuda_mem_index = cuda_init(pic[0x19]); |
|
543 |
|
|
544 |
adb_kbd_init(&adb_bus); |
|
545 |
adb_mouse_init(&adb_bus); |
|
546 |
|
|
547 |
macio_init(pci_bus, 0x0022); |
|
246 |
/* cuda also initialize ADB */ |
|
247 |
cuda_init(&cuda_mem_index, pic[0x19]); |
|
248 |
|
|
249 |
adb_kbd_init(&adb_bus); |
|
250 |
adb_mouse_init(&adb_bus); |
|
548 | 251 |
|
549 |
nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
|
|
252 |
dbdma_init(&dbdma_mem_index);
|
|
550 | 253 |
|
551 |
arch_name = "MAC99";
|
|
552 |
}
|
|
254 |
macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index,
|
|
255 |
cuda_mem_index, -1, 2, ide_mem_index);
|
|
553 | 256 |
|
554 | 257 |
if (usb_enabled) { |
555 | 258 |
usb_ohci_init_pci(pci_bus, 3, -1); |
... | ... | |
557 | 260 |
|
558 | 261 |
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
559 | 262 |
graphic_depth = 15; |
560 |
|
|
561 |
PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device, |
|
263 |
#if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */ |
|
264 |
/* The NewWorld NVRAM is not located in the MacIO device */ |
|
265 |
nvr = macio_nvram_init(&nvram_mem_index); |
|
266 |
pmac_format_nvram_partition(nvr, 0x2000); |
|
267 |
cpu_register_physical_memory(0xFFF04000, 0x20000, nvram_mem_index); |
|
268 |
nvram.opaque = nvr; |
|
269 |
nvram.read_fn = &macio_nvram_read; |
|
270 |
nvram.write_fn = &macio_nvram_write; |
|
271 |
#else |
|
272 |
m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
|
273 |
nvram.opaque = m48t59; |
|
274 |
nvram.read_fn = &m48t59_read; |
|
275 |
nvram.write_fn = &m48t59_write; |
|
276 |
#endif |
|
277 |
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", ram_size, boot_device, |
|
562 | 278 |
kernel_base, kernel_size, |
563 | 279 |
kernel_cmdline, |
564 | 280 |
initrd_base, initrd_size, |
... | ... | |
569 | 285 |
|
570 | 286 |
/* Special port to get debug messages from Open-Firmware */ |
571 | 287 |
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
572 |
} |
|
573 |
|
|
574 |
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device, |
|
575 |
DisplayState *ds, const char **fd_filename, |
|
576 |
int snapshot, |
|
577 |
const char *kernel_filename, |
|
578 |
const char *kernel_cmdline, |
|
579 |
const char *initrd_filename, |
|
580 |
const char *cpu_model) |
|
581 |
{ |
|
582 |
ppc_chrp_init(ram_size, vga_ram_size, boot_device, |
|
583 |
ds, fd_filename, snapshot, |
|
584 |
kernel_filename, kernel_cmdline, |
|
585 |
initrd_filename, cpu_model, 0); |
|
586 |
} |
|
587 |
|
|
588 |
static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device, |
|
589 |
DisplayState *ds, const char **fd_filename, |
|
590 |
int snapshot, |
|
591 |
const char *kernel_filename, |
|
592 |
const char *kernel_cmdline, |
|
593 |
const char *initrd_filename, |
|
594 |
const char *cpu_model) |
|
595 |
{ |
|
596 |
ppc_chrp_init(ram_size, vga_ram_size, boot_device, |
|
597 |
ds, fd_filename, snapshot, |
|
598 |
kernel_filename, kernel_cmdline, |
|
599 |
initrd_filename, cpu_model, 1); |
|
600 |
} |
|
288 |
} |
|
601 | 289 |
|
602 | 290 |
QEMUMachine core99_machine = { |
603 | 291 |
"mac99", |
604 | 292 |
"Mac99 based PowerMAC", |
605 | 293 |
ppc_core99_init, |
606 | 294 |
}; |
607 |
|
|
608 |
QEMUMachine heathrow_machine = { |
|
609 |
"g3bw", |
|
610 |
"Heathrow based PowerMAC", |
|
611 |
ppc_heathrow_init, |
|
612 |
}; |
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