Revision 3cd035d8 hw/bitbang_i2c.c
| b/hw/bitbang_i2c.c | ||
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| 7 | 7 |
* This code is licenced under the GNU GPL v2. |
| 8 | 8 |
*/ |
| 9 | 9 |
#include "hw.h" |
| 10 |
#include "i2c.h" |
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| 10 |
#include "bitbang_i2c.h"
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| 11 | 11 |
#include "sysbus.h" |
| 12 | 12 |
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//#define DEBUG_BITBANG_I2C |
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#ifdef DEBUG_BITBANG_I2C |
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#define DPRINTF(fmt, ...) \ |
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do { printf("bitbang_i2c: " fmt , ## __VA_ARGS__); } while (0)
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#else |
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#define DPRINTF(fmt, ...) do {} while(0)
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#endif |
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typedef enum bitbang_i2c_state {
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STOPPED = 0, |
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INITIALIZING, |
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SENDING_BIT7, |
| 17 | 25 |
SENDING_BIT6, |
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SENDING_BIT5, |
| ... | ... | |
| 33 | 41 |
SENDING_ACK |
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} bitbang_i2c_state; |
| 35 | 43 |
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typedef struct bitbang_i2c_interface {
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SysBusDevice busdev; |
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struct bitbang_i2c_interface {
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i2c_bus *bus; |
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bitbang_i2c_state state; |
| 40 | 47 |
int last_data; |
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int last_clock; |
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int device_out; |
|
| 42 | 50 |
uint8_t buffer; |
| 43 | 51 |
int current_addr; |
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qemu_irq out; |
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} bitbang_i2c_interface; |
|
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}; |
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static void bitbang_i2c_enter_stop(bitbang_i2c_interface *i2c) |
| 48 | 55 |
{
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DPRINTF("STOP\n");
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if (i2c->current_addr >= 0) |
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i2c_end_transfer(i2c->bus); |
| 51 | 59 |
i2c->current_addr = -1; |
| 52 | 60 |
i2c->state = STOPPED; |
| 53 | 61 |
} |
| 54 | 62 |
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static void bitbang_i2c_gpio_set(void *opaque, int irq, int level) |
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/* Set device data pin. */ |
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static int bitbang_i2c_ret(bitbang_i2c_interface *i2c, int level) |
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{
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i2c->device_out = level; |
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//DPRINTF("%d %d %d\n", i2c->last_clock, i2c->last_data, i2c->device_out);
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return level & i2c->last_data; |
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} |
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/* Leave device data pin unodified. */ |
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static int bitbang_i2c_nop(bitbang_i2c_interface *i2c) |
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{
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return bitbang_i2c_ret(i2c, i2c->device_out); |
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} |
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/* Returns data line level. */ |
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int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level) |
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{
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bitbang_i2c_interface *i2c = opaque; |
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int data; |
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int clock; |
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int data_goes_up; |
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int data_goes_down; |
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int clock_goes_up; |
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int clock_goes_down; |
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/* get pins states */ |
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data = i2c->last_data; |
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clock = i2c->last_clock; |
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if (irq == 0) |
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data = level; |
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if (irq == 1) |
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clock = level; |
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/* compute pins changes */ |
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data_goes_up = data == 1 && i2c->last_data == 0; |
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data_goes_down = data == 0 && i2c->last_data == 1; |
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clock_goes_up = clock == 1 && i2c->last_clock == 0; |
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clock_goes_down = clock == 0 && i2c->last_clock == 1; |
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if (data_goes_up == 0 && data_goes_down == 0 && |
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clock_goes_up == 0 && clock_goes_down == 0) |
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return; |
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if (!i2c) |
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return; |
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if ((RECEIVING_BIT7 > i2c->state && i2c->state > RECEIVING_BIT0) |
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|| i2c->state == WAITING_FOR_ACK) |
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qemu_set_irq(i2c->out, 0); |
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switch (i2c->state) {
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case STOPPED: |
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if (data_goes_down && clock == 1) |
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i2c->state = INITIALIZING; |
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break; |
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if (level != 0 && level != 1) {
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abort(); |
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} |
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case INITIALIZING: |
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if (clock_goes_down && data == 0) |
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if (line == BITBANG_I2C_SDA) {
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if (level == i2c->last_data) {
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return bitbang_i2c_nop(i2c); |
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} |
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i2c->last_data = level; |
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if (i2c->last_clock == 0) {
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return bitbang_i2c_nop(i2c); |
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} |
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if (level == 0) {
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DPRINTF("START\n");
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/* START condition. */ |
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i2c->state = SENDING_BIT7; |
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else |
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i2c->current_addr = -1; |
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} else {
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/* STOP condition. */ |
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bitbang_i2c_enter_stop(i2c); |
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break; |
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} |
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return bitbang_i2c_ret(i2c, 1); |
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} |
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data = i2c->last_data; |
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if (i2c->last_clock == level) {
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return bitbang_i2c_nop(i2c); |
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} |
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i2c->last_clock = level; |
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if (level == 0) {
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/* State is set/read at the start of the clock pulse. |
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release the data line at the end. */ |
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return bitbang_i2c_ret(i2c, 1); |
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} |
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switch (i2c->state) {
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case STOPPED: |
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return bitbang_i2c_ret(i2c, 1); |
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case SENDING_BIT7 ... SENDING_BIT0: |
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if (clock_goes_down) {
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i2c->buffer = (i2c->buffer << 1) | data; |
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/* will end up in WAITING_FOR_ACK */ |
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i2c->state++; |
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} else if (data_goes_up && clock == 1) |
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bitbang_i2c_enter_stop(i2c); |
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break; |
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i2c->buffer = (i2c->buffer << 1) | data; |
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/* will end up in WAITING_FOR_ACK */ |
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i2c->state++; |
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return bitbang_i2c_ret(i2c, 1); |
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case WAITING_FOR_ACK: |
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if (clock_goes_down) {
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if (i2c->current_addr < 0) {
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i2c->current_addr = i2c->buffer; |
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i2c_start_transfer(i2c->bus, (i2c->current_addr & 0xfe) / 2, |
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i2c->buffer & 1); |
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} else |
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i2c_send(i2c->bus, i2c->buffer); |
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if (i2c->current_addr & 1) {
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i2c->state = RECEIVING_BIT7; |
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i2c->buffer = i2c_recv(i2c->bus); |
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} else |
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i2c->state = SENDING_BIT7; |
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} else if (data_goes_up && clock == 1) |
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bitbang_i2c_enter_stop(i2c); |
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break; |
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case RECEIVING_BIT7 ... RECEIVING_BIT0: |
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qemu_set_irq(i2c->out, i2c->buffer >> 7); |
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if (clock_goes_down) {
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/* will end up in SENDING_ACK */ |
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i2c->state++; |
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i2c->buffer <<= 1; |
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} else if (data_goes_up && clock == 1) |
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bitbang_i2c_enter_stop(i2c); |
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break; |
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if (i2c->current_addr < 0) {
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i2c->current_addr = i2c->buffer; |
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DPRINTF("Address 0x%02x\n", i2c->current_addr);
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i2c_start_transfer(i2c->bus, i2c->current_addr >> 1, |
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i2c->current_addr & 1); |
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} else {
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DPRINTF("Sent 0x%02x\n", i2c->buffer);
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i2c_send(i2c->bus, i2c->buffer); |
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} |
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if (i2c->current_addr & 1) {
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i2c->state = RECEIVING_BIT7; |
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} else {
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i2c->state = SENDING_BIT7; |
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} |
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return bitbang_i2c_ret(i2c, 0); |
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case RECEIVING_BIT7: |
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i2c->buffer = i2c_recv(i2c->bus); |
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DPRINTF("RX byte 0x%02x\n", i2c->buffer);
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/* Fall through... */ |
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case RECEIVING_BIT6 ... RECEIVING_BIT0: |
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data = i2c->buffer >> 7; |
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/* will end up in SENDING_ACK */ |
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i2c->state++; |
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i2c->buffer <<= 1; |
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return bitbang_i2c_ret(i2c, data); |
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| 139 | 153 |
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case SENDING_ACK: |
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if (clock_goes_down) {
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i2c->state = RECEIVING_BIT7; |
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if (data == 0) |
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i2c->buffer = i2c_recv(i2c->bus); |
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else |
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i2c_nack(i2c->bus); |
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} else if (data_goes_up && clock == 1) |
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bitbang_i2c_enter_stop(i2c); |
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break; |
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i2c->state = RECEIVING_BIT7; |
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if (data != 0) {
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DPRINTF("NACKED\n");
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i2c_nack(i2c->bus); |
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} else {
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DPRINTF("ACKED\n");
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} |
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return bitbang_i2c_ret(i2c, 1); |
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} |
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abort(); |
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} |
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|
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bitbang_i2c_interface *bitbang_i2c_init(i2c_bus *bus) |
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{
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bitbang_i2c_interface *s; |
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s = qemu_mallocz(sizeof(bitbang_i2c_interface)); |
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s->bus = bus; |
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s->last_data = 1; |
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s->last_clock = 1; |
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s->device_out = 1; |
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return s; |
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} |
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i2c->last_data = data; |
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i2c->last_clock = clock; |
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/* GPIO interface. */ |
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typedef struct {
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SysBusDevice busdev; |
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bitbang_i2c_interface *bitbang; |
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int last_level; |
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qemu_irq out; |
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} GPIOI2CState; |
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|
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static void bitbang_i2c_gpio_set(void *opaque, int irq, int level) |
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{
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GPIOI2CState *s = opaque; |
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level = bitbang_i2c_set(s->bitbang, irq, level); |
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if (level != s->last_level) {
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s->last_level = level; |
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qemu_set_irq(s->out, level); |
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} |
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| 154 | 198 |
} |
| 155 | 199 |
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static int bitbang_i2c_init(SysBusDevice *dev)
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static int gpio_i2c_init(SysBusDevice *dev)
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{
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bitbang_i2c_interface *s = FROM_SYSBUS(bitbang_i2c_interface, dev);
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GPIOI2CState *s = FROM_SYSBUS(GPIOI2CState, dev);
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| 159 | 203 |
i2c_bus *bus; |
| 160 | 204 |
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sysbus_init_mmio(dev, 0x0, 0); |
| 162 | 206 |
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bus = i2c_init_bus(&dev->qdev, "i2c"); |
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s->bus = bus; |
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s->last_data = 1; |
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s->last_clock = 1; |
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s->bitbang = bitbang_i2c_init(bus); |
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| 168 | 209 |
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qdev_init_gpio_in(&dev->qdev, bitbang_i2c_gpio_set, 2); |
| 170 | 211 |
qdev_init_gpio_out(&dev->qdev, &s->out, 1); |
| ... | ... | |
| 172 | 213 |
return 0; |
| 173 | 214 |
} |
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static SysBusDeviceInfo gpio_i2c_info = {
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.init = gpio_i2c_init, |
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.qdev.name = "gpio_i2c", |
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.qdev.desc = "Virtual GPIO to I2C bridge", |
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.qdev.size = sizeof(GPIOI2CState), |
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}; |
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|
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| 175 | 223 |
static void bitbang_i2c_register(void) |
| 176 | 224 |
{
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sysbus_register_dev("bitbang_i2c",
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sizeof(bitbang_i2c_interface), bitbang_i2c_init); |
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sysbus_register_withprop(&gpio_i2c_info); |
|
| 179 | 226 |
} |
| 180 | 227 |
|
| 181 | 228 |
device_init(bitbang_i2c_register) |
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