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/*
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 * QEMU i8255x (PRO100) emulation
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 *
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 * Copyright (C) 2006-2010 Stefan Weil
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 *
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 * Portions of the code are copies from grub / etherboot eepro100.c
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 * and linux e100.c.
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 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, either version 2 of the License, or
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 * (at your option) version 3 or any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 *
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 * Tested features (i82559):
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 *      PXE boot (i386) ok
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 *      Linux networking (i386) ok
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 *
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 * Untested:
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 *      non-i386 platforms
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 *      Windows networking
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 *
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 * References:
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 *
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 * Intel 8255x 10/100 Mbps Ethernet Controller Family
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 * Open Source Software Developer Manual
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 *
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 * TODO:
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 *      * PHY emulation should be separated from nic emulation.
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 *        Most nic emulations could share the same phy code.
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 *      * i82550 is untested. It is programmed like the i82559.
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 *      * i82562 is untested. It is programmed like the i82559.
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 *      * Power management (i82558 and later) is not implemented.
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 *      * Wake-on-LAN is not implemented.
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 */
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#include <stddef.h>             /* offsetof */
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#include <stdbool.h>
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#include "hw.h"
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#include "pci.h"
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#include "net.h"
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#include "eeprom93xx.h"
50

    
51
/* Common declarations for all PCI devices. */
52

    
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#define PCI_CONFIG_8(offset, value) \
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    (pci_conf[offset] = (value))
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#define PCI_CONFIG_16(offset, value) \
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    (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
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#define PCI_CONFIG_32(offset, value) \
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    (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
59

    
60
#define KiB 1024
61

    
62
/* Debug EEPRO100 card. */
63
#if 0
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# define DEBUG_EEPRO100
65
#endif
66

    
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#ifdef DEBUG_EEPRO100
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#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
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#else
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#define logout(fmt, ...) ((void)0)
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#endif
72

    
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/* Set flags to 0 to disable debug output. */
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#define INT     1       /* interrupt related actions */
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#define MDI     1       /* mdi related actions */
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#define OTHER   1
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#define RXTX    1
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#define EEPROM  1       /* eeprom related actions */
79

    
80
#define TRACE(flag, command) ((flag) ? (command) : (void)0)
81

    
82
#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
83

    
84
#define MAX_ETH_FRAME_SIZE 1514
85

    
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/* This driver supports several different devices which are declared here. */
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#define i82550          0x82550
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#define i82551          0x82551
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#define i82557A         0x82557a
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#define i82557B         0x82557b
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#define i82557C         0x82557c
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#define i82558A         0x82558a
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#define i82558B         0x82558b
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#define i82559A         0x82559a
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#define i82559B         0x82559b
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#define i82559C         0x82559c
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#define i82559ER        0x82559e
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#define i82562          0x82562
99

    
100
/* Use 64 word EEPROM. TODO: could be a runtime option. */
101
#define EEPROM_SIZE     64
102

    
103
#define PCI_MEM_SIZE            (4 * KiB)
104
#define PCI_IO_SIZE             64
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#define PCI_FLASH_SIZE          (128 * KiB)
106

    
107
#define BIT(n) (1 << (n))
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
109

    
110
/* The SCB accepts the following controls for the Tx and Rx units: */
111
#define  CU_NOP         0x0000  /* No operation. */
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#define  CU_START       0x0010  /* CU start. */
113
#define  CU_RESUME      0x0020  /* CU resume. */
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#define  CU_STATSADDR   0x0040  /* Load dump counters address. */
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#define  CU_SHOWSTATS   0x0050  /* Dump statistical counters. */
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#define  CU_CMD_BASE    0x0060  /* Load CU base address. */
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#define  CU_DUMPSTATS   0x0070  /* Dump and reset statistical counters. */
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#define  CU_SRESUME     0x00a0  /* CU static resume. */
119

    
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#define  RU_NOP         0x0000
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#define  RX_START       0x0001
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#define  RX_RESUME      0x0002
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#define  RU_ABORT       0x0004
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#define  RX_ADDR_LOAD   0x0006
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#define  RX_RESUMENR    0x0007
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#define INT_MASK        0x0100
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#define DRVR_INT        0x0200  /* Driver generated interrupt. */
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129
/* Offsets to the various registers.
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   All accesses need not be longword aligned. */
131
enum speedo_offsets {
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    SCBStatus = 0,              /* Status Word. */
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    SCBAck = 1,
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    SCBCmd = 2,                 /* Rx/Command Unit command and status. */
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    SCBIntmask = 3,
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    SCBPointer = 4,             /* General purpose pointer. */
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    SCBPort = 8,                /* Misc. commands and operands.  */
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    SCBflash = 12,              /* Flash memory control. */
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    SCBeeprom = 14,             /* EEPROM control. */
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    SCBCtrlMDI = 16,            /* MDI interface control. */
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    SCBEarlyRx = 20,            /* Early receive byte count. */
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    SCBFlow = 24,               /* Flow Control. */
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    SCBpmdr = 27,               /* Power Management Driver. */
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    SCBgctrl = 28,              /* General Control. */
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    SCBgstat = 29,              /* General Status. */
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};
147

    
148
/* A speedo3 transmit buffer descriptor with two buffers... */
149
typedef struct {
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    uint16_t status;
151
    uint16_t command;
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    uint32_t link;              /* void * */
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    uint32_t tbd_array_addr;    /* transmit buffer descriptor array address. */
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    uint16_t tcb_bytes;         /* transmit command block byte count (in lower 14 bits */
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    uint8_t tx_threshold;       /* transmit threshold */
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    uint8_t tbd_count;          /* TBD number */
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    //~ /* This constitutes two "TBD" entries: hdr and data */
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    //~ uint32_t tx_buf_addr0;  /* void *, header of frame to be transmitted.  */
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    //~ int32_t  tx_buf_size0;  /* Length of Tx hdr. */
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    //~ uint32_t tx_buf_addr1;  /* void *, data to be transmitted.  */
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    //~ int32_t  tx_buf_size1;  /* Length of Tx data. */
162
} eepro100_tx_t;
163

    
164
/* Receive frame descriptor. */
165
typedef struct {
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    int16_t status;
167
    uint16_t command;
168
    uint32_t link;              /* struct RxFD * */
169
    uint32_t rx_buf_addr;       /* void * */
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    uint16_t count;
171
    uint16_t size;
172
    char packet[MAX_ETH_FRAME_SIZE + 4];
173
} eepro100_rx_t;
174

    
175
typedef enum {
176
    COMMAND_EL = BIT(15),
177
    COMMAND_S = BIT(14),
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    COMMAND_I = BIT(13),
179
    COMMAND_NC = BIT(4),
180
    COMMAND_SF = BIT(3),
181
    COMMAND_CMD = BITS(2, 0),
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} scb_command_bit;
183

    
184
typedef enum {
185
    STATUS_C = BIT(15),
186
    STATUS_OK = BIT(13),
187
} scb_status_bit;
188

    
189
typedef struct {
190
    uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
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             tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
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             tx_multiple_collisions, tx_total_collisions;
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    uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
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             rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
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             rx_short_frame_errors;
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    uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
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    uint16_t xmt_tco_frames, rcv_tco_frames;
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    /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
199
    uint32_t reserved[4];
200
} eepro100_stats_t;
201

    
202
typedef enum {
203
    cu_idle = 0,
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    cu_suspended = 1,
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    cu_active = 2,
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    cu_lpq_active = 2,
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    cu_hqp_active = 3
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} cu_state_t;
209

    
210
typedef enum {
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    ru_idle = 0,
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    ru_suspended = 1,
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    ru_no_resources = 2,
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    ru_ready = 4
215
} ru_state_t;
216

    
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typedef struct {
218
    PCIDevice dev;
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    uint8_t mult[8];            /* multicast mask array */
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    int mmio_index;
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    NICState *nic;
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    NICConf conf;
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    uint8_t scb_stat;           /* SCB stat/ack byte */
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    uint8_t int_stat;           /* PCI interrupt status */
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    /* region must not be saved by nic_save. */
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    uint32_t region[3];         /* PCI region addresses */
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    uint16_t mdimem[32];
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    eeprom_t *eeprom;
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    uint32_t device;            /* device variant */
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    uint32_t pointer;
231
    /* (cu_base + cu_offset) address the next command block in the command block list. */
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    uint32_t cu_base;           /* CU base address */
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    uint32_t cu_offset;         /* CU address offset */
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    /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
235
    uint32_t ru_base;           /* RU base address */
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    uint32_t ru_offset;         /* RU address offset */
237
    uint32_t statsaddr;         /* pointer to eepro100_stats_t */
238

    
239
    /* Temporary status information (no need to save these values),
240
     * used while processing CU commands. */
241
    eepro100_tx_t tx;           /* transmit buffer descriptor */
242
    uint32_t cb_address;        /* = cu_base + cu_offset */
243

    
244
    /* Statistical counters. Also used for wake-up packet (i82559). */
245
    eepro100_stats_t statistics;
246

    
247
#if 0
248
    uint16_t status;
249
#endif
250

    
251
    /* Configuration bytes. */
252
    uint8_t configuration[22];
253

    
254
    /* Data in mem is always in the byte order of the controller (le). */
255
    uint8_t mem[PCI_MEM_SIZE];
256
    /* vmstate for each particular nic */
257
    VMStateDescription *vmstate;
258

    
259
    /* Quasi static device properties (no need to save them). */
260
    uint16_t stats_size;
261
    bool has_extended_tcb_support;
262
} EEPRO100State;
263

    
264
/* Word indices in EEPROM. */
265
typedef enum {
266
    EEPROM_CNFG_MDIX  = 0x03,
267
    EEPROM_ID         = 0x05,
268
    EEPROM_PHY_ID     = 0x06,
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    EEPROM_VENDOR_ID  = 0x0c,
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    EEPROM_CONFIG_ASF = 0x0d,
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    EEPROM_DEVICE_ID  = 0x23,
272
    EEPROM_SMBUS_ADDR = 0x90,
273
} EEPROMOffset;
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275
/* Bit values for EEPROM ID word. */
276
typedef enum {
277
    EEPROM_ID_MDM = BIT(0),     /* Modem */
278
    EEPROM_ID_STB = BIT(1),     /* Standby Enable */
279
    EEPROM_ID_WMR = BIT(2),     /* ??? */
280
    EEPROM_ID_WOL = BIT(5),     /* Wake on LAN */
281
    EEPROM_ID_DPD = BIT(6),     /* Deep Power Down */
282
    EEPROM_ID_ALT = BIT(7),     /* */
283
    /* BITS(10, 8) device revision */
284
    EEPROM_ID_BD = BIT(11),     /* boot disable */
285
    EEPROM_ID_ID = BIT(13),     /* id bit */
286
    /* BITS(15, 14) signature */
287
    EEPROM_ID_VALID = BIT(14),  /* signature for valid eeprom */
288
} eeprom_id_bit;
289

    
290
/* Default values for MDI (PHY) registers */
291
static const uint16_t eepro100_mdi_default[] = {
292
    /* MDI Registers 0 - 6, 7 */
293
    0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
294
    /* MDI Registers 8 - 15 */
295
    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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    /* MDI Registers 16 - 31 */
297
    0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
299
};
300

    
301
/* Readonly mask for MDI (PHY) registers */
302
static const uint16_t eepro100_mdi_mask[] = {
303
    0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
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    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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    0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
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    0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
307
};
308

    
309
/* XXX: optimize */
310
static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
311
{
312
    val = cpu_to_le32(val);
313
    cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
314
}
315

    
316
#define POLYNOMIAL 0x04c11db6
317

    
318
/* From FreeBSD */
319
/* XXX: optimize */
320
static unsigned compute_mcast_idx(const uint8_t * ep)
321
{
322
    uint32_t crc;
323
    int carry, i, j;
324
    uint8_t b;
325

    
326
    crc = 0xffffffff;
327
    for (i = 0; i < 6; i++) {
328
        b = *ep++;
329
        for (j = 0; j < 8; j++) {
330
            carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
331
            crc <<= 1;
332
            b >>= 1;
333
            if (carry) {
334
                crc = ((crc ^ POLYNOMIAL) | carry);
335
            }
336
        }
337
    }
338
    return (crc & BITS(7, 2)) >> 2;
339
}
340

    
341
#if defined(DEBUG_EEPRO100)
342
static const char *nic_dump(const uint8_t * buf, unsigned size)
343
{
344
    static char dump[3 * 16 + 1];
345
    char *p = &dump[0];
346
    if (size > 16) {
347
        size = 16;
348
    }
349
    while (size-- > 0) {
350
        p += sprintf(p, " %02x", *buf++);
351
    }
352
    return dump;
353
}
354
#endif                          /* DEBUG_EEPRO100 */
355

    
356
enum scb_stat_ack {
357
    stat_ack_not_ours = 0x00,
358
    stat_ack_sw_gen = 0x04,
359
    stat_ack_rnr = 0x10,
360
    stat_ack_cu_idle = 0x20,
361
    stat_ack_frame_rx = 0x40,
362
    stat_ack_cu_cmd_done = 0x80,
363
    stat_ack_not_present = 0xFF,
364
    stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
365
    stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
366
};
367

    
368
static void disable_interrupt(EEPRO100State * s)
369
{
370
    if (s->int_stat) {
371
        TRACE(INT, logout("interrupt disabled\n"));
372
        qemu_irq_lower(s->dev.irq[0]);
373
        s->int_stat = 0;
374
    }
375
}
376

    
377
static void enable_interrupt(EEPRO100State * s)
378
{
379
    if (!s->int_stat) {
380
        TRACE(INT, logout("interrupt enabled\n"));
381
        qemu_irq_raise(s->dev.irq[0]);
382
        s->int_stat = 1;
383
    }
384
}
385

    
386
static void eepro100_acknowledge(EEPRO100State * s)
387
{
388
    s->scb_stat &= ~s->mem[SCBAck];
389
    s->mem[SCBAck] = s->scb_stat;
390
    if (s->scb_stat == 0) {
391
        disable_interrupt(s);
392
    }
393
}
394

    
395
static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
396
{
397
    uint8_t mask = ~s->mem[SCBIntmask];
398
    s->mem[SCBAck] |= status;
399
    status = s->scb_stat = s->mem[SCBAck];
400
    status &= (mask | 0x0f);
401
    //~ status &= (~s->mem[SCBIntmask] | 0x0xf);
402
    if (status && (mask & 0x01)) {
403
        /* SCB mask and SCB Bit M do not disable interrupt. */
404
        enable_interrupt(s);
405
    } else if (s->int_stat) {
406
        disable_interrupt(s);
407
    }
408
}
409

    
410
static void eepro100_cx_interrupt(EEPRO100State * s)
411
{
412
    /* CU completed action command. */
413
    /* Transmit not ok (82557 only, not in emulation). */
414
    eepro100_interrupt(s, 0x80);
415
}
416

    
417
static void eepro100_cna_interrupt(EEPRO100State * s)
418
{
419
    /* CU left the active state. */
420
    eepro100_interrupt(s, 0x20);
421
}
422

    
423
static void eepro100_fr_interrupt(EEPRO100State * s)
424
{
425
    /* RU received a complete frame. */
426
    eepro100_interrupt(s, 0x40);
427
}
428

    
429
static void eepro100_rnr_interrupt(EEPRO100State * s)
430
{
431
    /* RU is not ready. */
432
    eepro100_interrupt(s, 0x10);
433
}
434

    
435
static void eepro100_mdi_interrupt(EEPRO100State * s)
436
{
437
    /* MDI completed read or write cycle. */
438
    eepro100_interrupt(s, 0x08);
439
}
440

    
441
static void eepro100_swi_interrupt(EEPRO100State * s)
442
{
443
    /* Software has requested an interrupt. */
444
    eepro100_interrupt(s, 0x04);
445
}
446

    
447
#if 0
448
static void eepro100_fcp_interrupt(EEPRO100State * s)
449
{
450
    /* Flow control pause interrupt (82558 and later). */
451
    eepro100_interrupt(s, 0x01);
452
}
453
#endif
454

    
455
static void pci_reset(EEPRO100State * s)
456
{
457
    uint32_t device = s->device;
458
    uint8_t *pci_conf = s->dev.config;
459
    bool power_management = 1;
460

    
461
    TRACE(OTHER, logout("%p\n", s));
462

    
463
    /* PCI Vendor ID */
464
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
465
    /* PCI Device ID depends on device and is set below. */
466
    /* PCI Command */
467
    /* TODO: this is the default, do not override. */
468
    PCI_CONFIG_16(PCI_COMMAND, 0x0000);
469
    /* PCI Status */
470
    /* TODO: Value at RST# should be 0. */
471
    PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
472
    /* PCI Revision ID */
473
    PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
474
    /* TODO: this is the default, do not override. */
475
    /* PCI Class Code */
476
    PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
477
    pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
478
    /* PCI Cache Line Size */
479
    /* check cache line size!!! */
480
    //~ PCI_CONFIG_8(0x0c, 0x00);
481
    /* PCI Latency Timer */
482
    PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20);   // latency timer = 32 clocks
483
    /* PCI Header Type */
484
    /* BIST (built-in self test) */
485
    /* Expansion ROM Base Address (depends on boot disable!!!) */
486
    /* TODO: not needed, set when BAR is registered */
487
    PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
488
    /* Capability Pointer */
489
    /* TODO: revisions with power_management 1 use this but
490
     * do not set new capability list bit in status register. */
491
    PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
492
    /* Interrupt Line */
493
    /* Interrupt Pin */
494
    /* TODO: RST# value should be 0 */
495
    PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1);      // interrupt pin 0
496
    /* Minimum Grant */
497
    PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
498
    /* Maximum Latency */
499
    PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
500

    
501
    switch (device) {
502
    case i82550:
503
        // TODO: check device id.
504
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
505
        /* Revision ID: 0x0c, 0x0d, 0x0e. */
506
        PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
507
        // TODO: check size of statistical counters.
508
        s->stats_size = 80;
509
        // TODO: check extended tcb support.
510
        s->has_extended_tcb_support = 1;
511
        break;
512
    case i82551:
513
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
514
        /* Revision ID: 0x0f, 0x10. */
515
        PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
516
        // TODO: check size of statistical counters.
517
        s->stats_size = 80;
518
        s->has_extended_tcb_support = 1;
519
        break;
520
    case i82557A:
521
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
522
        PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
523
        PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
524
        power_management = 0;
525
        break;
526
    case i82557B:
527
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
528
        PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
529
        PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
530
        power_management = 0;
531
        break;
532
    case i82557C:
533
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
534
        PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
535
        PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
536
        power_management = 0;
537
        break;
538
    case i82558A:
539
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
540
        PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
541
                                  PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
542
        PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
543
        s->stats_size = 76;
544
        s->has_extended_tcb_support = 1;
545
        break;
546
    case i82558B:
547
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
548
        PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
549
                                  PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
550
        PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
551
        s->stats_size = 76;
552
        s->has_extended_tcb_support = 1;
553
        break;
554
    case i82559A:
555
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
556
        PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
557
                                  PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
558
        PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
559
        s->stats_size = 80;
560
        s->has_extended_tcb_support = 1;
561
        break;
562
    case i82559B:
563
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
564
        PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
565
                                  PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
566
        PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
567
        s->stats_size = 80;
568
        s->has_extended_tcb_support = 1;
569
        break;
570
    case i82559C:
571
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
572
        PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
573
                                  PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
574
        PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
575
        // TODO: Windows wants revision id 0x0c.
576
        PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
577
#if EEPROM_SIZE > 0
578
        PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
579
        PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
580
#endif
581
        s->stats_size = 80;
582
        s->has_extended_tcb_support = 1;
583
        break;
584
    case i82559ER:
585
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
586
        PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
587
                                  PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
588
        PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
589
        s->stats_size = 80;
590
        s->has_extended_tcb_support = 1;
591
        break;
592
    case i82562:
593
        // TODO: check device id.
594
        pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
595
        /* TODO: wrong revision id. */
596
        PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
597
        s->stats_size = 80;
598
        s->has_extended_tcb_support = 1;
599
        break;
600
    default:
601
        logout("Device %X is undefined!\n", device);
602
    }
603

    
604
    s->configuration[6] |= BIT(5);
605

    
606
    if (s->stats_size == 80) {
607
        /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
608
        if (s->configuration[6] & BIT(2)) {
609
            /* TCO statistical counters. */
610
            assert(s->configuration[6] & BIT(5));
611
        } else {
612
            if (s->configuration[6] & BIT(5)) {
613
                /* No extended statistical counters, i82557 compatible. */
614
                s->stats_size = 64;
615
            } else {
616
                /* i82558 compatible. */
617
                s->stats_size = 76;
618
            }
619
        }
620
    } else {
621
        if (s->configuration[6] & BIT(5)) {
622
            /* No extended statistical counters. */
623
            s->stats_size = 64;
624
        }
625
    }
626
    assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
627

    
628
    if (power_management) {
629
        /* Power Management Capabilities */
630
        PCI_CONFIG_8(0xdc, 0x01);
631
        /* Next Item Pointer */
632
        /* Capability ID */
633
        PCI_CONFIG_16(0xde, 0x7e21);
634
        /* TODO: Power Management Control / Status. */
635
        /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
636
    }
637

    
638
#if EEPROM_SIZE > 0
639
    if (device == i82557C || device == i82558B || device == i82559C) {
640
        // TODO: get vendor id from EEPROM for i82557C or later.
641
        // TODO: get device id from EEPROM for i82557C or later.
642
        // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
643
        // TODO: header type is determined by EEPROM for i82559.
644
        // TODO: get subsystem id from EEPROM for i82557C or later.
645
        // TODO: get subsystem vendor id from EEPROM for i82557C or later.
646
        // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
647
        // TODO: capability pointer depends on EEPROM for i82558.
648
        logout("Get device id and revision from EEPROM!!!\n");
649
    }
650
#endif /* EEPROM_SIZE > 0 */
651
}
652

    
653
static void nic_selective_reset(EEPRO100State * s)
654
{
655
    size_t i;
656
    uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
657
    //~ eeprom93xx_reset(s->eeprom);
658
    memcpy(eeprom_contents, s->conf.macaddr.a, 6);
659
    eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
660
    if (s->device == i82557B || s->device == i82557C)
661
        eeprom_contents[5] = 0x0100;
662
    eeprom_contents[EEPROM_PHY_ID] = 1;
663
    uint16_t sum = 0;
664
    for (i = 0; i < EEPROM_SIZE - 1; i++) {
665
        sum += eeprom_contents[i];
666
    }
667
    eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
668
    TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
669

    
670
    memset(s->mem, 0, sizeof(s->mem));
671
    uint32_t val = BIT(21);
672
    memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
673

    
674
    assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
675
    memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
676
}
677

    
678
static void nic_reset(void *opaque)
679
{
680
    EEPRO100State *s = opaque;
681
    TRACE(OTHER, logout("%p\n", s));
682
    /* TODO: Clearing of multicast table for selective reset, too? */
683
    memset(&s->mult[0], 0, sizeof(s->mult));
684
    nic_selective_reset(s);
685
}
686

    
687
#if defined(DEBUG_EEPRO100)
688
static const char * const e100_reg[PCI_IO_SIZE / 4] = {
689
    "Command/Status",
690
    "General Pointer",
691
    "Port",
692
    "EEPROM/Flash Control",
693
    "MDI Control",
694
    "Receive DMA Byte Count",
695
    "Flow Control",
696
    "General Status/Control"
697
};
698

    
699
static char *regname(uint32_t addr)
700
{
701
    static char buf[32];
702
    if (addr < PCI_IO_SIZE) {
703
        const char *r = e100_reg[addr / 4];
704
        if (r != 0) {
705
            snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
706
        } else {
707
            snprintf(buf, sizeof(buf), "0x%02x", addr);
708
        }
709
    } else {
710
        snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
711
    }
712
    return buf;
713
}
714
#endif                          /* DEBUG_EEPRO100 */
715

    
716
#if 0
717
static uint16_t eepro100_read_status(EEPRO100State * s)
718
{
719
    uint16_t val = s->status;
720
    TRACE(OTHER, logout("val=0x%04x\n", val));
721
    return val;
722
}
723

724
static void eepro100_write_status(EEPRO100State * s, uint16_t val)
725
{
726
    TRACE(OTHER, logout("val=0x%04x\n", val));
727
    s->status = val;
728
}
729
#endif
730

    
731
/*****************************************************************************
732
 *
733
 * Command emulation.
734
 *
735
 ****************************************************************************/
736

    
737
#if 0
738
static uint16_t eepro100_read_command(EEPRO100State * s)
739
{
740
    uint16_t val = 0xffff;
741
    //~ TRACE(OTHER, logout("val=0x%04x\n", val));
742
    return val;
743
}
744
#endif
745

    
746
/* Commands that can be put in a command list entry. */
747
enum commands {
748
    CmdNOp = 0,
749
    CmdIASetup = 1,
750
    CmdConfigure = 2,
751
    CmdMulticastList = 3,
752
    CmdTx = 4,
753
    CmdTDR = 5,                 /* load microcode */
754
    CmdDump = 6,
755
    CmdDiagnose = 7,
756

    
757
    /* And some extra flags: */
758
    CmdSuspend = 0x4000,        /* Suspend after completion. */
759
    CmdIntr = 0x2000,           /* Interrupt after completion. */
760
    CmdTxFlex = 0x0008,         /* Use "Flexible mode" for CmdTx command. */
761
};
762

    
763
static cu_state_t get_cu_state(EEPRO100State * s)
764
{
765
    return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
766
}
767

    
768
static void set_cu_state(EEPRO100State * s, cu_state_t state)
769
{
770
    s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
771
}
772

    
773
static ru_state_t get_ru_state(EEPRO100State * s)
774
{
775
    return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
776
}
777

    
778
static void set_ru_state(EEPRO100State * s, ru_state_t state)
779
{
780
    s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
781
}
782

    
783
static void dump_statistics(EEPRO100State * s)
784
{
785
    /* Dump statistical data. Most data is never changed by the emulation
786
     * and always 0, so we first just copy the whole block and then those
787
     * values which really matter.
788
     * Number of data should check configuration!!!
789
     */
790
    cpu_physical_memory_write(s->statsaddr,
791
                              (uint8_t *) & s->statistics, s->stats_size);
792
    stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
793
    stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
794
    stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
795
    stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
796
    //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
797
    //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
798
    //~ missing("CU dump statistical counters");
799
}
800

    
801
static void read_cb(EEPRO100State *s)
802
{
803
    cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
804
    s->tx.status = le16_to_cpu(s->tx.status);
805
    s->tx.command = le16_to_cpu(s->tx.command);
806
    s->tx.link = le32_to_cpu(s->tx.link);
807
    s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
808
    s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
809
}
810

    
811
static void tx_command(EEPRO100State *s)
812
{
813
    uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
814
    uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
815
    /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
816
    uint8_t buf[2600];
817
    uint16_t size = 0;
818
    uint32_t tbd_address = s->cb_address + 0x10;
819
    TRACE(RXTX, logout
820
        ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
821
         tbd_array, tcb_bytes, s->tx.tbd_count));
822

    
823
    if (tcb_bytes > 2600) {
824
        logout("TCB byte count too large, using 2600\n");
825
        tcb_bytes = 2600;
826
    }
827
    if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
828
        logout
829
            ("illegal values of TBD array address and TCB byte count!\n");
830
    }
831
    assert(tcb_bytes <= sizeof(buf));
832
    while (size < tcb_bytes) {
833
        uint32_t tx_buffer_address = ldl_phys(tbd_address);
834
        uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
835
        //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
836
        tbd_address += 8;
837
        TRACE(RXTX, logout
838
            ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
839
             tx_buffer_address, tx_buffer_size));
840
        tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
841
        cpu_physical_memory_read(tx_buffer_address, &buf[size],
842
                                 tx_buffer_size);
843
        size += tx_buffer_size;
844
    }
845
    if (tbd_array == 0xffffffff) {
846
        /* Simplified mode. Was already handled by code above. */
847
    } else {
848
        /* Flexible mode. */
849
        uint8_t tbd_count = 0;
850
        if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
851
            /* Extended Flexible TCB. */
852
            for (; tbd_count < 2; tbd_count++) {
853
                uint32_t tx_buffer_address = ldl_phys(tbd_address);
854
                uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
855
                uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
856
                tbd_address += 8;
857
                TRACE(RXTX, logout
858
                    ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
859
                     tx_buffer_address, tx_buffer_size));
860
                tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
861
                cpu_physical_memory_read(tx_buffer_address, &buf[size],
862
                                         tx_buffer_size);
863
                size += tx_buffer_size;
864
                if (tx_buffer_el & 1) {
865
                    break;
866
                }
867
            }
868
        }
869
        tbd_address = tbd_array;
870
        for (; tbd_count < s->tx.tbd_count; tbd_count++) {
871
            uint32_t tx_buffer_address = ldl_phys(tbd_address);
872
            uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
873
            uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
874
            tbd_address += 8;
875
            TRACE(RXTX, logout
876
                ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
877
                 tx_buffer_address, tx_buffer_size));
878
            tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
879
            cpu_physical_memory_read(tx_buffer_address, &buf[size],
880
                                     tx_buffer_size);
881
            size += tx_buffer_size;
882
            if (tx_buffer_el & 1) {
883
                break;
884
            }
885
        }
886
    }
887
    TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
888
    qemu_send_packet(&s->nic->nc, buf, size);
889
    s->statistics.tx_good_frames++;
890
    /* Transmit with bad status would raise an CX/TNO interrupt.
891
     * (82557 only). Emulation never has bad status. */
892
    //~ eepro100_cx_interrupt(s);
893
}
894

    
895
static void set_multicast_list(EEPRO100State *s)
896
{
897
    uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
898
    uint16_t i;
899
    memset(&s->mult[0], 0, sizeof(s->mult));
900
    TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
901
    for (i = 0; i < multicast_count; i += 6) {
902
        uint8_t multicast_addr[6];
903
        cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
904
        TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
905
        unsigned mcast_idx = compute_mcast_idx(multicast_addr);
906
        assert(mcast_idx < 64);
907
        s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
908
    }
909
}
910

    
911
static void action_command(EEPRO100State *s)
912
{
913
    for (;;) {
914
        bool bit_el;
915
        bool bit_s;
916
        bool bit_i;
917
        bool bit_nc;
918
        bool success = true;
919
        s->cb_address = s->cu_base + s->cu_offset;
920
        read_cb(s);
921
        bit_el = ((s->tx.command & COMMAND_EL) != 0);
922
        bit_s = ((s->tx.command & COMMAND_S) != 0);
923
        bit_i = ((s->tx.command & COMMAND_I) != 0);
924
        bit_nc = ((s->tx.command & COMMAND_NC) != 0);
925
#if 0
926
        bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
927
#endif
928
        s->cu_offset = s->tx.link;
929
        TRACE(OTHER,
930
              logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
931
                     s->tx.status, s->tx.command, s->tx.link));
932
        switch (s->tx.command & COMMAND_CMD) {
933
        case CmdNOp:
934
            /* Do nothing. */
935
            break;
936
        case CmdIASetup:
937
            cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
938
            TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
939
            break;
940
        case CmdConfigure:
941
            cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
942
                                     sizeof(s->configuration));
943
            TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
944
            break;
945
        case CmdMulticastList:
946
            set_multicast_list(s);
947
            break;
948
        case CmdTx:
949
            if (bit_nc) {
950
                missing("CmdTx: NC = 0");
951
                success = false;
952
                break;
953
            }
954
            tx_command(s);
955
            break;
956
        case CmdTDR:
957
            TRACE(OTHER, logout("load microcode\n"));
958
            /* Starting with offset 8, the command contains
959
             * 64 dwords microcode which we just ignore here. */
960
            break;
961
        default:
962
            missing("undefined command");
963
            success = false;
964
            break;
965
        }
966
        /* Write new status. */
967
        stw_phys(s->cb_address, s->tx.status | STATUS_C | (success ? STATUS_OK : 0));
968
        if (bit_i) {
969
            /* CU completed action. */
970
            eepro100_cx_interrupt(s);
971
        }
972
        if (bit_el) {
973
            /* CU becomes idle. Terminate command loop. */
974
            set_cu_state(s, cu_idle);
975
            eepro100_cna_interrupt(s);
976
            break;
977
        } else if (bit_s) {
978
            /* CU becomes suspended. Terminate command loop. */
979
            set_cu_state(s, cu_suspended);
980
            eepro100_cna_interrupt(s);
981
            break;
982
        } else {
983
            /* More entries in list. */
984
            TRACE(OTHER, logout("CU list with at least one more entry\n"));
985
        }
986
    }
987
    TRACE(OTHER, logout("CU list empty\n"));
988
    /* List is empty. Now CU is idle or suspended. */
989
}
990

    
991
static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
992
{
993
    cu_state_t cu_state;
994
    switch (val) {
995
    case CU_NOP:
996
        /* No operation. */
997
        break;
998
    case CU_START:
999
        cu_state = get_cu_state(s);
1000
        if (cu_state != cu_idle && cu_state != cu_suspended) {
1001
            /* Intel documentation says that CU must be idle or suspended
1002
             * for the CU start command. */
1003
            logout("unexpected CU state is %u\n", cu_state);
1004
        }
1005
        set_cu_state(s, cu_active);
1006
        s->cu_offset = s->pointer;
1007
        action_command(s);
1008
        break;
1009
    case CU_RESUME:
1010
        if (get_cu_state(s) != cu_suspended) {
1011
            logout("bad CU resume from CU state %u\n", get_cu_state(s));
1012
            /* Workaround for bad Linux eepro100 driver which resumes
1013
             * from idle state. */
1014
            //~ missing("cu resume");
1015
            set_cu_state(s, cu_suspended);
1016
        }
1017
        if (get_cu_state(s) == cu_suspended) {
1018
            TRACE(OTHER, logout("CU resuming\n"));
1019
            set_cu_state(s, cu_active);
1020
            action_command(s);
1021
        }
1022
        break;
1023
    case CU_STATSADDR:
1024
        /* Load dump counters address. */
1025
        s->statsaddr = s->pointer;
1026
        TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1027
        break;
1028
    case CU_SHOWSTATS:
1029
        /* Dump statistical counters. */
1030
        TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1031
        dump_statistics(s);
1032
        stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1033
        break;
1034
    case CU_CMD_BASE:
1035
        /* Load CU base. */
1036
        TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1037
        s->cu_base = s->pointer;
1038
        break;
1039
    case CU_DUMPSTATS:
1040
        /* Dump and reset statistical counters. */
1041
        TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1042
        dump_statistics(s);
1043
        stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1044
        memset(&s->statistics, 0, sizeof(s->statistics));
1045
        break;
1046
    case CU_SRESUME:
1047
        /* CU static resume. */
1048
        missing("CU static resume");
1049
        break;
1050
    default:
1051
        missing("Undefined CU command");
1052
    }
1053
}
1054

    
1055
static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1056
{
1057
    switch (val) {
1058
    case RU_NOP:
1059
        /* No operation. */
1060
        break;
1061
    case RX_START:
1062
        /* RU start. */
1063
        if (get_ru_state(s) != ru_idle) {
1064
            logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1065
            //~ assert(!"wrong RU state");
1066
        }
1067
        set_ru_state(s, ru_ready);
1068
        s->ru_offset = s->pointer;
1069
        TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1070
        break;
1071
    case RX_RESUME:
1072
        /* Restart RU. */
1073
        if (get_ru_state(s) != ru_suspended) {
1074
            logout("RU state is %u, should be %u\n", get_ru_state(s),
1075
                   ru_suspended);
1076
            //~ assert(!"wrong RU state");
1077
        }
1078
        set_ru_state(s, ru_ready);
1079
        break;
1080
    case RU_ABORT:
1081
        /* RU abort. */
1082
        if (get_ru_state(s) == ru_ready) {
1083
            eepro100_rnr_interrupt(s);
1084
        }
1085
        set_ru_state(s, ru_idle);
1086
        break;
1087
    case RX_ADDR_LOAD:
1088
        /* Load RU base. */
1089
        TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1090
        s->ru_base = s->pointer;
1091
        break;
1092
    default:
1093
        logout("val=0x%02x (undefined RU command)\n", val);
1094
        missing("Undefined SU command");
1095
    }
1096
}
1097

    
1098
static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1099
{
1100
    eepro100_ru_command(s, val & 0x0f);
1101
    eepro100_cu_command(s, val & 0xf0);
1102
    if ((val) == 0) {
1103
        TRACE(OTHER, logout("val=0x%02x\n", val));
1104
    }
1105
    /* Clear command byte after command was accepted. */
1106
    s->mem[SCBCmd] = 0;
1107
}
1108

    
1109
/*****************************************************************************
1110
 *
1111
 * EEPROM emulation.
1112
 *
1113
 ****************************************************************************/
1114

    
1115
#define EEPROM_CS       0x02
1116
#define EEPROM_SK       0x01
1117
#define EEPROM_DI       0x04
1118
#define EEPROM_DO       0x08
1119

    
1120
static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1121
{
1122
    uint16_t val;
1123
    memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1124
    if (eeprom93xx_read(s->eeprom)) {
1125
        val |= EEPROM_DO;
1126
    } else {
1127
        val &= ~EEPROM_DO;
1128
    }
1129
    TRACE(EEPROM, logout("val=0x%04x\n", val));
1130
    return val;
1131
}
1132

    
1133
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1134
{
1135
    TRACE(EEPROM, logout("val=0x%02x\n", val));
1136

    
1137
    /* mask unwriteable bits */
1138
    //~ val = SET_MASKED(val, 0x31, eeprom->value);
1139

    
1140
    int eecs = ((val & EEPROM_CS) != 0);
1141
    int eesk = ((val & EEPROM_SK) != 0);
1142
    int eedi = ((val & EEPROM_DI) != 0);
1143
    eeprom93xx_write(eeprom, eecs, eesk, eedi);
1144
}
1145

    
1146
static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1147
{
1148
    s->pointer = le32_to_cpu(val);
1149
    TRACE(OTHER, logout("val=0x%08x\n", val));
1150
}
1151

    
1152
/*****************************************************************************
1153
 *
1154
 * MDI emulation.
1155
 *
1156
 ****************************************************************************/
1157

    
1158
#if defined(DEBUG_EEPRO100)
1159
static const char * const mdi_op_name[] = {
1160
    "opcode 0",
1161
    "write",
1162
    "read",
1163
    "opcode 3"
1164
};
1165

    
1166
static const char * const mdi_reg_name[] = {
1167
    "Control",
1168
    "Status",
1169
    "PHY Identification (Word 1)",
1170
    "PHY Identification (Word 2)",
1171
    "Auto-Negotiation Advertisement",
1172
    "Auto-Negotiation Link Partner Ability",
1173
    "Auto-Negotiation Expansion"
1174
};
1175

    
1176
static const char *reg2name(uint8_t reg)
1177
{
1178
    static char buffer[10];
1179
    const char *p = buffer;
1180
    if (reg < ARRAY_SIZE(mdi_reg_name)) {
1181
        p = mdi_reg_name[reg];
1182
    } else {
1183
        snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1184
    }
1185
    return p;
1186
}
1187
#endif                          /* DEBUG_EEPRO100 */
1188

    
1189
static uint32_t eepro100_read_mdi(EEPRO100State * s)
1190
{
1191
    uint32_t val;
1192
    memcpy(&val, &s->mem[0x10], sizeof(val));
1193

    
1194
#ifdef DEBUG_EEPRO100
1195
    uint8_t raiseint = (val & BIT(29)) >> 29;
1196
    uint8_t opcode = (val & BITS(27, 26)) >> 26;
1197
    uint8_t phy = (val & BITS(25, 21)) >> 21;
1198
    uint8_t reg = (val & BITS(20, 16)) >> 16;
1199
    uint16_t data = (val & BITS(15, 0));
1200
#endif
1201
    /* Emulation takes no time to finish MDI transaction. */
1202
    val |= BIT(28);
1203
    TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1204
                      val, raiseint, mdi_op_name[opcode], phy,
1205
                      reg2name(reg), data));
1206
    return val;
1207
}
1208

    
1209
static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1210
{
1211
    uint8_t raiseint = (val & BIT(29)) >> 29;
1212
    uint8_t opcode = (val & BITS(27, 26)) >> 26;
1213
    uint8_t phy = (val & BITS(25, 21)) >> 21;
1214
    uint8_t reg = (val & BITS(20, 16)) >> 16;
1215
    uint16_t data = (val & BITS(15, 0));
1216
    TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1217
          val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1218
    if (phy != 1) {
1219
        /* Unsupported PHY address. */
1220
        //~ logout("phy must be 1 but is %u\n", phy);
1221
        data = 0;
1222
    } else if (opcode != 1 && opcode != 2) {
1223
        /* Unsupported opcode. */
1224
        logout("opcode must be 1 or 2 but is %u\n", opcode);
1225
        data = 0;
1226
    } else if (reg > 6) {
1227
        /* Unsupported register. */
1228
        logout("register must be 0...6 but is %u\n", reg);
1229
        data = 0;
1230
    } else {
1231
        TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1232
                          val, raiseint, mdi_op_name[opcode], phy,
1233
                          reg2name(reg), data));
1234
        if (opcode == 1) {
1235
            /* MDI write */
1236
            switch (reg) {
1237
            case 0:            /* Control Register */
1238
                if (data & 0x8000) {
1239
                    /* Reset status and control registers to default. */
1240
                    s->mdimem[0] = eepro100_mdi_default[0];
1241
                    s->mdimem[1] = eepro100_mdi_default[1];
1242
                    data = s->mdimem[reg];
1243
                } else {
1244
                    /* Restart Auto Configuration = Normal Operation */
1245
                    data &= ~0x0200;
1246
                }
1247
                break;
1248
            case 1:            /* Status Register */
1249
                missing("not writable");
1250
                data = s->mdimem[reg];
1251
                break;
1252
            case 2:            /* PHY Identification Register (Word 1) */
1253
            case 3:            /* PHY Identification Register (Word 2) */
1254
                missing("not implemented");
1255
                break;
1256
            case 4:            /* Auto-Negotiation Advertisement Register */
1257
            case 5:            /* Auto-Negotiation Link Partner Ability Register */
1258
                break;
1259
            case 6:            /* Auto-Negotiation Expansion Register */
1260
            default:
1261
                missing("not implemented");
1262
            }
1263
            s->mdimem[reg] = data;
1264
        } else if (opcode == 2) {
1265
            /* MDI read */
1266
            switch (reg) {
1267
            case 0:            /* Control Register */
1268
                if (data & 0x8000) {
1269
                    /* Reset status and control registers to default. */
1270
                    s->mdimem[0] = eepro100_mdi_default[0];
1271
                    s->mdimem[1] = eepro100_mdi_default[1];
1272
                }
1273
                break;
1274
            case 1:            /* Status Register */
1275
                s->mdimem[reg] |= 0x0020;
1276
                break;
1277
            case 2:            /* PHY Identification Register (Word 1) */
1278
            case 3:            /* PHY Identification Register (Word 2) */
1279
            case 4:            /* Auto-Negotiation Advertisement Register */
1280
                break;
1281
            case 5:            /* Auto-Negotiation Link Partner Ability Register */
1282
                s->mdimem[reg] = 0x41fe;
1283
                break;
1284
            case 6:            /* Auto-Negotiation Expansion Register */
1285
                s->mdimem[reg] = 0x0001;
1286
                break;
1287
            }
1288
            data = s->mdimem[reg];
1289
        }
1290
        /* Emulation takes no time to finish MDI transaction.
1291
         * Set MDI bit in SCB status register. */
1292
        s->mem[SCBAck] |= 0x08;
1293
        val |= BIT(28);
1294
        if (raiseint) {
1295
            eepro100_mdi_interrupt(s);
1296
        }
1297
    }
1298
    val = (val & 0xffff0000) + data;
1299
    memcpy(&s->mem[0x10], &val, sizeof(val));
1300
}
1301

    
1302
/*****************************************************************************
1303
 *
1304
 * Port emulation.
1305
 *
1306
 ****************************************************************************/
1307

    
1308
#define PORT_SOFTWARE_RESET     0
1309
#define PORT_SELFTEST           1
1310
#define PORT_SELECTIVE_RESET    2
1311
#define PORT_DUMP               3
1312
#define PORT_SELECTION_MASK     3
1313

    
1314
typedef struct {
1315
    uint32_t st_sign;           /* Self Test Signature */
1316
    uint32_t st_result;         /* Self Test Results */
1317
} eepro100_selftest_t;
1318

    
1319
static uint32_t eepro100_read_port(EEPRO100State * s)
1320
{
1321
    return 0;
1322
}
1323

    
1324
static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1325
{
1326
    val = le32_to_cpu(val);
1327
    uint32_t address = (val & ~PORT_SELECTION_MASK);
1328
    uint8_t selection = (val & PORT_SELECTION_MASK);
1329
    switch (selection) {
1330
    case PORT_SOFTWARE_RESET:
1331
        nic_reset(s);
1332
        break;
1333
    case PORT_SELFTEST:
1334
        TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1335
        eepro100_selftest_t data;
1336
        cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1337
        data.st_sign = 0xffffffff;
1338
        data.st_result = 0;
1339
        cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1340
        break;
1341
    case PORT_SELECTIVE_RESET:
1342
        TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1343
        nic_selective_reset(s);
1344
        break;
1345
    default:
1346
        logout("val=0x%08x\n", val);
1347
        missing("unknown port selection");
1348
    }
1349
}
1350

    
1351
/*****************************************************************************
1352
 *
1353
 * General hardware emulation.
1354
 *
1355
 ****************************************************************************/
1356

    
1357
static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1358
{
1359
    uint8_t val;
1360
    if (addr <= sizeof(s->mem) - sizeof(val)) {
1361
        memcpy(&val, &s->mem[addr], sizeof(val));
1362
    }
1363

    
1364
    switch (addr) {
1365
    case SCBStatus:
1366
        //~ val = eepro100_read_status(s);
1367
        TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1368
        break;
1369
    case SCBAck:
1370
        //~ val = eepro100_read_status(s);
1371
        TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1372
        break;
1373
    case SCBCmd:
1374
        TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1375
        //~ val = eepro100_read_command(s);
1376
        break;
1377
    case SCBIntmask:
1378
        TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1379
        break;
1380
    case SCBPort + 3:
1381
        TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1382
        break;
1383
    case SCBeeprom:
1384
        val = eepro100_read_eeprom(s);
1385
        break;
1386
    case SCBpmdr:       /* Power Management Driver Register */
1387
        val = 0;
1388
        TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1389
        break;
1390
    case SCBgstat:      /* General Status Register */
1391
        /* 100 Mbps full duplex, valid link */
1392
        val = 0x07;
1393
        TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1394
        break;
1395
    default:
1396
        logout("addr=%s val=0x%02x\n", regname(addr), val);
1397
        missing("unknown byte read");
1398
    }
1399
    return val;
1400
}
1401

    
1402
static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1403
{
1404
    uint16_t val;
1405
    if (addr <= sizeof(s->mem) - sizeof(val)) {
1406
        memcpy(&val, &s->mem[addr], sizeof(val));
1407
    }
1408

    
1409
    switch (addr) {
1410
    case SCBStatus:
1411
        //~ val = eepro100_read_status(s);
1412
    case SCBCmd:
1413
        TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1414
        break;
1415
    case SCBeeprom:
1416
        val = eepro100_read_eeprom(s);
1417
        TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1418
        break;
1419
    default:
1420
        logout("addr=%s val=0x%04x\n", regname(addr), val);
1421
        missing("unknown word read");
1422
    }
1423
    return val;
1424
}
1425

    
1426
static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1427
{
1428
    uint32_t val;
1429
    if (addr <= sizeof(s->mem) - sizeof(val)) {
1430
        memcpy(&val, &s->mem[addr], sizeof(val));
1431
    }
1432

    
1433
    switch (addr) {
1434
    case SCBStatus:
1435
        //~ val = eepro100_read_status(s);
1436
        TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1437
        break;
1438
    case SCBPointer:
1439
        //~ val = eepro100_read_pointer(s);
1440
        TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1441
        break;
1442
    case SCBPort:
1443
        val = eepro100_read_port(s);
1444
        TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1445
        break;
1446
    case SCBCtrlMDI:
1447
        val = eepro100_read_mdi(s);
1448
        break;
1449
    default:
1450
        logout("addr=%s val=0x%08x\n", regname(addr), val);
1451
        missing("unknown longword read");
1452
    }
1453
    return val;
1454
}
1455

    
1456
static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1457
{
1458
    if (addr <= sizeof(s->mem) - sizeof(val)) {
1459
        memcpy(&s->mem[addr], &val, sizeof(val));
1460
    }
1461

    
1462
    TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1463

    
1464
    switch (addr) {
1465
    case SCBStatus:
1466
        //~ eepro100_write_status(s, val);
1467
        break;
1468
    case SCBAck:
1469
        eepro100_acknowledge(s);
1470
        break;
1471
    case SCBCmd:
1472
        eepro100_write_command(s, val);
1473
        break;
1474
    case SCBIntmask:
1475
        if (val & BIT(1)) {
1476
            eepro100_swi_interrupt(s);
1477
        }
1478
        eepro100_interrupt(s, 0);
1479
        break;
1480
    case SCBPort + 3:
1481
    case SCBFlow:       /* does not exist on 82557 */
1482
    case SCBFlow + 1:
1483
    case SCBFlow + 2:
1484
    case SCBpmdr:       /* does not exist on 82557 */
1485
        TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1486
        break;
1487
    case SCBeeprom:
1488
        eepro100_write_eeprom(s->eeprom, val);
1489
        break;
1490
    default:
1491
        logout("addr=%s val=0x%02x\n", regname(addr), val);
1492
        missing("unknown byte write");
1493
    }
1494
}
1495

    
1496
static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1497
{
1498
    if (addr <= sizeof(s->mem) - sizeof(val)) {
1499
        memcpy(&s->mem[addr], &val, sizeof(val));
1500
    }
1501

    
1502
    TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1503

    
1504
    switch (addr) {
1505
    case SCBStatus:
1506
        //~ eepro100_write_status(s, val);
1507
        eepro100_acknowledge(s);
1508
        break;
1509
    case SCBCmd:
1510
        eepro100_write_command(s, val);
1511
        eepro100_write1(s, SCBIntmask, val >> 8);
1512
        break;
1513
    case SCBeeprom:
1514
        eepro100_write_eeprom(s->eeprom, val);
1515
        break;
1516
    default:
1517
        logout("addr=%s val=0x%04x\n", regname(addr), val);
1518
        missing("unknown word write");
1519
    }
1520
}
1521

    
1522
static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1523
{
1524
    if (addr <= sizeof(s->mem) - sizeof(val)) {
1525
        memcpy(&s->mem[addr], &val, sizeof(val));
1526
    }
1527

    
1528
    switch (addr) {
1529
    case SCBPointer:
1530
        eepro100_write_pointer(s, val);
1531
        break;
1532
    case SCBPort:
1533
        TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1534
        eepro100_write_port(s, val);
1535
        break;
1536
    case SCBCtrlMDI:
1537
        eepro100_write_mdi(s, val);
1538
        break;
1539
    default:
1540
        logout("addr=%s val=0x%08x\n", regname(addr), val);
1541
        missing("unknown longword write");
1542
    }
1543
}
1544

    
1545
/*****************************************************************************
1546
 *
1547
 * Port mapped I/O.
1548
 *
1549
 ****************************************************************************/
1550

    
1551
static uint32_t ioport_read1(void *opaque, uint32_t addr)
1552
{
1553
    EEPRO100State *s = opaque;
1554
    //~ logout("addr=%s\n", regname(addr));
1555
    return eepro100_read1(s, addr - s->region[1]);
1556
}
1557

    
1558
static uint32_t ioport_read2(void *opaque, uint32_t addr)
1559
{
1560
    EEPRO100State *s = opaque;
1561
    return eepro100_read2(s, addr - s->region[1]);
1562
}
1563

    
1564
static uint32_t ioport_read4(void *opaque, uint32_t addr)
1565
{
1566
    EEPRO100State *s = opaque;
1567
    return eepro100_read4(s, addr - s->region[1]);
1568
}
1569

    
1570
static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1571
{
1572
    EEPRO100State *s = opaque;
1573
    //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1574
    eepro100_write1(s, addr - s->region[1], val);
1575
}
1576

    
1577
static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1578
{
1579
    EEPRO100State *s = opaque;
1580
    eepro100_write2(s, addr - s->region[1], val);
1581
}
1582

    
1583
static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1584
{
1585
    EEPRO100State *s = opaque;
1586
    eepro100_write4(s, addr - s->region[1], val);
1587
}
1588

    
1589
/***********************************************************/
1590
/* PCI EEPRO100 definitions */
1591

    
1592
static void pci_map(PCIDevice * pci_dev, int region_num,
1593
                    pcibus_t addr, pcibus_t size, int type)
1594
{
1595
    EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1596

    
1597
    TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1598
          "size=0x%08"FMT_PCIBUS", type=%d\n",
1599
          region_num, addr, size, type));
1600

    
1601
    assert(region_num == 1);
1602
    register_ioport_write(addr, size, 1, ioport_write1, s);
1603
    register_ioport_read(addr, size, 1, ioport_read1, s);
1604
    register_ioport_write(addr, size, 2, ioport_write2, s);
1605
    register_ioport_read(addr, size, 2, ioport_read2, s);
1606
    register_ioport_write(addr, size, 4, ioport_write4, s);
1607
    register_ioport_read(addr, size, 4, ioport_read4, s);
1608

    
1609
    s->region[region_num] = addr;
1610
}
1611

    
1612
/*****************************************************************************
1613
 *
1614
 * Memory mapped I/O.
1615
 *
1616
 ****************************************************************************/
1617

    
1618
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1619
{
1620
    EEPRO100State *s = opaque;
1621
    //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1622
    eepro100_write1(s, addr, val);
1623
}
1624

    
1625
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1626
{
1627
    EEPRO100State *s = opaque;
1628
    //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1629
    eepro100_write2(s, addr, val);
1630
}
1631

    
1632
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1633
{
1634
    EEPRO100State *s = opaque;
1635
    //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1636
    eepro100_write4(s, addr, val);
1637
}
1638

    
1639
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1640
{
1641
    EEPRO100State *s = opaque;
1642
    //~ logout("addr=%s\n", regname(addr));
1643
    return eepro100_read1(s, addr);
1644
}
1645

    
1646
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1647
{
1648
    EEPRO100State *s = opaque;
1649
    //~ logout("addr=%s\n", regname(addr));
1650
    return eepro100_read2(s, addr);
1651
}
1652

    
1653
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1654
{
1655
    EEPRO100State *s = opaque;
1656
    //~ logout("addr=%s\n", regname(addr));
1657
    return eepro100_read4(s, addr);
1658
}
1659

    
1660
static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1661
    pci_mmio_writeb,
1662
    pci_mmio_writew,
1663
    pci_mmio_writel
1664
};
1665

    
1666
static CPUReadMemoryFunc * const pci_mmio_read[] = {
1667
    pci_mmio_readb,
1668
    pci_mmio_readw,
1669
    pci_mmio_readl
1670
};
1671

    
1672
static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1673
                         pcibus_t addr, pcibus_t size, int type)
1674
{
1675
    EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1676

    
1677
    TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1678
          "size=0x%08"FMT_PCIBUS", type=%d\n",
1679
          region_num, addr, size, type));
1680

    
1681
    if (region_num == 0) {
1682
        /* Map control / status registers. */
1683
        cpu_register_physical_memory(addr, size, s->mmio_index);
1684
        s->region[region_num] = addr;
1685
    }
1686
}
1687

    
1688
static int nic_can_receive(VLANClientState *nc)
1689
{
1690
    EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1691
    TRACE(RXTX, logout("%p\n", s));
1692
    return get_ru_state(s) == ru_ready;
1693
    //~ return !eepro100_buffer_full(s);
1694
}
1695

    
1696
static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1697
{
1698
    /* TODO:
1699
     * - Magic packets should set bit 30 in power management driver register.
1700
     * - Interesting packets should set bit 29 in power management driver register.
1701
     */
1702
    EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1703
    uint16_t rfd_status = 0xa000;
1704
    static const uint8_t broadcast_macaddr[6] =
1705
        { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1706

    
1707
    /* TODO: check multiple IA bit. */
1708
    if (s->configuration[20] & BIT(6)) {
1709
        missing("Multiple IA bit");
1710
        return -1;
1711
    }
1712

    
1713
    if (s->configuration[8] & 0x80) {
1714
        /* CSMA is disabled. */
1715
        logout("%p received while CSMA is disabled\n", s);
1716
        return -1;
1717
    } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1718
        /* Short frame and configuration byte 7/0 (discard short receive) set:
1719
         * Short frame is discarded */
1720
        logout("%p received short frame (%zu byte)\n", s, size);
1721
        s->statistics.rx_short_frame_errors++;
1722
        //~ return -1;
1723
    } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1724
        /* Long frame and configuration byte 18/3 (long receive ok) not set:
1725
         * Long frames are discarded. */
1726
        logout("%p received long frame (%zu byte), ignored\n", s, size);
1727
        return -1;
1728
    } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) {       // !!!
1729
        /* Frame matches individual address. */
1730
        /* TODO: check configuration byte 15/4 (ignore U/L). */
1731
        TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1732
    } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1733
        /* Broadcast frame. */
1734
        TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1735
        rfd_status |= 0x0002;
1736
    } else if (buf[0] & 0x01) {
1737
        /* Multicast frame. */
1738
        TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1739
        if (s->configuration[21] & BIT(3)) {
1740
          /* Multicast all bit is set, receive all multicast frames. */
1741
        } else {
1742
          unsigned mcast_idx = compute_mcast_idx(buf);
1743
          assert(mcast_idx < 64);
1744
          if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1745
            /* Multicast frame is allowed in hash table. */
1746
          } else if (s->configuration[15] & BIT(0)) {
1747
              /* Promiscuous: receive all. */
1748
              rfd_status |= 0x0004;
1749
          } else {
1750
              TRACE(RXTX, logout("%p multicast ignored\n", s));
1751
              return -1;
1752
          }
1753
        }
1754
        /* TODO: Next not for promiscuous mode? */
1755
        rfd_status |= 0x0002;
1756
    } else if (s->configuration[15] & BIT(0)) {
1757
        /* Promiscuous: receive all. */
1758
        TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1759
        rfd_status |= 0x0004;
1760
    } else {
1761
        TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1762
              nic_dump(buf, size)));
1763
        return size;
1764
    }
1765

    
1766
    if (get_ru_state(s) != ru_ready) {
1767
        /* No resources available. */
1768
        logout("no resources, state=%u\n", get_ru_state(s));
1769
        /* TODO: RNR interrupt only at first failed frame? */
1770
        eepro100_rnr_interrupt(s);
1771
        s->statistics.rx_resource_errors++;
1772
        //~ assert(!"no resources");
1773
        return -1;
1774
    }
1775
    //~ !!!
1776
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1777
    eepro100_rx_t rx;
1778
    cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1779
                             offsetof(eepro100_rx_t, packet));
1780
    uint16_t rfd_command = le16_to_cpu(rx.command);
1781
    uint16_t rfd_size = le16_to_cpu(rx.size);
1782

    
1783
    if (size > rfd_size) {
1784
        logout("Receive buffer (%" PRId16 " bytes) too small for data "
1785
            "(%zu bytes); data truncated\n", rfd_size, size);
1786
        size = rfd_size;
1787
    }
1788
    if (size < 64) {
1789
        rfd_status |= 0x0080;
1790
    }
1791
    TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1792
          rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1793
    stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1794
             rfd_status);
1795
    stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1796
    /* Early receive interrupt not supported. */
1797
    //~ eepro100_er_interrupt(s);
1798
    /* Receive CRC Transfer not supported. */
1799
    if (s->configuration[18] & BIT(2)) {
1800
        missing("Receive CRC Transfer");
1801
        return -1;
1802
    }
1803
    /* TODO: check stripping enable bit. */
1804
    //~ assert(!(s->configuration[17] & BIT(0)));
1805
    cpu_physical_memory_write(s->ru_base + s->ru_offset +
1806
                              offsetof(eepro100_rx_t, packet), buf, size);
1807
    s->statistics.rx_good_frames++;
1808
    eepro100_fr_interrupt(s);
1809
    s->ru_offset = le32_to_cpu(rx.link);
1810
    if (rfd_command & COMMAND_EL) {
1811
        /* EL bit is set, so this was the last frame. */
1812
        logout("receive: Running out of frames\n");
1813
        set_ru_state(s, ru_suspended);
1814
    }
1815
    if (rfd_command & COMMAND_S) {
1816
        /* S bit is set. */
1817
        set_ru_state(s, ru_suspended);
1818
    }
1819
    return size;
1820
}
1821

    
1822
static const VMStateDescription vmstate_eepro100 = {
1823
    .version_id = 3,
1824
    .minimum_version_id = 2,
1825
    .minimum_version_id_old = 2,
1826
    .fields      = (VMStateField []) {
1827
        VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1828
        VMSTATE_UNUSED(32),
1829
        VMSTATE_BUFFER(mult, EEPRO100State),
1830
        VMSTATE_BUFFER(mem, EEPRO100State),
1831
        /* Save all members of struct between scb_stat and mem. */
1832
        VMSTATE_UINT8(scb_stat, EEPRO100State),
1833
        VMSTATE_UINT8(int_stat, EEPRO100State),
1834
        VMSTATE_UNUSED(3*4),
1835
        VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1836
        VMSTATE_UNUSED(19*4),
1837
        VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1838
        /* The eeprom should be saved and restored by its own routines. */
1839
        VMSTATE_UINT32(device, EEPRO100State),
1840
        /* TODO check device. */
1841
        VMSTATE_UINT32(pointer, EEPRO100State),
1842
        VMSTATE_UINT32(cu_base, EEPRO100State),
1843
        VMSTATE_UINT32(cu_offset, EEPRO100State),
1844
        VMSTATE_UINT32(ru_base, EEPRO100State),
1845
        VMSTATE_UINT32(ru_offset, EEPRO100State),
1846
        VMSTATE_UINT32(statsaddr, EEPRO100State),
1847
        /* Save eepro100_stats_t statistics. */
1848
        VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1849
        VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1850
        VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1851
        VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1852
        VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1853
        VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1854
        VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1855
        VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1856
        VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1857
        VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1858
        VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1859
        VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1860
        VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1861
        VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1862
        VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1863
        VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1864
        VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1865
        VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1866
        VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1867
        VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1868
        VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1869
#if 0
1870
        VMSTATE_UINT16(status, EEPRO100State),
1871
#endif
1872
        /* Configuration bytes. */
1873
        VMSTATE_BUFFER(configuration, EEPRO100State),
1874
        VMSTATE_END_OF_LIST()
1875
    }
1876
};
1877

    
1878
static void nic_cleanup(VLANClientState *nc)
1879
{
1880
    EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1881

    
1882
    s->nic = NULL;
1883
}
1884

    
1885
static int pci_nic_uninit(PCIDevice *pci_dev)
1886
{
1887
    EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1888

    
1889
    cpu_unregister_io_memory(s->mmio_index);
1890
    vmstate_unregister(s->vmstate, s);
1891
    eeprom93xx_free(s->eeprom);
1892
    qemu_del_vlan_client(&s->nic->nc);
1893
    return 0;
1894
}
1895

    
1896
static NetClientInfo net_eepro100_info = {
1897
    .type = NET_CLIENT_TYPE_NIC,
1898
    .size = sizeof(NICState),
1899
    .can_receive = nic_can_receive,
1900
    .receive = nic_receive,
1901
    .cleanup = nic_cleanup,
1902
};
1903

    
1904
static int nic_init(PCIDevice *pci_dev, uint32_t device)
1905
{
1906
    EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1907

    
1908
    TRACE(OTHER, logout("\n"));
1909

    
1910
    s->device = device;
1911

    
1912
    pci_reset(s);
1913

    
1914
    /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1915
     * i82559 and later support 64 or 256 word EEPROM. */
1916
    s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1917

    
1918
    /* Handler for memory-mapped I/O */
1919
    s->mmio_index =
1920
        cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1921

    
1922
    pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1923
                           PCI_BASE_ADDRESS_SPACE_MEMORY |
1924
                           PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1925
    pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1926
                           pci_map);
1927
    pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1928
                           pci_mmio_map);
1929

    
1930
    qemu_macaddr_default_if_unset(&s->conf.macaddr);
1931
    logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1932
    assert(s->region[1] == 0);
1933

    
1934
    nic_reset(s);
1935

    
1936
    s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1937
                          pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1938

    
1939
    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1940
    TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1941

    
1942
    qemu_register_reset(nic_reset, s);
1943

    
1944
    s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1945
    memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1946
    s->vmstate->name = s->nic->nc.model;
1947
    vmstate_register(-1, s->vmstate, s);
1948

    
1949
    return 0;
1950
}
1951

    
1952
static int pci_i82550_init(PCIDevice *pci_dev)
1953
{
1954
    return nic_init(pci_dev, i82550);
1955
}
1956

    
1957
static int pci_i82551_init(PCIDevice *pci_dev)
1958
{
1959
    return nic_init(pci_dev, i82551);
1960
}
1961

    
1962
static int pci_i82557a_init(PCIDevice *pci_dev)
1963
{
1964
    return nic_init(pci_dev, i82557A);
1965
}
1966

    
1967
static int pci_i82557b_init(PCIDevice *pci_dev)
1968
{
1969
    return nic_init(pci_dev, i82557B);
1970
}
1971

    
1972
static int pci_i82557c_init(PCIDevice *pci_dev)
1973
{
1974
    return nic_init(pci_dev, i82557C);
1975
}
1976

    
1977
static int pci_i82558a_init(PCIDevice *pci_dev)
1978
{
1979
    return nic_init(pci_dev, i82558A);
1980
}
1981

    
1982
static int pci_i82558b_init(PCIDevice *pci_dev)
1983
{
1984
    return nic_init(pci_dev, i82558B);
1985
}
1986

    
1987
static int pci_i82559a_init(PCIDevice *pci_dev)
1988
{
1989
    return nic_init(pci_dev, i82559A);
1990
}
1991

    
1992
static int pci_i82559b_init(PCIDevice *pci_dev)
1993
{
1994
    return nic_init(pci_dev, i82559B);
1995
}
1996

    
1997
static int pci_i82559c_init(PCIDevice *pci_dev)
1998
{
1999
    return nic_init(pci_dev, i82559C);
2000
}
2001

    
2002
static int pci_i82559er_init(PCIDevice *pci_dev)
2003
{
2004
    return nic_init(pci_dev, i82559ER);
2005
}
2006

    
2007
static int pci_i82562_init(PCIDevice *pci_dev)
2008
{
2009
    return nic_init(pci_dev, i82562);
2010
}
2011

    
2012
static PCIDeviceInfo eepro100_info[] = {
2013
    {
2014
        .qdev.name = "i82550",
2015
        .qdev.desc = "Intel i82550 Ethernet",
2016
        .qdev.size = sizeof(EEPRO100State),
2017
        .init      = pci_i82550_init,
2018
        .exit      = pci_nic_uninit,
2019
        .romfile   = "gpxe-eepro100-80861209.rom",
2020
        .qdev.props = (Property[]) {
2021
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2022
            DEFINE_PROP_END_OF_LIST(),
2023
        },
2024
    },{
2025
        .qdev.name = "i82551",
2026
        .qdev.desc = "Intel i82551 Ethernet",
2027
        .qdev.size = sizeof(EEPRO100State),
2028
        .init      = pci_i82551_init,
2029
        .exit      = pci_nic_uninit,
2030
        .romfile   = "gpxe-eepro100-80861209.rom",
2031
        .qdev.props = (Property[]) {
2032
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2033
            DEFINE_PROP_END_OF_LIST(),
2034
        },
2035
    },{
2036
        .qdev.name = "i82557a",
2037
        .qdev.desc = "Intel i82557A Ethernet",
2038
        .qdev.size = sizeof(EEPRO100State),
2039
        .init      = pci_i82557a_init,
2040
        .exit      = pci_nic_uninit,
2041
        .romfile   = "gpxe-eepro100-80861229.rom",
2042
        .qdev.props = (Property[]) {
2043
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2044
            DEFINE_PROP_END_OF_LIST(),
2045
        },
2046
    },{
2047
        .qdev.name = "i82557b",
2048
        .qdev.desc = "Intel i82557B Ethernet",
2049
        .qdev.size = sizeof(EEPRO100State),
2050
        .init      = pci_i82557b_init,
2051
        .exit      = pci_nic_uninit,
2052
        .romfile   = "gpxe-eepro100-80861229.rom",
2053
        .qdev.props = (Property[]) {
2054
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2055
            DEFINE_PROP_END_OF_LIST(),
2056
        },
2057
    },{
2058
        .qdev.name = "i82557c",
2059
        .qdev.desc = "Intel i82557C Ethernet",
2060
        .qdev.size = sizeof(EEPRO100State),
2061
        .init      = pci_i82557c_init,
2062
        .exit      = pci_nic_uninit,
2063
        .romfile   = "gpxe-eepro100-80861229.rom",
2064
        .qdev.props = (Property[]) {
2065
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2066
            DEFINE_PROP_END_OF_LIST(),
2067
        },
2068
    },{
2069
        .qdev.name = "i82558a",
2070
        .qdev.desc = "Intel i82558A Ethernet",
2071
        .qdev.size = sizeof(EEPRO100State),
2072
        .init      = pci_i82558a_init,
2073
        .exit      = pci_nic_uninit,
2074
        .romfile   = "gpxe-eepro100-80861229.rom",
2075
        .qdev.props = (Property[]) {
2076
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2077
            DEFINE_PROP_END_OF_LIST(),
2078
        },
2079
    },{
2080
        .qdev.name = "i82558b",
2081
        .qdev.desc = "Intel i82558B Ethernet",
2082
        .qdev.size = sizeof(EEPRO100State),
2083
        .init      = pci_i82558b_init,
2084
        .exit      = pci_nic_uninit,
2085
        .romfile   = "gpxe-eepro100-80861229.rom",
2086
        .qdev.props = (Property[]) {
2087
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2088
            DEFINE_PROP_END_OF_LIST(),
2089
        },
2090
    },{
2091
        .qdev.name = "i82559a",
2092
        .qdev.desc = "Intel i82559A Ethernet",
2093
        .qdev.size = sizeof(EEPRO100State),
2094
        .init      = pci_i82559a_init,
2095
        .exit      = pci_nic_uninit,
2096
        .romfile   = "gpxe-eepro100-80861229.rom",
2097
        .qdev.props = (Property[]) {
2098
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2099
            DEFINE_PROP_END_OF_LIST(),
2100
        },
2101
    },{
2102
        .qdev.name = "i82559b",
2103
        .qdev.desc = "Intel i82559B Ethernet",
2104
        .qdev.size = sizeof(EEPRO100State),
2105
        .init      = pci_i82559b_init,
2106
        .exit      = pci_nic_uninit,
2107
        .romfile   = "gpxe-eepro100-80861229.rom",
2108
        .qdev.props = (Property[]) {
2109
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2110
            DEFINE_PROP_END_OF_LIST(),
2111
        },
2112
    },{
2113
        .qdev.name = "i82559c",
2114
        .qdev.desc = "Intel i82559C Ethernet",
2115
        .qdev.size = sizeof(EEPRO100State),
2116
        .init      = pci_i82559c_init,
2117
        .exit      = pci_nic_uninit,
2118
        .romfile   = "gpxe-eepro100-80861229.rom",
2119
        .qdev.props = (Property[]) {
2120
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2121
            DEFINE_PROP_END_OF_LIST(),
2122
        },
2123
    },{
2124
        .qdev.name = "i82559er",
2125
        .qdev.desc = "Intel i82559ER Ethernet",
2126
        .qdev.size = sizeof(EEPRO100State),
2127
        .init      = pci_i82559er_init,
2128
        .exit      = pci_nic_uninit,
2129
        .romfile   = "gpxe-eepro100-80861209.rom",
2130
        .qdev.props = (Property[]) {
2131
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2132
            DEFINE_PROP_END_OF_LIST(),
2133
        },
2134
    },{
2135
        .qdev.name = "i82562",
2136
        .qdev.desc = "Intel i82562 Ethernet",
2137
        .qdev.size = sizeof(EEPRO100State),
2138
        .init      = pci_i82562_init,
2139
        .exit      = pci_nic_uninit,
2140
        .romfile   = "gpxe-eepro100-80861209.rom",
2141
        .qdev.props = (Property[]) {
2142
            DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2143
            DEFINE_PROP_END_OF_LIST(),
2144
        },
2145
    },{
2146
        /* end of list */
2147
    }
2148
};
2149

    
2150
static void eepro100_register_devices(void)
2151
{
2152
    pci_qdev_register_many(eepro100_info);
2153
}
2154

    
2155
device_init(eepro100_register_devices)