Revision 3d2bf4a1 hw/ide.c
b/hw/ide.c | ||
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2700 | 2700 |
} |
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/***********************************************************/ |
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/* MMIO based ide port |
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* This emulates IDE device connected directly to the CPU bus without |
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* dedicated ide controller, which is often seen on embedded boards. |
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*/ |
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|
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typedef struct { |
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IDEBus *bus; |
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int shift; |
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} MMIOState; |
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|
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static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) |
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{ |
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MMIOState *s = (MMIOState*)opaque; |
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IDEBus *bus = s->bus; |
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addr >>= s->shift; |
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if (addr & 7) |
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return ide_ioport_read(bus, addr); |
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else |
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return ide_data_readw(bus, 0); |
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} |
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|
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static void mmio_ide_write (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MMIOState *s = (MMIOState*)opaque; |
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IDEBus *bus = s->bus; |
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addr >>= s->shift; |
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if (addr & 7) |
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ide_ioport_write(bus, addr, val); |
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else |
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ide_data_writew(bus, 0, val); |
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} |
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|
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static CPUReadMemoryFunc * const mmio_ide_reads[] = { |
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mmio_ide_read, |
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mmio_ide_read, |
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mmio_ide_read, |
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}; |
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|
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static CPUWriteMemoryFunc * const mmio_ide_writes[] = { |
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mmio_ide_write, |
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mmio_ide_write, |
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mmio_ide_write, |
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}; |
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|
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static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) |
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{ |
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MMIOState *s= (MMIOState*)opaque; |
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IDEBus *bus = s->bus; |
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return ide_status_read(bus, 0); |
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} |
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|
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static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MMIOState *s = (MMIOState*)opaque; |
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IDEBus *bus = s->bus; |
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ide_cmd_write(bus, 0, val); |
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} |
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|
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static CPUReadMemoryFunc * const mmio_ide_status[] = { |
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mmio_ide_status_read, |
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mmio_ide_status_read, |
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mmio_ide_status_read, |
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}; |
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|
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static CPUWriteMemoryFunc * const mmio_ide_cmd[] = { |
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mmio_ide_cmd_write, |
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mmio_ide_cmd_write, |
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mmio_ide_cmd_write, |
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}; |
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|
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void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, |
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qemu_irq irq, int shift, |
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BlockDriverState *hd0, BlockDriverState *hd1) |
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{ |
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MMIOState *s = qemu_mallocz(sizeof(MMIOState)); |
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IDEBus *bus = qemu_mallocz(sizeof(*bus)); |
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int mem1, mem2; |
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ide_init2(bus, hd0, hd1, irq); |
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s->bus = bus; |
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s->shift = shift; |
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mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s); |
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mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s); |
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cpu_register_physical_memory(membase, 16 << shift, mem1); |
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cpu_register_physical_memory(membase2, 2 << shift, mem2); |
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} |
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|
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/***********************************************************/ |
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/* CF-ATA Microdrive */ |
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#define METADATA_SIZE 0x20 |
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