Revision 3d7b417e target-ppc/cpu.h
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/* condition register */ |
| 554 | 554 |
uint32_t crf[8]; |
| 555 | 555 |
/* XER */ |
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/* XXX: We use only 5 fields, but we want to keep the structure aligned */ |
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uint8_t xer[8]; |
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target_ulong xer; |
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/* Reservation address */ |
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target_ulong reserve; |
| 560 | 559 |
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/*****************************************************************************/ |
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/* Registers definitions */ |
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#define XER_SO 31 |
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#define XER_OV 30 |
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#define XER_CA 29 |
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#define XER_CMP 8 |
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#define XER_BC 0 |
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#define xer_so env->xer[4]
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#define xer_ov env->xer[6]
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#define xer_ca env->xer[2]
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#define xer_cmp env->xer[1]
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#define xer_bc env->xer[0]
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#define XER_SO 31
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#define XER_OV 30
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#define XER_CA 29
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#define XER_CMP 8
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#define XER_BC 0
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#define xer_so ((env->xer >> XER_SO) & 1)
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#define xer_ov ((env->xer >> XER_OV) & 1)
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#define xer_ca ((env->xer >> XER_CA) & 1)
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#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
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#define xer_bc ((env->xer >> XER_BC) & 0x7F)
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| 844 | 843 |
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/* SPR definitions */ |
| 846 | 845 |
#define SPR_MQ (0x000) |
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