Revision 3deaeab7

b/target-sparc/cpu.h
198 198 
    int interrupt_request;
199 199 
    int halted;
200 200 
    uint32_t mmu_bm;
201 
    uint32_t mmu_ctpr_mask;
202 
    uint32_t mmu_cxr_mask;
203 
    uint32_t mmu_sfsr_mask;
204 
    uint32_t mmu_trcr_mask;
201 205 
    /* NOTE: we allow 8 more registers to handle wrapping */
202 206 
    target_ulong regbase[NWINDOWS * 16 + 8];
203 207 

  		












  

    
      b/target-sparc/helper.c
    
  






  129
  129
  
    

  		





  130
  130
  
    
    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */


  		





  131
  131
  
    
    /* Context base + context number */


  		





  132
  
  
    
    pde_ptr = ((env->mmuregs[1] & ~63)<< 4) + (env->mmuregs[2] << 2);


  		





  
  132
  
    
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);


  		





  133
  133
  
    
    pde = ldl_phys(pde_ptr);


  		





  134
  134
  
    

  		





  135
  135
  
    
    /* Ctx pde */


  		












  

    
      b/target-sparc/op_helper.c
    
  






  591
  591
  
    

  		





  592
  592
  
    
            oldreg = env->mmuregs[reg];


  		





  593
  593
  
    
            switch(reg) {


  		





  594
  
  
    
            case 0:


  		





  
  594
  
    
            case 0: // Control Register


  		





  595
  595
  
    
                env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |


  		





  596
  596
  
    
                                    (T1 & 0x00ffffff);


  		





  597
  597
  
    
                // Mappings generated during no-fault mode or MMU


  		





  ......




  600
  600
  
    
                    (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))


  		





  601
  601
  
    
                    tlb_flush(env, 1);


  		





  602
  602
  
    
                break;


  		





  603
  
  
    
            case 2:


  		





  604
  
  
    
                env->mmuregs[reg] = T1;


  		





  
  603
  
    
            case 1: // Context Table Pointer Register


  		





  
  604
  
    
                env->mmuregs[reg] = T1 & env->mmu_ctpr_mask;


  		





  
  605
  
    
                break;


  		





  
  606
  
    
            case 2: // Context Register


  		





  
  607
  
    
                env->mmuregs[reg] = T1 & env->mmu_cxr_mask;


  		





  605
  608
  
    
                if (oldreg != env->mmuregs[reg]) {


  		





  606
  609
  
    
                    /* we flush when the MMU context changes because


  		





  607
  610
  
    
                       QEMU has no MMU context support */


  		





  608
  611
  
    
                    tlb_flush(env, 1);


  		





  609
  612
  
    
                }


  		





  610
  613
  
    
                break;


  		





  611
  
  
    
            case 3:


  		





  612
  
  
    
            case 4:


  		





  
  614
  
    
            case 3: // Synchronous Fault Status Register with Clear


  		





  
  615
  
    
            case 4: // Synchronous Fault Address Register


  		





  
  616
  
    
                break;


  		





  
  617
  
    
            case 0x10: // TLB Replacement Control Register


  		





  
  618
  
    
                env->mmuregs[reg] = T1 & env->mmu_trcr_mask;


  		





  613
  619
  
    
                break;


  		





  614
  
  
    
            case 0x13:


  		





  615
  
  
    
                env->mmuregs[3] = T1;


  		





  
  620
  
    
            case 0x13: // Synchronous Fault Status Register with Read and Clear


  		





  
  621
  
    
                env->mmuregs[3] = T1 & env->mmu_sfsr_mask;


  		





  616
  622
  
    
                break;


  		





  617
  
  
    
            case 0x14:


  		





  
  623
  
    
            case 0x14: // Synchronous Fault Address Register


  		





  618
  624
  
    
                env->mmuregs[4] = T1;


  		





  619
  625
  
    
                break;


  		





  620
  626
  
    
            default:


  		












  

    
      b/target-sparc/translate.c
    
  






  62
  62
  
    
    uint32_t fpu_version;


  		





  63
  63
  
    
    uint32_t mmu_version;


  		





  64
  64
  
    
    uint32_t mmu_bm;


  		





  
  65
  
    
    uint32_t mmu_ctpr_mask;


  		





  
  66
  
    
    uint32_t mmu_cxr_mask;


  		





  
  67
  
    
    uint32_t mmu_sfsr_mask;


  		





  
  68
  
    
    uint32_t mmu_trcr_mask;


  		





  65
  69
  
    
};


  		





  66
  70
  
    

  		





  67
  71
  
    
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);


  		





  ......




  3758
  3762
  
    
    env->fsr = def->fpu_version;


  		





  3759
  3763
  
    
#if !defined(TARGET_SPARC64)


  		





  3760
  3764
  
    
    env->mmu_bm = def->mmu_bm;


  		





  
  3765
  
    
    env->mmu_ctpr_mask = def->mmu_ctpr_mask;


  		





  
  3766
  
    
    env->mmu_cxr_mask = def->mmu_cxr_mask;


  		





  
  3767
  
    
    env->mmu_sfsr_mask = def->mmu_sfsr_mask;


  		





  
  3768
  
    
    env->mmu_trcr_mask = def->mmu_trcr_mask;


  		





  3761
  3769
  
    
    env->mmuregs[0] |= def->mmu_version;


  		





  3762
  3770
  
    
    cpu_sparc_set_id(env, 0);


  		





  3763
  3771
  
    
#endif


  		





  ......




  3887
  3895
  
    
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */


  		





  3888
  3896
  
    
        .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */


  		





  3889
  3897
  
    
        .mmu_bm = 0x00004000,


  		





  
  3898
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  3899
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  3900
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  3901
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3890
  3902
  
    
    },


  		





  3891
  3903
  
    
    {


  		





  3892
  3904
  
    
        .name = "Fujitsu MB86904",


  		





  ......




  3894
  3906
  
    
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */


  		





  3895
  3907
  
    
        .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */


  		





  3896
  3908
  
    
        .mmu_bm = 0x00004000,


  		





  
  3909
  
    
        .mmu_ctpr_mask = 0x00ffffc0,


  		





  
  3910
  
    
        .mmu_cxr_mask = 0x000000ff,


  		





  
  3911
  
    
        .mmu_sfsr_mask = 0x00016fff,


  		





  
  3912
  
    
        .mmu_trcr_mask = 0x00ffffff,


  		





  3897
  3913
  
    
    },


  		





  3898
  3914
  
    
    {


  		





  3899
  3915
  
    
        .name = "Fujitsu MB86907",


  		





  ......




  3901
  3917
  
    
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */


  		





  3902
  3918
  
    
        .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */


  		





  3903
  3919
  
    
        .mmu_bm = 0x00004000,


  		





  
  3920
  
    
        .mmu_ctpr_mask = 0xffffffc0,


  		





  
  3921
  
    
        .mmu_cxr_mask = 0x000000ff,


  		





  
  3922
  
    
        .mmu_sfsr_mask = 0x00016fff,


  		





  
  3923
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3904
  3924
  
    
    },


  		





  3905
  3925
  
    
    {


  		





  3906
  3926
  
    
        .name = "LSI L64811",


  		





  ......




  3908
  3928
  
    
        .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */


  		





  3909
  3929
  
    
        .mmu_version = 0x10 << 24,


  		





  3910
  3930
  
    
        .mmu_bm = 0x00004000,


  		





  
  3931
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  3932
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  3933
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  3934
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3911
  3935
  
    
    },


  		





  3912
  3936
  
    
    {


  		





  3913
  3937
  
    
        .name = "Cypress CY7C601",


  		





  ......




  3915
  3939
  
    
        .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */


  		





  3916
  3940
  
    
        .mmu_version = 0x10 << 24,


  		





  3917
  3941
  
    
        .mmu_bm = 0x00004000,


  		





  
  3942
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  3943
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  3944
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  3945
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3918
  3946
  
    
    },


  		





  3919
  3947
  
    
    {


  		





  3920
  3948
  
    
        .name = "Cypress CY7C611",


  		





  ......




  3922
  3950
  
    
        .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */


  		





  3923
  3951
  
    
        .mmu_version = 0x10 << 24,


  		





  3924
  3952
  
    
        .mmu_bm = 0x00004000,


  		





  
  3953
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  3954
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  3955
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  3956
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3925
  3957
  
    
    },


  		





  3926
  3958
  
    
    {


  		





  3927
  3959
  
    
        .name = "TI SuperSparc II",


  		





  ......




  3929
  3961
  
    
        .fpu_version = 0 << 17,


  		





  3930
  3962
  
    
        .mmu_version = 0x04000000,


  		





  3931
  3963
  
    
        .mmu_bm = 0x00002000,


  		





  
  3964
  
    
        .mmu_ctpr_mask = 0xffffffc0,


  		





  
  3965
  
    
        .mmu_cxr_mask = 0x0000ffff,


  		





  
  3966
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  3967
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3932
  3968
  
    
    },


  		





  3933
  3969
  
    
    {


  		





  3934
  3970
  
    
        .name = "TI MicroSparc I",


  		





  ......




  3936
  3972
  
    
        .fpu_version = 4 << 17,


  		





  3937
  3973
  
    
        .mmu_version = 0x41000000,


  		





  3938
  3974
  
    
        .mmu_bm = 0x00004000,


  		





  
  3975
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  3976
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  3977
  
    
        .mmu_sfsr_mask = 0x00016fff,


  		





  
  3978
  
    
        .mmu_trcr_mask = 0x0000003f,


  		





  3939
  3979
  
    
    },


  		





  3940
  3980
  
    
    {


  		





  3941
  3981
  
    
        .name = "TI MicroSparc II",


  		





  ......




  3943
  3983
  
    
        .fpu_version = 4 << 17,


  		





  3944
  3984
  
    
        .mmu_version = 0x02000000,


  		





  3945
  3985
  
    
        .mmu_bm = 0x00004000,


  		





  
  3986
  
    
        .mmu_ctpr_mask = 0x00ffffc0,


  		





  
  3987
  
    
        .mmu_cxr_mask = 0x000000ff,


  		





  
  3988
  
    
        .mmu_sfsr_mask = 0x00016bff,


  		





  
  3989
  
    
        .mmu_trcr_mask = 0x00ffffff,


  		





  3946
  3990
  
    
    },


  		





  3947
  3991
  
    
    {


  		





  3948
  3992
  
    
        .name = "TI MicroSparc IIep",


  		





  ......




  3950
  3994
  
    
        .fpu_version = 4 << 17,


  		





  3951
  3995
  
    
        .mmu_version = 0x04000000,


  		





  3952
  3996
  
    
        .mmu_bm = 0x00004000,


  		





  
  3997
  
    
        .mmu_ctpr_mask = 0x00ffffc0,


  		





  
  3998
  
    
        .mmu_cxr_mask = 0x000000ff,


  		





  
  3999
  
    
        .mmu_sfsr_mask = 0x00016bff,


  		





  
  4000
  
    
        .mmu_trcr_mask = 0x00ffffff,


  		





  3953
  4001
  
    
    },


  		





  3954
  4002
  
    
    {


  		





  3955
  4003
  
    
        .name = "TI SuperSparc 51",


  		





  ......




  3957
  4005
  
    
        .fpu_version = 0 << 17,


  		





  3958
  4006
  
    
        .mmu_version = 0x04000000,


  		





  3959
  4007
  
    
        .mmu_bm = 0x00002000,


  		





  
  4008
  
    
        .mmu_ctpr_mask = 0xffffffc0,


  		





  
  4009
  
    
        .mmu_cxr_mask = 0x0000ffff,


  		





  
  4010
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4011
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3960
  4012
  
    
    },


  		





  3961
  4013
  
    
    {


  		





  3962
  4014
  
    
        .name = "TI SuperSparc 61",


  		





  ......




  3964
  4016
  
    
        .fpu_version = 0 << 17,


  		





  3965
  4017
  
    
        .mmu_version = 0x04000000,


  		





  3966
  4018
  
    
        .mmu_bm = 0x00002000,


  		





  
  4019
  
    
        .mmu_ctpr_mask = 0xffffffc0,


  		





  
  4020
  
    
        .mmu_cxr_mask = 0x0000ffff,


  		





  
  4021
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4022
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3967
  4023
  
    
    },


  		





  3968
  4024
  
    
    {


  		





  3969
  4025
  
    
        .name = "Ross RT625",


  		





  ......




  3971
  4027
  
    
        .fpu_version = 1 << 17,


  		





  3972
  4028
  
    
        .mmu_version = 0x1e000000,


  		





  3973
  4029
  
    
        .mmu_bm = 0x00004000,


  		





  
  4030
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  4031
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  4032
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4033
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3974
  4034
  
    
    },


  		





  3975
  4035
  
    
    {


  		





  3976
  4036
  
    
        .name = "Ross RT620",


  		





  ......




  3978
  4038
  
    
        .fpu_version = 1 << 17,


  		





  3979
  4039
  
    
        .mmu_version = 0x1f000000,


  		





  3980
  4040
  
    
        .mmu_bm = 0x00004000,


  		





  
  4041
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  4042
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  4043
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4044
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3981
  4045
  
    
    },


  		





  3982
  4046
  
    
    {


  		





  3983
  4047
  
    
        .name = "BIT B5010",


  		





  ......




  3985
  4049
  
    
        .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */


  		





  3986
  4050
  
    
        .mmu_version = 0x20000000,


  		





  3987
  4051
  
    
        .mmu_bm = 0x00004000,


  		





  
  4052
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  4053
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  4054
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4055
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3988
  4056
  
    
    },


  		





  3989
  4057
  
    
    {


  		





  3990
  4058
  
    
        .name = "Matsushita MN10501",


  		





  ......




  3992
  4060
  
    
        .fpu_version = 0 << 17,


  		





  3993
  4061
  
    
        .mmu_version = 0x50000000,


  		





  3994
  4062
  
    
        .mmu_bm = 0x00004000,


  		





  
  4063
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  4064
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  4065
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4066
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  3995
  4067
  
    
    },


  		





  3996
  4068
  
    
    {


  		





  3997
  4069
  
    
        .name = "Weitek W8601",


  		





  ......




  3999
  4071
  
    
        .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */


  		





  4000
  4072
  
    
        .mmu_version = 0x10 << 24,


  		





  4001
  4073
  
    
        .mmu_bm = 0x00004000,


  		





  
  4074
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  4075
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  4076
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4077
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  4002
  4078
  
    
    },


  		





  4003
  4079
  
    
    {


  		





  4004
  4080
  
    
        .name = "LEON2",


  		





  ......




  4006
  4082
  
    
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */


  		





  4007
  4083
  
    
        .mmu_version = 0xf2000000,


  		





  4008
  4084
  
    
        .mmu_bm = 0x00004000,


  		





  
  4085
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  4086
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  4087
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4088
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  4009
  4089
  
    
    },


  		





  4010
  4090
  
    
    {


  		





  4011
  4091
  
    
        .name = "LEON3",


  		





  ......




  4013
  4093
  
    
        .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */


  		





  4014
  4094
  
    
        .mmu_version = 0xf3000000,


  		





  4015
  4095
  
    
        .mmu_bm = 0x00004000,


  		





  
  4096
  
    
        .mmu_ctpr_mask = 0x007ffff0,


  		





  
  4097
  
    
        .mmu_cxr_mask = 0x0000003f,


  		





  
  4098
  
    
        .mmu_sfsr_mask = 0xffffffff,


  		





  
  4099
  
    
        .mmu_trcr_mask = 0xffffffff,


  		





  4016
  4100
  
    
    },


  		





  4017
  4101
  
    
#endif


  		





  4018
  4102
  
    
};


  		












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