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/*
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* sparc helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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|
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//#define DEBUG_MMU
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|
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/* Sparc MMU emulation */
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|
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/* thread support */
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|
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
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|
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void cpu_lock(void) |
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{
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spin_lock(&global_cpu_lock); |
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} |
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|
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void cpu_unlock(void) |
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{
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spin_unlock(&global_cpu_lock); |
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} |
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|
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#if defined(CONFIG_USER_ONLY)
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|
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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|
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#else
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|
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
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static const int access_table[8][8] = { |
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{ 0, 0, 0, 0, 2, 0, 3, 3 },
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{ 0, 0, 0, 0, 2, 0, 0, 0 },
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{ 2, 2, 0, 0, 0, 2, 3, 3 },
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{ 2, 2, 0, 0, 0, 2, 0, 0 },
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{ 2, 0, 2, 0, 2, 2, 3, 3 },
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{ 2, 0, 2, 0, 2, 0, 2, 0 },
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{ 2, 2, 2, 0, 2, 2, 3, 3 },
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{ 2, 2, 2, 0, 2, 2, 2, 0 }
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}; |
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|
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static const int perm_table[2][8] = { |
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{
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC |
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}, |
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{
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ, |
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0,
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0,
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} |
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}; |
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|
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int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
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int *access_index, target_ulong address, int rw, |
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int mmu_idx)
|
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{
|
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int access_perms = 0; |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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target_ulong virt_addr; |
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int error_code = 0, is_dirty, is_user; |
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unsigned long page_offset; |
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|
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is_user = mmu_idx == MMU_USER_IDX; |
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virt_addr = address & TARGET_PAGE_MASK; |
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|
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
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// Boot mode: instruction fetches are taken from PROM
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if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) { |
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC; |
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return 0; |
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} |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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return 0; |
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} |
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|
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
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*physical = 0xffffffffffff0000ULL;
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|
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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|
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return 1 << 2; |
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case 2: /* L0 PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 4 << 2; |
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case 1: /* L0 PDE */ |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (1 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (1 << 8) | (4 << 2); |
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case 1: /* L1 PDE */ |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (2 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (2 << 8) | (4 << 2); |
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case 1: /* L2 PDE */ |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (3 << 8) | (1 << 2); |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return (3 << 8) | (4 << 2); |
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case 2: /* L3 PTE */ |
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virt_addr = address & TARGET_PAGE_MASK; |
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
|
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} |
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break;
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case 2: /* L2 PTE */ |
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virt_addr = address & ~0x3ffff;
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page_offset = address & 0x3ffff;
|
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} |
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break;
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case 2: /* L1 PTE */ |
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virt_addr = address & ~0xffffff;
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page_offset = address & 0xffffff;
|
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} |
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} |
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|
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK; |
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if (is_dirty)
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pde |= PG_MODIFIED_MASK; |
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stl_phys_notdirty(pde_ptr, pde); |
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} |
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
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error_code = access_table[*access_index][access_perms]; |
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
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return error_code;
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|
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms]; |
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE; |
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} |
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|
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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} |
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|
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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target_phys_addr_t paddr; |
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target_ulong vaddr; |
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int error_code = 0, prot, ret = 0, access_index; |
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|
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
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if (error_code == 0) { |
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vaddr = address & TARGET_PAGE_MASK; |
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paddr &= TARGET_PAGE_MASK; |
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#ifdef DEBUG_MMU
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
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TARGET_FMT_lx "\n", address, paddr, vaddr);
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#endif
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
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return ret;
|
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} |
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|
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if (env->mmuregs[3]) /* Fault status register */ |
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
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env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
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env->mmuregs[4] = address; /* Fault address register */ |
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|
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK; |
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
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return ret;
|
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} else {
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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} |
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|
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target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
|
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{
|
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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|
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/* Context base + context number */
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pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
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(env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
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case 2: /* PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 0; |
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case 1: /* L1 PDE */ |
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if (mmulev == 3) |
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return pde;
|
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L1 PTE */ |
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return pde;
|
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case 1: /* L2 PDE */ |
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if (mmulev == 2) |
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return pde;
|
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L2 PTE */ |
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return pde;
|
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case 1: /* L3 PDE */ |
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if (mmulev == 1) |
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return pde;
|
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L3 PTE */ |
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return pde;
|
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} |
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} |
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} |
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} |
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return 0; |
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} |
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|
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#ifdef DEBUG_MMU
|
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void dump_mmu(CPUState *env)
|
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{
|
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target_ulong va, va1, va2; |
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unsigned int n, m, o; |
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target_phys_addr_t pde_ptr, pa; |
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uint32_t pde; |
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|
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printf("MMU dump:\n");
|
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
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(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
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for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
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pde = mmu_probe(env, va, 2);
|
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if (pde) {
|
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pa = cpu_get_phys_page_debug(env, va); |
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
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" PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
| 343 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
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pde = mmu_probe(env, va1, 1);
|
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if (pde) {
|
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pa = cpu_get_phys_page_debug(env, va1); |
| 347 |
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
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" PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
| 349 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
| 350 |
pde = mmu_probe(env, va2, 0);
|
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if (pde) {
|
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pa = cpu_get_phys_page_debug(env, va2); |
| 353 |
printf(" VA: " TARGET_FMT_lx ", PA: " |
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TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
| 355 |
va2, pa, pde); |
| 356 |
} |
| 357 |
} |
| 358 |
} |
| 359 |
} |
| 360 |
} |
| 361 |
} |
| 362 |
printf("MMU dump ends\n");
|
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} |
| 364 |
#endif /* DEBUG_MMU */ |
| 365 |
|
| 366 |
#else /* !TARGET_SPARC64 */ |
| 367 |
/*
|
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* UltraSparc IIi I/DMMUs
|
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*/
|
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static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
| 371 |
int *access_index, target_ulong address, int rw, |
| 372 |
int is_user)
|
| 373 |
{
|
| 374 |
target_ulong mask; |
| 375 |
unsigned int i; |
| 376 |
|
| 377 |
if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
| 378 |
*physical = address; |
| 379 |
*prot = PAGE_READ | PAGE_WRITE; |
| 380 |
return 0; |
| 381 |
} |
| 382 |
|
| 383 |
for (i = 0; i < 64; i++) { |
| 384 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
| 385 |
default:
|
| 386 |
case 0x0: // 8k |
| 387 |
mask = 0xffffffffffffe000ULL;
|
| 388 |
break;
|
| 389 |
case 0x1: // 64k |
| 390 |
mask = 0xffffffffffff0000ULL;
|
| 391 |
break;
|
| 392 |
case 0x2: // 512k |
| 393 |
mask = 0xfffffffffff80000ULL;
|
| 394 |
break;
|
| 395 |
case 0x3: // 4M |
| 396 |
mask = 0xffffffffffc00000ULL;
|
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break;
|
| 398 |
} |
| 399 |
// ctx match, vaddr match?
|
| 400 |
if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
| 401 |
(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
| 402 |
// valid, access ok?
|
| 403 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || |
| 404 |
((env->dtlb_tte[i] & 0x4) && is_user) ||
|
| 405 |
(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
| 406 |
if (env->dmmuregs[3]) /* Fault status register */ |
| 407 |
env->dmmuregs[3] = 2; /* overflow (not read before another fault) */ |
| 408 |
env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
| 409 |
env->dmmuregs[4] = address; /* Fault address register */ |
| 410 |
env->exception_index = TT_DFAULT; |
| 411 |
#ifdef DEBUG_MMU
|
| 412 |
printf("DFAULT at 0x%" PRIx64 "\n", address); |
| 413 |
#endif
|
| 414 |
return 1; |
| 415 |
} |
| 416 |
*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
| 417 |
*prot = PAGE_READ; |
| 418 |
if (env->dtlb_tte[i] & 0x2) |
| 419 |
*prot |= PAGE_WRITE; |
| 420 |
return 0; |
| 421 |
} |
| 422 |
} |
| 423 |
#ifdef DEBUG_MMU
|
| 424 |
printf("DMISS at 0x%" PRIx64 "\n", address); |
| 425 |
#endif
|
| 426 |
env->exception_index = TT_DMISS; |
| 427 |
return 1; |
| 428 |
} |
| 429 |
|
| 430 |
static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, |
| 431 |
int *access_index, target_ulong address, int rw, |
| 432 |
int is_user)
|
| 433 |
{
|
| 434 |
target_ulong mask; |
| 435 |
unsigned int i; |
| 436 |
|
| 437 |
if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
| 438 |
*physical = address; |
| 439 |
*prot = PAGE_EXEC; |
| 440 |
return 0; |
| 441 |
} |
| 442 |
|
| 443 |
for (i = 0; i < 64; i++) { |
| 444 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
| 445 |
default:
|
| 446 |
case 0x0: // 8k |
| 447 |
mask = 0xffffffffffffe000ULL;
|
| 448 |
break;
|
| 449 |
case 0x1: // 64k |
| 450 |
mask = 0xffffffffffff0000ULL;
|
| 451 |
break;
|
| 452 |
case 0x2: // 512k |
| 453 |
mask = 0xfffffffffff80000ULL;
|
| 454 |
break;
|
| 455 |
case 0x3: // 4M |
| 456 |
mask = 0xffffffffffc00000ULL;
|
| 457 |
break;
|
| 458 |
} |
| 459 |
// ctx match, vaddr match?
|
| 460 |
if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
| 461 |
(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
| 462 |
// valid, access ok?
|
| 463 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
| 464 |
((env->itlb_tte[i] & 0x4) && is_user)) {
|
| 465 |
if (env->immuregs[3]) /* Fault status register */ |
| 466 |
env->immuregs[3] = 2; /* overflow (not read before another fault) */ |
| 467 |
env->immuregs[3] |= (is_user << 3) | 1; |
| 468 |
env->exception_index = TT_TFAULT; |
| 469 |
#ifdef DEBUG_MMU
|
| 470 |
printf("TFAULT at 0x%" PRIx64 "\n", address); |
| 471 |
#endif
|
| 472 |
return 1; |
| 473 |
} |
| 474 |
*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
| 475 |
*prot = PAGE_EXEC; |
| 476 |
return 0; |
| 477 |
} |
| 478 |
} |
| 479 |
#ifdef DEBUG_MMU
|
| 480 |
printf("TMISS at 0x%" PRIx64 "\n", address); |
| 481 |
#endif
|
| 482 |
env->exception_index = TT_TMISS; |
| 483 |
return 1; |
| 484 |
} |
| 485 |
|
| 486 |
int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot, |
| 487 |
int *access_index, target_ulong address, int rw, |
| 488 |
int mmu_idx)
|
| 489 |
{
|
| 490 |
int is_user = mmu_idx == MMU_USER_IDX;
|
| 491 |
|
| 492 |
if (rw == 2) |
| 493 |
return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
|
| 494 |
else
|
| 495 |
return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
|
| 496 |
} |
| 497 |
|
| 498 |
/* Perform address translation */
|
| 499 |
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 500 |
int mmu_idx, int is_softmmu) |
| 501 |
{
|
| 502 |
target_ulong virt_addr, vaddr; |
| 503 |
target_phys_addr_t paddr; |
| 504 |
int error_code = 0, prot, ret = 0, access_index; |
| 505 |
|
| 506 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
| 507 |
if (error_code == 0) { |
| 508 |
virt_addr = address & TARGET_PAGE_MASK; |
| 509 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
|
| 510 |
#ifdef DEBUG_MMU
|
| 511 |
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr); |
| 512 |
#endif
|
| 513 |
ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
| 514 |
return ret;
|
| 515 |
} |
| 516 |
// XXX
|
| 517 |
return 1; |
| 518 |
} |
| 519 |
|
| 520 |
#ifdef DEBUG_MMU
|
| 521 |
void dump_mmu(CPUState *env)
|
| 522 |
{
|
| 523 |
unsigned int i; |
| 524 |
const char *mask; |
| 525 |
|
| 526 |
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]); |
| 527 |
if ((env->lsu & DMMU_E) == 0) { |
| 528 |
printf("DMMU disabled\n");
|
| 529 |
} else {
|
| 530 |
printf("DMMU dump:\n");
|
| 531 |
for (i = 0; i < 64; i++) { |
| 532 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
| 533 |
default:
|
| 534 |
case 0x0: |
| 535 |
mask = " 8k";
|
| 536 |
break;
|
| 537 |
case 0x1: |
| 538 |
mask = " 64k";
|
| 539 |
break;
|
| 540 |
case 0x2: |
| 541 |
mask = "512k";
|
| 542 |
break;
|
| 543 |
case 0x3: |
| 544 |
mask = " 4M";
|
| 545 |
break;
|
| 546 |
} |
| 547 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
| 548 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n", |
| 549 |
env->dtlb_tag[i] & ~0x1fffULL,
|
| 550 |
env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
| 551 |
mask, |
| 552 |
env->dtlb_tte[i] & 0x4? "priv": "user", |
| 553 |
env->dtlb_tte[i] & 0x2? "RW": "RO", |
| 554 |
env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
| 555 |
env->dtlb_tag[i] & 0x1fffULL);
|
| 556 |
} |
| 557 |
} |
| 558 |
} |
| 559 |
if ((env->lsu & IMMU_E) == 0) { |
| 560 |
printf("IMMU disabled\n");
|
| 561 |
} else {
|
| 562 |
printf("IMMU dump:\n");
|
| 563 |
for (i = 0; i < 64; i++) { |
| 564 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
| 565 |
default:
|
| 566 |
case 0x0: |
| 567 |
mask = " 8k";
|
| 568 |
break;
|
| 569 |
case 0x1: |
| 570 |
mask = " 64k";
|
| 571 |
break;
|
| 572 |
case 0x2: |
| 573 |
mask = "512k";
|
| 574 |
break;
|
| 575 |
case 0x3: |
| 576 |
mask = " 4M";
|
| 577 |
break;
|
| 578 |
} |
| 579 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
| 580 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n", |
| 581 |
env->itlb_tag[i] & ~0x1fffULL,
|
| 582 |
env->itlb_tte[i] & 0x1ffffffe000ULL,
|
| 583 |
mask, |
| 584 |
env->itlb_tte[i] & 0x4? "priv": "user", |
| 585 |
env->itlb_tte[i] & 0x40? "locked": "unlocked", |
| 586 |
env->itlb_tag[i] & 0x1fffULL);
|
| 587 |
} |
| 588 |
} |
| 589 |
} |
| 590 |
} |
| 591 |
#endif /* DEBUG_MMU */ |
| 592 |
|
| 593 |
#endif /* TARGET_SPARC64 */ |
| 594 |
#endif /* !CONFIG_USER_ONLY */ |
| 595 |
|
| 596 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
| 597 |
{
|
| 598 |
dst[0] = src[0]; |
| 599 |
dst[1] = src[1]; |
| 600 |
dst[2] = src[2]; |
| 601 |
dst[3] = src[3]; |
| 602 |
dst[4] = src[4]; |
| 603 |
dst[5] = src[5]; |
| 604 |
dst[6] = src[6]; |
| 605 |
dst[7] = src[7]; |
| 606 |
} |
| 607 |
|
| 608 |
#ifdef TARGET_SPARC64
|
| 609 |
#if !defined(CONFIG_USER_ONLY)
|
| 610 |
#include "qemu-common.h" |
| 611 |
#include "hw/irq.h" |
| 612 |
#include "qemu-timer.h" |
| 613 |
#endif
|
| 614 |
|
| 615 |
void do_tick_set_count(void *opaque, uint64_t count) |
| 616 |
{
|
| 617 |
#if !defined(CONFIG_USER_ONLY)
|
| 618 |
ptimer_set_count(opaque, -count); |
| 619 |
#endif
|
| 620 |
} |
| 621 |
|
| 622 |
uint64_t do_tick_get_count(void *opaque)
|
| 623 |
{
|
| 624 |
#if !defined(CONFIG_USER_ONLY)
|
| 625 |
return -ptimer_get_count(opaque);
|
| 626 |
#else
|
| 627 |
return 0; |
| 628 |
#endif
|
| 629 |
} |
| 630 |
|
| 631 |
void do_tick_set_limit(void *opaque, uint64_t limit) |
| 632 |
{
|
| 633 |
#if !defined(CONFIG_USER_ONLY)
|
| 634 |
ptimer_set_limit(opaque, -limit, 0);
|
| 635 |
#endif
|
| 636 |
} |
| 637 |
#endif
|