Revision 3df3f6fd hw/ne2000.c
b/hw/ne2000.c | ||
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} |
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} |
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static inline void ne2000_dma_update(NE2000State *s, int len) |
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{ |
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s->rsar += len; |
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/* wrap */ |
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/* XXX: check what to do if rsar > stop */ |
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if (s->rsar == s->stop) |
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s->rsar = s->start; |
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if (s->rcnt <= len) { |
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s->rcnt = 0; |
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/* signal end of transfert */ |
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
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} else { |
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s->rcnt -= len; |
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} |
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} |
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static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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NE2000State *s = opaque; |
... | ... | |
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printf("NE2000: asic write val=0x%04x\n", val); |
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#endif |
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if (s->rcnt == 0) |
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return;
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return;
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if (s->dcfg & 0x01) { |
453 | 471 |
/* 16 bit access */ |
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ne2000_mem_writew(s, s->rsar, val); |
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s->rsar += 2; |
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s->rcnt -= 2; |
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ne2000_dma_update(s, 2); |
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} else { |
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/* 8 bit access */ |
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ne2000_mem_writeb(s, s->rsar, val); |
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s->rsar++; |
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s->rcnt--; |
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} |
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/* wrap */ |
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if (s->rsar == s->stop) |
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s->rsar = s->start; |
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if (s->rcnt == 0) { |
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/* signal end of transfert */ |
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
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ne2000_dma_update(s, 1); |
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} |
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} |
472 | 480 |
|
... | ... | |
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if (s->dcfg & 0x01) { |
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/* 16 bit access */ |
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ret = ne2000_mem_readw(s, s->rsar); |
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s->rsar += 2; |
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s->rcnt -= 2; |
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ne2000_dma_update(s, 2); |
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} else { |
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/* 8 bit access */ |
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ret = ne2000_mem_readb(s, s->rsar); |
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s->rsar++; |
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s->rcnt--; |
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} |
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/* wrap */ |
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if (s->rsar == s->stop) |
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s->rsar = s->start; |
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if (s->rcnt == 0) { |
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/* signal end of transfert */ |
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
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ne2000_dma_update(s, 1); |
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} |
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#ifdef DEBUG_NE2000 |
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printf("NE2000: asic read val=0x%04x\n", ret); |
... | ... | |
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printf("NE2000: asic writel val=0x%04x\n", val); |
509 | 507 |
#endif |
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if (s->rcnt == 0) |
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return;
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return;
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/* 32 bit access */ |
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ne2000_mem_writel(s, s->rsar, val); |
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s->rsar += 4; |
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s->rcnt -= 4; |
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/* wrap */ |
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if (s->rsar == s->stop) |
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s->rsar = s->start; |
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if (s->rcnt == 0) { |
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/* signal end of transfert */ |
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
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} |
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ne2000_dma_update(s, 4); |
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} |
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static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
... | ... | |
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/* 32 bit access */ |
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ret = ne2000_mem_readl(s, s->rsar); |
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s->rsar += 4; |
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s->rcnt -= 4; |
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/* wrap */ |
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if (s->rsar == s->stop) |
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s->rsar = s->start; |
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if (s->rcnt == 0) { |
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/* signal end of transfert */ |
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
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} |
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ne2000_dma_update(s, 4); |
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#ifdef DEBUG_NE2000 |
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printf("NE2000: asic readl val=0x%04x\n", ret); |
546 | 525 |
#endif |
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