Revision 3e382bc8

b/target-mips/helper.c
332 332 
        } else {
333 333 
            env->CP0_ErrorEPC = env->PC;
334 334 
        }
335 
        env->hflags = MIPS_HFLAG_ERL;
335 
        env->hflags |= MIPS_HFLAG_ERL;
336 
	env->CP0_Status |= (1 << CP0St_ERL);
336 337 
        pc = 0xBFC00000;
337 338 
        break;
338 339 
    case EXCP_MCHECK:
......
396 397 
            pc = 0x80000000;
397 398 
        }
398 399 
        env->hflags |= MIPS_HFLAG_EXL;
400 
	env->CP0_Status |= (1 << CP0St_EXL);
399 401 
        pc += offset;
400 402 
        env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
401 403 
        if (env->hflags & MIPS_HFLAG_BMASK) {
b/target-mips/op.c
1104 1104 
    if (env->hflags & MIPS_HFLAG_ERL) {
1105 1105 
        env->PC = env->CP0_ErrorEPC;
1106 1106 
        env->hflags &= ~MIPS_HFLAG_ERL;
1107 
	env->CP0_Status &= ~(1 << CP0St_ERL);
1107 1108 
    } else {
1108 1109 
        env->PC = env->CP0_EPC;
1109 1110 
        env->hflags &= ~MIPS_HFLAG_EXL;
1111 
	env->CP0_Status &= ~(1 << CP0St_EXL);
1110 1112 
    }
1111 1113 
    env->CP0_LLAddr = 1;
1112 1114 
}
b/target-mips/op_helper.c
219 219 
        T0 = env->CP0_Status;
220 220 
        if (env->hflags & MIPS_HFLAG_UM)
221 221 
            T0 |= (1 << CP0St_UM);
222 
        if (env->hflags & MIPS_HFLAG_ERL)
223 
            T0 |= (1 << CP0St_ERL);
224 
        if (env->hflags & MIPS_HFLAG_EXL)
225 
            T0 |= (1 << CP0St_EXL);
226 222 
        rn = "Status";
227 223 
        break;
228 224 
    case 13:

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