Revision 3e4587d5 target-mips/translate_init.c
b/target-mips/translate_init.c | ||
---|---|---|
129 | 129 |
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
130 | 130 |
}, |
131 | 131 |
{ |
132 |
.name = "4KEm", |
|
133 |
.CP0_PRid = 0x00019100, |
|
134 |
/* Config1 implemented, MIPS32R2, fixed mapping MMU, |
|
135 |
no virtual icache, uncached coherency. */ |
|
136 |
.CP0_Config0 = (1 << CP0C0_M) | (0x1 << CP0C0_AR) | |
|
137 |
(0x3 << CP0C0_MT) | (0x2 << CP0C0_K0), |
|
138 |
.CP0_Config1 = MIPS_CONFIG1 | |
|
139 |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
|
140 |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
|
141 |
.CP0_Config2 = MIPS_CONFIG2, |
|
142 |
.CP0_Config3 = MIPS_CONFIG3, |
|
143 |
.SYNCI_Step = 32, |
|
144 |
.CCRes = 2, |
|
145 |
.CP0_Status_rw_bitmask = 0x1258FF17, |
|
146 |
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
|
147 |
}, |
|
148 |
{ |
|
132 | 149 |
.name = "24Kc", |
133 | 150 |
.CP0_PRid = 0x00019300, |
134 | 151 |
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), |
... | ... | |
141 | 158 |
.CCRes = 2, |
142 | 159 |
/* No DSP implemented. */ |
143 | 160 |
.CP0_Status_rw_bitmask = 0x1278FF1F, |
144 |
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
|
|
161 |
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
|
145 | 162 |
}, |
146 | 163 |
{ |
147 | 164 |
.name = "24Kf", |
... | ... | |
158 | 175 |
.CP0_Status_rw_bitmask = 0x3678FF1F, |
159 | 176 |
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
160 | 177 |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
161 |
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
|
|
178 |
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
|
162 | 179 |
}, |
163 | 180 |
{ |
164 | 181 |
.name = "34Kf", |
Also available in: Unified diff