Revision 3f582262 hw/pxa2xx.c
| b/hw/pxa2xx.c | ||
|---|---|---|
| 69 | 69 |
#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ |
| 70 | 70 |
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ |
| 71 | 71 |
|
| 72 |
static uint32_t pxa2xx_i2c_read(void *, target_phys_addr_t); |
|
| 73 |
static void pxa2xx_i2c_write(void *, target_phys_addr_t, uint32_t); |
|
| 74 |
|
|
| 72 | 75 |
static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) |
| 73 | 76 |
{
|
| 74 | 77 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
| 78 |
if (addr > s->pm_base + PCMD31) {
|
|
| 79 |
/* Special case: PWRI2C registers appear in the same range. */ |
|
| 80 |
return pxa2xx_i2c_read(s->i2c[1], addr); |
|
| 81 |
} |
|
| 75 | 82 |
addr -= s->pm_base; |
| 76 | 83 |
|
| 77 | 84 |
switch (addr) {
|
| ... | ... | |
| 92 | 99 |
uint32_t value) |
| 93 | 100 |
{
|
| 94 | 101 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
| 102 |
if (addr > s->pm_base + PCMD31) {
|
|
| 103 |
/* Special case: PWRI2C registers appear in the same range. */ |
|
| 104 |
pxa2xx_i2c_write(s->i2c[1], addr, value); |
|
| 105 |
return; |
|
| 106 |
} |
|
| 95 | 107 |
addr -= s->pm_base; |
| 96 | 108 |
|
| 97 | 109 |
switch (addr) {
|
| ... | ... | |
| 1086 | 1098 |
pxa2xx_rtc_write, |
| 1087 | 1099 |
}; |
| 1088 | 1100 |
|
| 1101 |
/* I2C Interface */ |
|
| 1102 |
struct pxa2xx_i2c_s {
|
|
| 1103 |
i2c_slave slave; |
|
| 1104 |
i2c_bus *bus; |
|
| 1105 |
target_phys_addr_t base; |
|
| 1106 |
qemu_irq irq; |
|
| 1107 |
|
|
| 1108 |
uint16_t control; |
|
| 1109 |
uint16_t status; |
|
| 1110 |
uint8_t ibmr; |
|
| 1111 |
uint8_t data; |
|
| 1112 |
}; |
|
| 1113 |
|
|
| 1114 |
#define IBMR 0x80 /* I2C Bus Monitor register */ |
|
| 1115 |
#define IDBR 0x88 /* I2C Data Buffer register */ |
|
| 1116 |
#define ICR 0x90 /* I2C Control register */ |
|
| 1117 |
#define ISR 0x98 /* I2C Status register */ |
|
| 1118 |
#define ISAR 0xa0 /* I2C Slave Address register */ |
|
| 1119 |
|
|
| 1120 |
static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s) |
|
| 1121 |
{
|
|
| 1122 |
uint16_t level = 0; |
|
| 1123 |
level |= s->status & s->control & (1 << 10); /* BED */ |
|
| 1124 |
level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ |
|
| 1125 |
level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ |
|
| 1126 |
level |= s->status & (1 << 9); /* SAD */ |
|
| 1127 |
qemu_set_irq(s->irq, !!level); |
|
| 1128 |
} |
|
| 1129 |
|
|
| 1130 |
/* These are only stubs now. */ |
|
| 1131 |
static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event) |
|
| 1132 |
{
|
|
| 1133 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; |
|
| 1134 |
|
|
| 1135 |
switch (event) {
|
|
| 1136 |
case I2C_START_SEND: |
|
| 1137 |
s->status |= (1 << 9); /* set SAD */ |
|
| 1138 |
s->status &= ~(1 << 0); /* clear RWM */ |
|
| 1139 |
break; |
|
| 1140 |
case I2C_START_RECV: |
|
| 1141 |
s->status |= (1 << 9); /* set SAD */ |
|
| 1142 |
s->status |= 1 << 0; /* set RWM */ |
|
| 1143 |
break; |
|
| 1144 |
case I2C_FINISH: |
|
| 1145 |
s->status |= (1 << 4); /* set SSD */ |
|
| 1146 |
break; |
|
| 1147 |
case I2C_NACK: |
|
| 1148 |
s->status |= 1 << 1; /* set ACKNAK */ |
|
| 1149 |
break; |
|
| 1150 |
} |
|
| 1151 |
pxa2xx_i2c_update(s); |
|
| 1152 |
} |
|
| 1153 |
|
|
| 1154 |
static int pxa2xx_i2c_rx(i2c_slave *i2c) |
|
| 1155 |
{
|
|
| 1156 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; |
|
| 1157 |
if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) |
|
| 1158 |
return 0; |
|
| 1159 |
|
|
| 1160 |
if (s->status & (1 << 0)) { /* RWM */
|
|
| 1161 |
s->status |= 1 << 6; /* set ITE */ |
|
| 1162 |
} |
|
| 1163 |
pxa2xx_i2c_update(s); |
|
| 1164 |
|
|
| 1165 |
return s->data; |
|
| 1166 |
} |
|
| 1167 |
|
|
| 1168 |
static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data) |
|
| 1169 |
{
|
|
| 1170 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; |
|
| 1171 |
if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) |
|
| 1172 |
return 1; |
|
| 1173 |
|
|
| 1174 |
if (!(s->status & (1 << 0))) { /* RWM */
|
|
| 1175 |
s->status |= 1 << 7; /* set IRF */ |
|
| 1176 |
s->data = data; |
|
| 1177 |
} |
|
| 1178 |
pxa2xx_i2c_update(s); |
|
| 1179 |
|
|
| 1180 |
return 1; |
|
| 1181 |
} |
|
| 1182 |
|
|
| 1183 |
static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) |
|
| 1184 |
{
|
|
| 1185 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
|
| 1186 |
addr -= s->base; |
|
| 1187 |
|
|
| 1188 |
switch (addr) {
|
|
| 1189 |
case ICR: |
|
| 1190 |
return s->control; |
|
| 1191 |
case ISR: |
|
| 1192 |
return s->status | (i2c_bus_busy(s->bus) << 2); |
|
| 1193 |
case ISAR: |
|
| 1194 |
return s->slave.address; |
|
| 1195 |
case IDBR: |
|
| 1196 |
return s->data; |
|
| 1197 |
case IBMR: |
|
| 1198 |
if (s->status & (1 << 2)) |
|
| 1199 |
s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ |
|
| 1200 |
else |
|
| 1201 |
s->ibmr = 0; |
|
| 1202 |
return s->ibmr; |
|
| 1203 |
default: |
|
| 1204 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
|
|
| 1205 |
break; |
|
| 1206 |
} |
|
| 1207 |
return 0; |
|
| 1208 |
} |
|
| 1209 |
|
|
| 1210 |
static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, |
|
| 1211 |
uint32_t value) |
|
| 1212 |
{
|
|
| 1213 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
|
| 1214 |
int ack; |
|
| 1215 |
addr -= s->base; |
|
| 1216 |
|
|
| 1217 |
switch (addr) {
|
|
| 1218 |
case ICR: |
|
| 1219 |
s->control = value & 0xfff7; |
|
| 1220 |
if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
|
|
| 1221 |
/* TODO: slave mode */ |
|
| 1222 |
if (value & (1 << 0)) { /* START condition */
|
|
| 1223 |
if (s->data & 1) |
|
| 1224 |
s->status |= 1 << 0; /* set RWM */ |
|
| 1225 |
else |
|
| 1226 |
s->status &= ~(1 << 0); /* clear RWM */ |
|
| 1227 |
ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); |
|
| 1228 |
} else {
|
|
| 1229 |
if (s->status & (1 << 0)) { /* RWM */
|
|
| 1230 |
s->data = i2c_recv(s->bus); |
|
| 1231 |
if (value & (1 << 2)) /* ACKNAK */ |
|
| 1232 |
i2c_nack(s->bus); |
|
| 1233 |
ack = 1; |
|
| 1234 |
} else |
|
| 1235 |
ack = !i2c_send(s->bus, s->data); |
|
| 1236 |
} |
|
| 1237 |
|
|
| 1238 |
if (value & (1 << 1)) /* STOP condition */ |
|
| 1239 |
i2c_end_transfer(s->bus); |
|
| 1240 |
|
|
| 1241 |
if (ack) {
|
|
| 1242 |
if (value & (1 << 0)) /* START condition */ |
|
| 1243 |
s->status |= 1 << 6; /* set ITE */ |
|
| 1244 |
else |
|
| 1245 |
if (s->status & (1 << 0)) /* RWM */ |
|
| 1246 |
s->status |= 1 << 7; /* set IRF */ |
|
| 1247 |
else |
|
| 1248 |
s->status |= 1 << 6; /* set ITE */ |
|
| 1249 |
s->status &= ~(1 << 1); /* clear ACKNAK */ |
|
| 1250 |
} else {
|
|
| 1251 |
s->status |= 1 << 6; /* set ITE */ |
|
| 1252 |
s->status |= 1 << 10; /* set BED */ |
|
| 1253 |
s->status |= 1 << 1; /* set ACKNAK */ |
|
| 1254 |
} |
|
| 1255 |
} |
|
| 1256 |
if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ |
|
| 1257 |
if (value & (1 << 4)) /* MA */ |
|
| 1258 |
i2c_end_transfer(s->bus); |
|
| 1259 |
pxa2xx_i2c_update(s); |
|
| 1260 |
break; |
|
| 1261 |
|
|
| 1262 |
case ISR: |
|
| 1263 |
s->status &= ~(value & 0x07f0); |
|
| 1264 |
pxa2xx_i2c_update(s); |
|
| 1265 |
break; |
|
| 1266 |
|
|
| 1267 |
case ISAR: |
|
| 1268 |
i2c_set_slave_address(&s->slave, value & 0x7f); |
|
| 1269 |
break; |
|
| 1270 |
|
|
| 1271 |
case IDBR: |
|
| 1272 |
s->data = value & 0xff; |
|
| 1273 |
break; |
|
| 1274 |
|
|
| 1275 |
default: |
|
| 1276 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
|
|
| 1277 |
} |
|
| 1278 |
} |
|
| 1279 |
|
|
| 1280 |
static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
|
|
| 1281 |
pxa2xx_i2c_read, |
|
| 1282 |
pxa2xx_i2c_read, |
|
| 1283 |
pxa2xx_i2c_read, |
|
| 1284 |
}; |
|
| 1285 |
|
|
| 1286 |
static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
|
|
| 1287 |
pxa2xx_i2c_write, |
|
| 1288 |
pxa2xx_i2c_write, |
|
| 1289 |
pxa2xx_i2c_write, |
|
| 1290 |
}; |
|
| 1291 |
|
|
| 1292 |
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, |
|
| 1293 |
qemu_irq irq, int ioregister) |
|
| 1294 |
{
|
|
| 1295 |
int iomemtype; |
|
| 1296 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) |
|
| 1297 |
qemu_mallocz(sizeof(struct pxa2xx_i2c_s)); |
|
| 1298 |
|
|
| 1299 |
s->base = base; |
|
| 1300 |
s->irq = irq; |
|
| 1301 |
s->slave.event = pxa2xx_i2c_event; |
|
| 1302 |
s->slave.recv = pxa2xx_i2c_rx; |
|
| 1303 |
s->slave.send = pxa2xx_i2c_tx; |
|
| 1304 |
s->bus = i2c_init_bus(); |
|
| 1305 |
|
|
| 1306 |
if (ioregister) {
|
|
| 1307 |
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn, |
|
| 1308 |
pxa2xx_i2c_writefn, s); |
|
| 1309 |
cpu_register_physical_memory(s->base & 0xfffff000, 0xfff, iomemtype); |
|
| 1310 |
} |
|
| 1311 |
|
|
| 1312 |
return s; |
|
| 1313 |
} |
|
| 1314 |
|
|
| 1315 |
i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s) |
|
| 1316 |
{
|
|
| 1317 |
return s->bus; |
|
| 1318 |
} |
|
| 1319 |
|
|
| 1089 | 1320 |
/* PXA Inter-IC Sound Controller */ |
| 1090 | 1321 |
static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s) |
| 1091 | 1322 |
{
|
| ... | ... | |
| 1544 | 1775 |
s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]); |
| 1545 | 1776 |
|
| 1546 | 1777 |
pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], |
| 1547 |
s->pic[PXA27X_PIC_OST_4_11], s->env);
|
|
| 1778 |
s->pic[PXA27X_PIC_OST_4_11]); |
|
| 1548 | 1779 |
|
| 1549 | 1780 |
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121); |
| 1550 | 1781 |
|
| ... | ... | |
| 1608 | 1839 |
cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype); |
| 1609 | 1840 |
pxa2xx_rtc_reset(s); |
| 1610 | 1841 |
|
| 1842 |
/* Note that PM registers are in the same page with PWRI2C registers. |
|
| 1843 |
* As a workaround we don't map PWRI2C into memory and we expect |
|
| 1844 |
* PM handlers to call PWRI2C handlers when appropriate. */ |
|
| 1845 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1); |
|
| 1846 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0); |
|
| 1847 |
|
|
| 1611 | 1848 |
s->pm_base = 0x40f00000; |
| 1612 | 1849 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn, |
| 1613 | 1850 |
pxa2xx_pm_writefn, s); |
| ... | ... | |
| 1643 | 1880 |
|
| 1644 | 1881 |
s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]); |
| 1645 | 1882 |
|
| 1646 |
pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], s->env);
|
|
| 1883 |
pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]); |
|
| 1647 | 1884 |
|
| 1648 | 1885 |
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85); |
| 1649 | 1886 |
|
| ... | ... | |
| 1707 | 1944 |
cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype); |
| 1708 | 1945 |
pxa2xx_rtc_reset(s); |
| 1709 | 1946 |
|
| 1947 |
/* Note that PM registers are in the same page with PWRI2C registers. |
|
| 1948 |
* As a workaround we don't map PWRI2C into memory and we expect |
|
| 1949 |
* PM handlers to call PWRI2C handlers when appropriate. */ |
|
| 1950 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1); |
|
| 1951 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0); |
|
| 1952 |
|
|
| 1710 | 1953 |
s->pm_base = 0x40f00000; |
| 1711 | 1954 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn, |
| 1712 | 1955 |
pxa2xx_pm_writefn, s); |
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