Revision 3f582262 hw/pxa2xx_dma.c

b/hw/pxa2xx_dma.c
443 443 
    s->base = base;
444 444 
    s->irq = irq;
445 445 
    s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request;
446 
    s->req = qemu_mallocz(sizeof(int) * PXA2XX_DMA_NUM_REQUESTS);
446 
    s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
447 447 

  		





  448
  448
  
    
    memset(s->chan, 0, sizeof(struct pxa2xx_dma_channel_s) * s->channels);


  		





  449
  449
  
    
    for (i = 0; i < s->channels; i ++)


  		





  450
  450
  
    
        s->chan[i].state = DCSR_STOPINTR;


  		





  451
  451
  
    

  		





  452
  
  
    
    memset(s->req, 0, sizeof(int) * PXA2XX_DMA_NUM_REQUESTS);


  		





  
  452
  
    
    memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);


  		





  453
  453
  
    

  		





  454
  454
  
    
    iomemtype = cpu_register_io_memory(0, pxa2xx_dma_readfn,


  		





  455
  
  
    
                   pxa2xx_dma_writefn, s);


  		





  
  455
  
    
                    pxa2xx_dma_writefn, s);


  		





  456
  456
  
    
    cpu_register_physical_memory(base, 0x0000ffff, iomemtype);


  		





  457
  457
  
    

  		





  458
  458
  
    
    return s;


  		












Also available in:
  Unified diff