Revision 3f582262 hw/pxa2xx_timer.c
b/hw/pxa2xx_timer.c | ||
---|---|---|
75 | 75 |
}; |
76 | 76 |
|
77 | 77 |
typedef struct { |
78 |
uint32_t base;
|
|
78 |
target_phys_addr_t base;
|
|
79 | 79 |
int32_t clock; |
80 | 80 |
int32_t oldclock; |
81 | 81 |
uint64_t lastload; |
... | ... | |
85 | 85 |
uint32_t events; |
86 | 86 |
uint32_t irq_enabled; |
87 | 87 |
uint32_t reset3; |
88 |
CPUState *cpustate; |
|
89 |
int64_t qemu_ticks; |
|
90 | 88 |
uint32_t snapshot; |
91 | 89 |
} pxa2xx_timer_info; |
92 | 90 |
|
... | ... | |
121 | 119 |
counter = counters[n]; |
122 | 120 |
|
123 | 121 |
if (!s->tm4[counter].freq) { |
124 |
qemu_del_timer(s->timer[n].qtimer);
|
|
122 |
qemu_del_timer(s->tm4[n].tm.qtimer);
|
|
125 | 123 |
return; |
126 | 124 |
} |
127 | 125 |
|
... | ... | |
131 | 129 |
|
132 | 130 |
new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), |
133 | 131 |
ticks_per_sec, s->tm4[counter].freq); |
134 |
qemu_mod_timer(s->timer[n].qtimer, new_qemu);
|
|
132 |
qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
|
|
135 | 133 |
} |
136 | 134 |
|
137 | 135 |
static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) |
... | ... | |
350 | 348 |
if (t->num == 3) |
351 | 349 |
if (i->reset3 & 1) { |
352 | 350 |
i->reset3 = 0; |
353 |
cpu_reset(i->cpustate);
|
|
351 |
qemu_system_reset_request();
|
|
354 | 352 |
} |
355 | 353 |
} |
356 | 354 |
|
... | ... | |
367 | 365 |
} |
368 | 366 |
|
369 | 367 |
static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base, |
370 |
qemu_irq *irqs, CPUState *cpustate)
|
|
368 |
qemu_irq *irqs) |
|
371 | 369 |
{ |
372 | 370 |
int i; |
373 | 371 |
int iomemtype; |
... | ... | |
380 | 378 |
s->clock = 0; |
381 | 379 |
s->lastload = qemu_get_clock(vm_clock); |
382 | 380 |
s->reset3 = 0; |
383 |
s->cpustate = cpustate; |
|
384 | 381 |
|
385 | 382 |
for (i = 0; i < 4; i ++) { |
386 | 383 |
s->timer[i].value = 0; |
... | ... | |
398 | 395 |
return s; |
399 | 396 |
} |
400 | 397 |
|
401 |
void pxa25x_timer_init(target_phys_addr_t base, |
|
402 |
qemu_irq *irqs, CPUState *cpustate) |
|
398 |
void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs) |
|
403 | 399 |
{ |
404 |
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
|
|
400 |
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); |
|
405 | 401 |
s->freq = PXA25X_FREQ; |
406 | 402 |
s->tm4 = 0; |
407 | 403 |
} |
408 | 404 |
|
409 | 405 |
void pxa27x_timer_init(target_phys_addr_t base, |
410 |
qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate)
|
|
406 |
qemu_irq *irqs, qemu_irq irq4) |
|
411 | 407 |
{ |
412 |
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
|
|
408 |
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); |
|
413 | 409 |
int i; |
414 | 410 |
s->freq = PXA27X_FREQ; |
415 | 411 |
s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 * |
Also available in: Unified diff