Revision 3fc6c082 target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 1 | 1 |
/* |
| 2 |
* PPC emulation for qemu: main translation routines. |
|
| 2 |
* PowerPC emulation for qemu: main translation routines.
|
|
| 3 | 3 |
* |
| 4 |
* Copyright (c) 2003 Jocelyn Mayer |
|
| 4 |
* Copyright (c) 2003-2005 Jocelyn Mayer
|
|
| 5 | 5 |
* |
| 6 | 6 |
* This library is free software; you can redistribute it and/or |
| 7 | 7 |
* modify it under the terms of the GNU Lesser General Public |
| ... | ... | |
| 141 | 141 |
int supervisor; |
| 142 | 142 |
#endif |
| 143 | 143 |
int fpu_enabled; |
| 144 |
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
|
| 144 | 145 |
} DisasContext; |
| 145 | 146 |
|
| 146 |
typedef struct opc_handler_t {
|
|
| 147 |
struct opc_handler_t {
|
|
| 147 | 148 |
/* invalid bits */ |
| 148 | 149 |
uint32_t inval; |
| 149 | 150 |
/* instruction type */ |
| 150 | 151 |
uint32_t type; |
| 151 | 152 |
/* handler */ |
| 152 | 153 |
void (*handler)(DisasContext *ctx); |
| 153 |
} opc_handler_t;
|
|
| 154 |
}; |
|
| 154 | 155 |
|
| 155 | 156 |
#define RET_EXCP(ctx, excp, error) \ |
| 156 | 157 |
do { \
|
| ... | ... | |
| 173 | 174 |
#define RET_MTMSR(ctx) \ |
| 174 | 175 |
RET_EXCP((ctx), EXCP_MTMSR, 0) |
| 175 | 176 |
|
| 177 |
static inline void RET_STOP (DisasContext *ctx) |
|
| 178 |
{
|
|
| 179 |
RET_EXCP(ctx, EXCP_MTMSR, 0); |
|
| 180 |
} |
|
| 181 |
|
|
| 176 | 182 |
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
| 177 | 183 |
static void gen_##name (DisasContext *ctx); \ |
| 178 | 184 |
GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \ |
| ... | ... | |
| 186 | 192 |
unsigned char pad[1]; |
| 187 | 193 |
#endif |
| 188 | 194 |
opc_handler_t handler; |
| 195 |
const unsigned char *oname; |
|
| 189 | 196 |
} opcode_t; |
| 190 | 197 |
|
| 191 | 198 |
/*** Instruction decoding ***/ |
| ... | ... | |
| 226 | 233 |
EXTRACT_HELPER(crbA, 16, 5); |
| 227 | 234 |
EXTRACT_HELPER(crbB, 11, 5); |
| 228 | 235 |
/* SPR / TBL */ |
| 229 |
EXTRACT_HELPER(SPR, 11, 10); |
|
| 236 |
EXTRACT_HELPER(_SPR, 11, 10); |
|
| 237 |
static inline uint32_t SPR (uint32_t opcode) |
|
| 238 |
{
|
|
| 239 |
uint32_t sprn = _SPR(opcode); |
|
| 240 |
|
|
| 241 |
return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
|
| 242 |
} |
|
| 230 | 243 |
/*** Get constants ***/ |
| 231 | 244 |
EXTRACT_HELPER(IMM, 12, 8); |
| 232 | 245 |
/* 16 bits signed immediate value */ |
| ... | ... | |
| 282 | 295 |
return ret; |
| 283 | 296 |
} |
| 284 | 297 |
|
| 298 |
#if HOST_LONG_BITS == 64 |
|
| 299 |
#define OPC_ALIGN 8 |
|
| 300 |
#else |
|
| 301 |
#define OPC_ALIGN 4 |
|
| 302 |
#endif |
|
| 285 | 303 |
#if defined(__APPLE__) |
| 286 | 304 |
#define OPCODES_SECTION \ |
| 287 |
__attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) ))
|
|
| 305 |
__attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
|
|
| 288 | 306 |
#else |
| 289 | 307 |
#define OPCODES_SECTION \ |
| 290 |
__attribute__ ((section(".opcodes"), unused, aligned (8) ))
|
|
| 308 |
__attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
|
|
| 291 | 309 |
#endif |
| 292 | 310 |
|
| 293 | 311 |
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ |
| ... | ... | |
| 301 | 319 |
.type = _typ, \ |
| 302 | 320 |
.handler = &gen_##name, \ |
| 303 | 321 |
}, \ |
| 322 |
.oname = stringify(name), \ |
|
| 304 | 323 |
} |
| 305 | 324 |
|
| 306 | 325 |
#define GEN_OPCODE_MARK(name) \ |
| ... | ... | |
| 314 | 333 |
.type = 0x00, \ |
| 315 | 334 |
.handler = NULL, \ |
| 316 | 335 |
}, \ |
| 336 |
.oname = stringify(name), \ |
|
| 317 | 337 |
} |
| 318 | 338 |
|
| 319 | 339 |
/* Start opcode list */ |
| ... | ... | |
| 1344 | 1364 |
#endif |
| 1345 | 1365 |
|
| 1346 | 1366 |
/* lswi */ |
| 1347 |
/* PPC32 specification says we must generate an exception if |
|
| 1367 |
/* PowerPC32 specification says we must generate an exception if
|
|
| 1348 | 1368 |
* rA is in the range of registers to be loaded. |
| 1349 | 1369 |
* In an other hand, IBM says this is valid, but rA won't be loaded. |
| 1350 | 1370 |
* For now, I'll follow the spec... |
| ... | ... | |
| 1965 | 1985 |
#endif |
| 1966 | 1986 |
} |
| 1967 | 1987 |
|
| 1988 |
#if 0 |
|
| 1989 |
#define SPR_NOACCESS ((void *)(-1)) |
|
| 1990 |
#else |
|
| 1991 |
static void spr_noaccess (void *opaque, int sprn) |
|
| 1992 |
{
|
|
| 1993 |
sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
|
| 1994 |
printf("ERROR: try to access SPR %d !\n", sprn);
|
|
| 1995 |
} |
|
| 1996 |
#define SPR_NOACCESS (&spr_noaccess) |
|
| 1997 |
#endif |
|
| 1998 |
|
|
| 1968 | 1999 |
/* mfspr */ |
| 1969 |
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
|
|
| 2000 |
static inline void gen_op_mfspr (DisasContext *ctx)
|
|
| 1970 | 2001 |
{
|
| 2002 |
void (*read_cb)(void *opaque, int sprn); |
|
| 1971 | 2003 |
uint32_t sprn = SPR(ctx->opcode); |
| 1972 | 2004 |
|
| 1973 |
#if defined(CONFIG_USER_ONLY) |
|
| 1974 |
switch (check_spr_access(sprn, 0, 0))
|
|
| 1975 |
#else
|
|
| 1976 |
switch (check_spr_access(sprn, 0, ctx->supervisor))
|
|
| 2005 |
#if !defined(CONFIG_USER_ONLY)
|
|
| 2006 |
if (ctx->supervisor)
|
|
| 2007 |
read_cb = ctx->spr_cb[sprn].oea_read;
|
|
| 2008 |
else
|
|
| 1977 | 2009 |
#endif |
| 1978 |
{
|
|
| 1979 |
case -1: |
|
| 1980 |
RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
|
| 1981 |
return; |
|
| 1982 |
case 0: |
|
| 2010 |
read_cb = ctx->spr_cb[sprn].uea_read; |
|
| 2011 |
if (read_cb != NULL) {
|
|
| 2012 |
if (read_cb != SPR_NOACCESS) {
|
|
| 2013 |
(*read_cb)(ctx, sprn); |
|
| 2014 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
|
| 2015 |
} else {
|
|
| 2016 |
/* Privilege exception */ |
|
| 2017 |
printf("Trying to read priviledged spr %d %03x\n", sprn, sprn);
|
|
| 1983 | 2018 |
RET_PRIVREG(ctx); |
| 1984 |
return; |
|
| 1985 |
default: |
|
| 1986 |
break; |
|
| 1987 | 2019 |
} |
| 1988 |
switch (sprn) {
|
|
| 1989 |
case XER: |
|
| 1990 |
gen_op_load_xer(); |
|
| 1991 |
break; |
|
| 1992 |
case LR: |
|
| 1993 |
gen_op_load_lr(); |
|
| 1994 |
break; |
|
| 1995 |
case CTR: |
|
| 1996 |
gen_op_load_ctr(); |
|
| 1997 |
break; |
|
| 1998 |
case IBAT0U: |
|
| 1999 |
gen_op_load_ibat(0, 0); |
|
| 2000 |
break; |
|
| 2001 |
case IBAT1U: |
|
| 2002 |
gen_op_load_ibat(0, 1); |
|
| 2003 |
break; |
|
| 2004 |
case IBAT2U: |
|
| 2005 |
gen_op_load_ibat(0, 2); |
|
| 2006 |
break; |
|
| 2007 |
case IBAT3U: |
|
| 2008 |
gen_op_load_ibat(0, 3); |
|
| 2009 |
break; |
|
| 2010 |
case IBAT4U: |
|
| 2011 |
gen_op_load_ibat(0, 4); |
|
| 2012 |
break; |
|
| 2013 |
case IBAT5U: |
|
| 2014 |
gen_op_load_ibat(0, 5); |
|
| 2015 |
break; |
|
| 2016 |
case IBAT6U: |
|
| 2017 |
gen_op_load_ibat(0, 6); |
|
| 2018 |
break; |
|
| 2019 |
case IBAT7U: |
|
| 2020 |
gen_op_load_ibat(0, 7); |
|
| 2021 |
break; |
|
| 2022 |
case IBAT0L: |
|
| 2023 |
gen_op_load_ibat(1, 0); |
|
| 2024 |
break; |
|
| 2025 |
case IBAT1L: |
|
| 2026 |
gen_op_load_ibat(1, 1); |
|
| 2027 |
break; |
|
| 2028 |
case IBAT2L: |
|
| 2029 |
gen_op_load_ibat(1, 2); |
|
| 2030 |
break; |
|
| 2031 |
case IBAT3L: |
|
| 2032 |
gen_op_load_ibat(1, 3); |
|
| 2033 |
break; |
|
| 2034 |
case IBAT4L: |
|
| 2035 |
gen_op_load_ibat(1, 4); |
|
| 2036 |
break; |
|
| 2037 |
case IBAT5L: |
|
| 2038 |
gen_op_load_ibat(1, 5); |
|
| 2039 |
break; |
|
| 2040 |
case IBAT6L: |
|
| 2041 |
gen_op_load_ibat(1, 6); |
|
| 2042 |
break; |
|
| 2043 |
case IBAT7L: |
|
| 2044 |
gen_op_load_ibat(1, 7); |
|
| 2045 |
break; |
|
| 2046 |
case DBAT0U: |
|
| 2047 |
gen_op_load_dbat(0, 0); |
|
| 2048 |
break; |
|
| 2049 |
case DBAT1U: |
|
| 2050 |
gen_op_load_dbat(0, 1); |
|
| 2051 |
break; |
|
| 2052 |
case DBAT2U: |
|
| 2053 |
gen_op_load_dbat(0, 2); |
|
| 2054 |
break; |
|
| 2055 |
case DBAT3U: |
|
| 2056 |
gen_op_load_dbat(0, 3); |
|
| 2057 |
break; |
|
| 2058 |
case DBAT4U: |
|
| 2059 |
gen_op_load_dbat(0, 4); |
|
| 2060 |
break; |
|
| 2061 |
case DBAT5U: |
|
| 2062 |
gen_op_load_dbat(0, 5); |
|
| 2063 |
break; |
|
| 2064 |
case DBAT6U: |
|
| 2065 |
gen_op_load_dbat(0, 6); |
|
| 2066 |
break; |
|
| 2067 |
case DBAT7U: |
|
| 2068 |
gen_op_load_dbat(0, 7); |
|
| 2069 |
break; |
|
| 2070 |
case DBAT0L: |
|
| 2071 |
gen_op_load_dbat(1, 0); |
|
| 2072 |
break; |
|
| 2073 |
case DBAT1L: |
|
| 2074 |
gen_op_load_dbat(1, 1); |
|
| 2075 |
break; |
|
| 2076 |
case DBAT2L: |
|
| 2077 |
gen_op_load_dbat(1, 2); |
|
| 2078 |
break; |
|
| 2079 |
case DBAT3L: |
|
| 2080 |
gen_op_load_dbat(1, 3); |
|
| 2081 |
break; |
|
| 2082 |
case DBAT4L: |
|
| 2083 |
gen_op_load_dbat(1, 4); |
|
| 2084 |
break; |
|
| 2085 |
case DBAT5L: |
|
| 2086 |
gen_op_load_dbat(1, 5); |
|
| 2087 |
break; |
|
| 2088 |
case DBAT6L: |
|
| 2089 |
gen_op_load_dbat(1, 6); |
|
| 2090 |
break; |
|
| 2091 |
case DBAT7L: |
|
| 2092 |
gen_op_load_dbat(1, 7); |
|
| 2093 |
break; |
|
| 2094 |
case SDR1: |
|
| 2095 |
gen_op_load_sdr1(); |
|
| 2096 |
break; |
|
| 2097 |
case V_TBL: |
|
| 2098 |
gen_op_load_tbl(); |
|
| 2099 |
break; |
|
| 2100 |
case V_TBU: |
|
| 2101 |
gen_op_load_tbu(); |
|
| 2102 |
break; |
|
| 2103 |
case DECR: |
|
| 2104 |
gen_op_load_decr(); |
|
| 2105 |
break; |
|
| 2106 |
default: |
|
| 2107 |
gen_op_load_spr(sprn); |
|
| 2108 |
break; |
|
| 2020 |
} else {
|
|
| 2021 |
/* Not defined */ |
|
| 2022 |
printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
|
|
| 2023 |
RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
|
| 2109 | 2024 |
} |
| 2110 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
|
| 2111 | 2025 |
} |
| 2112 | 2026 |
|
| 2113 |
/* mftb */ |
|
| 2114 |
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC) |
|
| 2027 |
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC) |
|
| 2115 | 2028 |
{
|
| 2116 |
uint32_t sprn = SPR(ctx->opcode); |
|
| 2117 |
|
|
| 2118 |
/* We need to update the time base before reading it */ |
|
| 2119 |
switch (sprn) {
|
|
| 2120 |
case V_TBL: |
|
| 2121 |
gen_op_load_tbl(); |
|
| 2122 |
break; |
|
| 2123 |
case V_TBU: |
|
| 2124 |
gen_op_load_tbu(); |
|
| 2125 |
break; |
|
| 2126 |
default: |
|
| 2127 |
RET_INVAL(ctx); |
|
| 2128 |
return; |
|
| 2029 |
gen_op_mfspr(ctx); |
|
| 2129 | 2030 |
} |
| 2130 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
|
| 2031 |
|
|
| 2032 |
/* mftb */ |
|
| 2033 |
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_TB) |
|
| 2034 |
{
|
|
| 2035 |
gen_op_mfspr(ctx); |
|
| 2131 | 2036 |
} |
| 2132 | 2037 |
|
| 2133 | 2038 |
/* mtcrf */ |
| ... | ... | |
| 2158 | 2063 |
/* mtspr */ |
| 2159 | 2064 |
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
| 2160 | 2065 |
{
|
| 2066 |
void (*write_cb)(void *opaque, int sprn); |
|
| 2161 | 2067 |
uint32_t sprn = SPR(ctx->opcode); |
| 2162 | 2068 |
|
| 2163 |
#if 0 |
|
| 2164 |
if (loglevel > 0) {
|
|
| 2165 |
fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn), |
|
| 2166 |
rS(ctx->opcode), sprn); |
|
| 2167 |
} |
|
| 2168 |
#endif |
|
| 2169 |
#if defined(CONFIG_USER_ONLY) |
|
| 2170 |
switch (check_spr_access(sprn, 1, 0)) |
|
| 2171 |
#else |
|
| 2172 |
switch (check_spr_access(sprn, 1, ctx->supervisor)) |
|
| 2069 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2070 |
if (ctx->supervisor) |
|
| 2071 |
write_cb = ctx->spr_cb[sprn].oea_write; |
|
| 2072 |
else |
|
| 2173 | 2073 |
#endif |
| 2174 |
{
|
|
| 2175 |
case -1: |
|
| 2176 |
RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
|
| 2177 |
break; |
|
| 2178 |
case 0: |
|
| 2074 |
write_cb = ctx->spr_cb[sprn].uea_write; |
|
| 2075 |
if (write_cb != NULL) {
|
|
| 2076 |
if (write_cb != SPR_NOACCESS) {
|
|
| 2077 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
|
| 2078 |
(*write_cb)(ctx, sprn); |
|
| 2079 |
} else {
|
|
| 2080 |
/* Privilege exception */ |
|
| 2081 |
printf("Trying to write priviledged spr %d %03x\n", sprn, sprn);
|
|
| 2179 | 2082 |
RET_PRIVREG(ctx); |
| 2180 |
break; |
|
| 2181 |
default: |
|
| 2182 |
break; |
|
| 2183 | 2083 |
} |
| 2184 |
gen_op_load_gpr_T0(rS(ctx->opcode)); |
|
| 2185 |
switch (sprn) {
|
|
| 2186 |
case XER: |
|
| 2187 |
gen_op_store_xer(); |
|
| 2188 |
break; |
|
| 2189 |
case LR: |
|
| 2190 |
gen_op_store_lr(); |
|
| 2191 |
break; |
|
| 2192 |
case CTR: |
|
| 2193 |
gen_op_store_ctr(); |
|
| 2194 |
break; |
|
| 2195 |
case IBAT0U: |
|
| 2196 |
gen_op_store_ibat(0, 0); |
|
| 2197 |
RET_MTMSR(ctx); |
|
| 2198 |
break; |
|
| 2199 |
case IBAT1U: |
|
| 2200 |
gen_op_store_ibat(0, 1); |
|
| 2201 |
RET_MTMSR(ctx); |
|
| 2202 |
break; |
|
| 2203 |
case IBAT2U: |
|
| 2204 |
gen_op_store_ibat(0, 2); |
|
| 2205 |
RET_MTMSR(ctx); |
|
| 2206 |
break; |
|
| 2207 |
case IBAT3U: |
|
| 2208 |
gen_op_store_ibat(0, 3); |
|
| 2209 |
RET_MTMSR(ctx); |
|
| 2210 |
break; |
|
| 2211 |
case IBAT4U: |
|
| 2212 |
gen_op_store_ibat(0, 4); |
|
| 2213 |
RET_MTMSR(ctx); |
|
| 2214 |
break; |
|
| 2215 |
case IBAT5U: |
|
| 2216 |
gen_op_store_ibat(0, 5); |
|
| 2217 |
RET_MTMSR(ctx); |
|
| 2218 |
break; |
|
| 2219 |
case IBAT6U: |
|
| 2220 |
gen_op_store_ibat(0, 6); |
|
| 2221 |
RET_MTMSR(ctx); |
|
| 2222 |
break; |
|
| 2223 |
case IBAT7U: |
|
| 2224 |
gen_op_store_ibat(0, 7); |
|
| 2225 |
RET_MTMSR(ctx); |
|
| 2226 |
break; |
|
| 2227 |
case IBAT0L: |
|
| 2228 |
gen_op_store_ibat(1, 0); |
|
| 2229 |
RET_MTMSR(ctx); |
|
| 2230 |
break; |
|
| 2231 |
case IBAT1L: |
|
| 2232 |
gen_op_store_ibat(1, 1); |
|
| 2233 |
RET_MTMSR(ctx); |
|
| 2234 |
break; |
|
| 2235 |
case IBAT2L: |
|
| 2236 |
gen_op_store_ibat(1, 2); |
|
| 2237 |
RET_MTMSR(ctx); |
|
| 2238 |
break; |
|
| 2239 |
case IBAT3L: |
|
| 2240 |
gen_op_store_ibat(1, 3); |
|
| 2241 |
RET_MTMSR(ctx); |
|
| 2242 |
break; |
|
| 2243 |
case IBAT4L: |
|
| 2244 |
gen_op_store_ibat(1, 4); |
|
| 2245 |
RET_MTMSR(ctx); |
|
| 2246 |
break; |
|
| 2247 |
case IBAT5L: |
|
| 2248 |
gen_op_store_ibat(1, 5); |
|
| 2249 |
RET_MTMSR(ctx); |
|
| 2250 |
break; |
|
| 2251 |
case IBAT6L: |
|
| 2252 |
gen_op_store_ibat(1, 6); |
|
| 2253 |
RET_MTMSR(ctx); |
|
| 2254 |
break; |
|
| 2255 |
case IBAT7L: |
|
| 2256 |
gen_op_store_ibat(1, 7); |
|
| 2257 |
RET_MTMSR(ctx); |
|
| 2258 |
break; |
|
| 2259 |
case DBAT0U: |
|
| 2260 |
gen_op_store_dbat(0, 0); |
|
| 2261 |
RET_MTMSR(ctx); |
|
| 2262 |
break; |
|
| 2263 |
case DBAT1U: |
|
| 2264 |
gen_op_store_dbat(0, 1); |
|
| 2265 |
RET_MTMSR(ctx); |
|
| 2266 |
break; |
|
| 2267 |
case DBAT2U: |
|
| 2268 |
gen_op_store_dbat(0, 2); |
|
| 2269 |
RET_MTMSR(ctx); |
|
| 2270 |
break; |
|
| 2271 |
case DBAT3U: |
|
| 2272 |
gen_op_store_dbat(0, 3); |
|
| 2273 |
RET_MTMSR(ctx); |
|
| 2274 |
break; |
|
| 2275 |
case DBAT4U: |
|
| 2276 |
gen_op_store_dbat(0, 4); |
|
| 2277 |
RET_MTMSR(ctx); |
|
| 2278 |
break; |
|
| 2279 |
case DBAT5U: |
|
| 2280 |
gen_op_store_dbat(0, 5); |
|
| 2281 |
RET_MTMSR(ctx); |
|
| 2282 |
break; |
|
| 2283 |
case DBAT6U: |
|
| 2284 |
gen_op_store_dbat(0, 6); |
|
| 2285 |
RET_MTMSR(ctx); |
|
| 2286 |
break; |
|
| 2287 |
case DBAT7U: |
|
| 2288 |
gen_op_store_dbat(0, 7); |
|
| 2289 |
RET_MTMSR(ctx); |
|
| 2290 |
break; |
|
| 2291 |
case DBAT0L: |
|
| 2292 |
gen_op_store_dbat(1, 0); |
|
| 2293 |
RET_MTMSR(ctx); |
|
| 2294 |
break; |
|
| 2295 |
case DBAT1L: |
|
| 2296 |
gen_op_store_dbat(1, 1); |
|
| 2297 |
RET_MTMSR(ctx); |
|
| 2298 |
break; |
|
| 2299 |
case DBAT2L: |
|
| 2300 |
gen_op_store_dbat(1, 2); |
|
| 2301 |
RET_MTMSR(ctx); |
|
| 2302 |
break; |
|
| 2303 |
case DBAT3L: |
|
| 2304 |
gen_op_store_dbat(1, 3); |
|
| 2305 |
RET_MTMSR(ctx); |
|
| 2306 |
break; |
|
| 2307 |
case DBAT4L: |
|
| 2308 |
gen_op_store_dbat(1, 4); |
|
| 2309 |
RET_MTMSR(ctx); |
|
| 2310 |
break; |
|
| 2311 |
case DBAT5L: |
|
| 2312 |
gen_op_store_dbat(1, 5); |
|
| 2313 |
RET_MTMSR(ctx); |
|
| 2314 |
break; |
|
| 2315 |
case DBAT6L: |
|
| 2316 |
gen_op_store_dbat(1, 6); |
|
| 2317 |
RET_MTMSR(ctx); |
|
| 2318 |
break; |
|
| 2319 |
case DBAT7L: |
|
| 2320 |
gen_op_store_dbat(1, 7); |
|
| 2321 |
RET_MTMSR(ctx); |
|
| 2322 |
break; |
|
| 2323 |
case SDR1: |
|
| 2324 |
gen_op_store_sdr1(); |
|
| 2325 |
RET_MTMSR(ctx); |
|
| 2326 |
break; |
|
| 2327 |
case O_TBL: |
|
| 2328 |
gen_op_store_tbl(); |
|
| 2329 |
break; |
|
| 2330 |
case O_TBU: |
|
| 2331 |
gen_op_store_tbu(); |
|
| 2332 |
break; |
|
| 2333 |
case DECR: |
|
| 2334 |
gen_op_store_decr(); |
|
| 2335 |
break; |
|
| 2336 |
default: |
|
| 2337 |
gen_op_store_spr(sprn); |
|
| 2338 |
break; |
|
| 2084 |
} else {
|
|
| 2085 |
/* Not defined */ |
|
| 2086 |
printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
|
|
| 2087 |
RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
|
| 2339 | 2088 |
} |
| 2340 | 2089 |
} |
| 2341 | 2090 |
|
| ... | ... | |
| 2514 | 2263 |
/*** Lookaside buffer management ***/ |
| 2515 | 2264 |
/* Optional & supervisor only: */ |
| 2516 | 2265 |
/* tlbia */ |
| 2517 |
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
|
|
| 2266 |
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
|
|
| 2518 | 2267 |
{
|
| 2519 | 2268 |
#if defined(CONFIG_USER_ONLY) |
| 2520 | 2269 |
RET_PRIVOPC(ctx); |
| ... | ... | |
| 2624 | 2373 |
/* End opcode list */ |
| 2625 | 2374 |
GEN_OPCODE_MARK(end); |
| 2626 | 2375 |
|
| 2627 |
/*****************************************************************************/ |
|
| 2628 |
#include <stdlib.h> |
|
| 2629 |
#include <string.h> |
|
| 2630 |
|
|
| 2631 |
int fflush (FILE *stream); |
|
| 2632 |
|
|
| 2633 |
/* Main ppc opcodes table: |
|
| 2634 |
* at init, all opcodes are invalids |
|
| 2635 |
*/ |
|
| 2636 |
static opc_handler_t *ppc_opcodes[0x40]; |
|
| 2637 |
|
|
| 2638 |
/* Opcode types */ |
|
| 2639 |
enum {
|
|
| 2640 |
PPC_DIRECT = 0, /* Opcode routine */ |
|
| 2641 |
PPC_INDIRECT = 1, /* Indirect opcode table */ |
|
| 2642 |
}; |
|
| 2643 |
|
|
| 2644 |
static inline int is_indirect_opcode (void *handler) |
|
| 2645 |
{
|
|
| 2646 |
return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
|
| 2647 |
} |
|
| 2648 |
|
|
| 2649 |
static inline opc_handler_t **ind_table(void *handler) |
|
| 2650 |
{
|
|
| 2651 |
return (opc_handler_t **)((unsigned long)handler & ~3); |
|
| 2652 |
} |
|
| 2653 |
|
|
| 2654 |
/* Instruction table creation */ |
|
| 2655 |
/* Opcodes tables creation */ |
|
| 2656 |
static void fill_new_table (opc_handler_t **table, int len) |
|
| 2657 |
{
|
|
| 2658 |
int i; |
|
| 2659 |
|
|
| 2660 |
for (i = 0; i < len; i++) |
|
| 2661 |
table[i] = &invalid_handler; |
|
| 2662 |
} |
|
| 2663 |
|
|
| 2664 |
static int create_new_table (opc_handler_t **table, unsigned char idx) |
|
| 2665 |
{
|
|
| 2666 |
opc_handler_t **tmp; |
|
| 2667 |
|
|
| 2668 |
tmp = malloc(0x20 * sizeof(opc_handler_t)); |
|
| 2669 |
if (tmp == NULL) |
|
| 2670 |
return -1; |
|
| 2671 |
fill_new_table(tmp, 0x20); |
|
| 2672 |
table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
|
| 2673 |
|
|
| 2674 |
return 0; |
|
| 2675 |
} |
|
| 2676 |
|
|
| 2677 |
static int insert_in_table (opc_handler_t **table, unsigned char idx, |
|
| 2678 |
opc_handler_t *handler) |
|
| 2679 |
{
|
|
| 2680 |
if (table[idx] != &invalid_handler) |
|
| 2681 |
return -1; |
|
| 2682 |
table[idx] = handler; |
|
| 2683 |
|
|
| 2684 |
return 0; |
|
| 2685 |
} |
|
| 2686 |
|
|
| 2687 |
static int register_direct_insn (opc_handler_t **ppc_opcodes, |
|
| 2688 |
unsigned char idx, opc_handler_t *handler) |
|
| 2689 |
{
|
|
| 2690 |
if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
|
|
| 2691 |
printf("*** ERROR: opcode %02x already assigned in main "
|
|
| 2692 |
"opcode table\n", idx); |
|
| 2693 |
return -1; |
|
| 2694 |
} |
|
| 2695 |
|
|
| 2696 |
return 0; |
|
| 2697 |
} |
|
| 2698 |
|
|
| 2699 |
static int register_ind_in_table (opc_handler_t **table, |
|
| 2700 |
unsigned char idx1, unsigned char idx2, |
|
| 2701 |
opc_handler_t *handler) |
|
| 2702 |
{
|
|
| 2703 |
if (table[idx1] == &invalid_handler) {
|
|
| 2704 |
if (create_new_table(table, idx1) < 0) {
|
|
| 2705 |
printf("*** ERROR: unable to create indirect table "
|
|
| 2706 |
"idx=%02x\n", idx1); |
|
| 2707 |
return -1; |
|
| 2708 |
} |
|
| 2709 |
} else {
|
|
| 2710 |
if (!is_indirect_opcode(table[idx1])) {
|
|
| 2711 |
printf("*** ERROR: idx %02x already assigned to a direct "
|
|
| 2712 |
"opcode\n", idx1); |
|
| 2713 |
return -1; |
|
| 2714 |
} |
|
| 2715 |
} |
|
| 2716 |
if (handler != NULL && |
|
| 2717 |
insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
|
| 2718 |
printf("*** ERROR: opcode %02x already assigned in "
|
|
| 2719 |
"opcode table %02x\n", idx2, idx1); |
|
| 2720 |
return -1; |
|
| 2721 |
} |
|
| 2722 |
|
|
| 2723 |
return 0; |
|
| 2724 |
} |
|
| 2725 |
|
|
| 2726 |
static int register_ind_insn (opc_handler_t **ppc_opcodes, |
|
| 2727 |
unsigned char idx1, unsigned char idx2, |
|
| 2728 |
opc_handler_t *handler) |
|
| 2729 |
{
|
|
| 2730 |
int ret; |
|
| 2731 |
|
|
| 2732 |
ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
|
| 2733 |
|
|
| 2734 |
return ret; |
|
| 2735 |
} |
|
| 2736 |
|
|
| 2737 |
static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
|
| 2738 |
unsigned char idx1, unsigned char idx2, |
|
| 2739 |
unsigned char idx3, opc_handler_t *handler) |
|
| 2740 |
{
|
|
| 2741 |
if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
|
|
| 2742 |
printf("*** ERROR: unable to join indirect table idx "
|
|
| 2743 |
"[%02x-%02x]\n", idx1, idx2); |
|
| 2744 |
return -1; |
|
| 2745 |
} |
|
| 2746 |
if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, |
|
| 2747 |
handler) < 0) {
|
|
| 2748 |
printf("*** ERROR: unable to insert opcode "
|
|
| 2749 |
"[%02x-%02x-%02x]\n", idx1, idx2, idx3); |
|
| 2750 |
return -1; |
|
| 2751 |
} |
|
| 2752 |
|
|
| 2753 |
return 0; |
|
| 2754 |
} |
|
| 2755 |
|
|
| 2756 |
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
|
| 2757 |
{
|
|
| 2758 |
if (insn->opc2 != 0xFF) {
|
|
| 2759 |
if (insn->opc3 != 0xFF) {
|
|
| 2760 |
if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, |
|
| 2761 |
insn->opc3, &insn->handler) < 0) |
|
| 2762 |
return -1; |
|
| 2763 |
} else {
|
|
| 2764 |
if (register_ind_insn(ppc_opcodes, insn->opc1, |
|
| 2765 |
insn->opc2, &insn->handler) < 0) |
|
| 2766 |
return -1; |
|
| 2767 |
} |
|
| 2768 |
} else {
|
|
| 2769 |
if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
|
| 2770 |
return -1; |
|
| 2771 |
} |
|
| 2772 |
|
|
| 2773 |
return 0; |
|
| 2774 |
} |
|
| 2775 |
|
|
| 2776 |
static int test_opcode_table (opc_handler_t **table, int len) |
|
| 2777 |
{
|
|
| 2778 |
int i, count, tmp; |
|
| 2779 |
|
|
| 2780 |
for (i = 0, count = 0; i < len; i++) {
|
|
| 2781 |
/* Consistency fixup */ |
|
| 2782 |
if (table[i] == NULL) |
|
| 2783 |
table[i] = &invalid_handler; |
|
| 2784 |
if (table[i] != &invalid_handler) {
|
|
| 2785 |
if (is_indirect_opcode(table[i])) {
|
|
| 2786 |
tmp = test_opcode_table(ind_table(table[i]), 0x20); |
|
| 2787 |
if (tmp == 0) {
|
|
| 2788 |
free(table[i]); |
|
| 2789 |
table[i] = &invalid_handler; |
|
| 2790 |
} else {
|
|
| 2791 |
count++; |
|
| 2792 |
} |
|
| 2793 |
} else {
|
|
| 2794 |
count++; |
|
| 2795 |
} |
|
| 2796 |
} |
|
| 2797 |
} |
|
| 2798 |
|
|
| 2799 |
return count; |
|
| 2800 |
} |
|
| 2801 |
|
|
| 2802 |
static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
|
| 2803 |
{
|
|
| 2804 |
if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
|
| 2805 |
printf("*** WARNING: no opcode defined !\n");
|
|
| 2806 |
} |
|
| 2807 |
|
|
| 2808 |
#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw))) |
|
| 2809 |
#define SPR_UR SPR_RIGHTS(0, 0) |
|
| 2810 |
#define SPR_UW SPR_RIGHTS(1, 0) |
|
| 2811 |
#define SPR_SR SPR_RIGHTS(0, 1) |
|
| 2812 |
#define SPR_SW SPR_RIGHTS(1, 1) |
|
| 2813 |
|
|
| 2814 |
#define spr_set_rights(spr, rights) \ |
|
| 2815 |
do { \
|
|
| 2816 |
spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \ |
|
| 2817 |
} while (0) |
|
| 2818 |
|
|
| 2819 |
static void init_spr_rights (uint32_t pvr) |
|
| 2820 |
{
|
|
| 2821 |
/* XER (SPR 1) */ |
|
| 2822 |
spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
|
| 2823 |
/* LR (SPR 8) */ |
|
| 2824 |
spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
|
| 2825 |
/* CTR (SPR 9) */ |
|
| 2826 |
spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
|
| 2827 |
/* TBL (SPR 268) */ |
|
| 2828 |
spr_set_rights(V_TBL, SPR_UR | SPR_SR); |
|
| 2829 |
/* TBU (SPR 269) */ |
|
| 2830 |
spr_set_rights(V_TBU, SPR_UR | SPR_SR); |
|
| 2831 |
/* DSISR (SPR 18) */ |
|
| 2832 |
spr_set_rights(DSISR, SPR_SR | SPR_SW); |
|
| 2833 |
/* DAR (SPR 19) */ |
|
| 2834 |
spr_set_rights(DAR, SPR_SR | SPR_SW); |
|
| 2835 |
/* DEC (SPR 22) */ |
|
| 2836 |
spr_set_rights(DECR, SPR_SR | SPR_SW); |
|
| 2837 |
/* SDR1 (SPR 25) */ |
|
| 2838 |
spr_set_rights(SDR1, SPR_SR | SPR_SW); |
|
| 2839 |
/* SRR0 (SPR 26) */ |
|
| 2840 |
spr_set_rights(SRR0, SPR_SR | SPR_SW); |
|
| 2841 |
/* SRR1 (SPR 27) */ |
|
| 2842 |
spr_set_rights(SRR1, SPR_SR | SPR_SW); |
|
| 2843 |
/* SPRG0 (SPR 272) */ |
|
| 2844 |
spr_set_rights(SPRG0, SPR_SR | SPR_SW); |
|
| 2845 |
/* SPRG1 (SPR 273) */ |
|
| 2846 |
spr_set_rights(SPRG1, SPR_SR | SPR_SW); |
|
| 2847 |
/* SPRG2 (SPR 274) */ |
|
| 2848 |
spr_set_rights(SPRG2, SPR_SR | SPR_SW); |
|
| 2849 |
/* SPRG3 (SPR 275) */ |
|
| 2850 |
spr_set_rights(SPRG3, SPR_SR | SPR_SW); |
|
| 2851 |
/* ASR (SPR 280) */ |
|
| 2852 |
spr_set_rights(ASR, SPR_SR | SPR_SW); |
|
| 2853 |
/* EAR (SPR 282) */ |
|
| 2854 |
spr_set_rights(EAR, SPR_SR | SPR_SW); |
|
| 2855 |
/* TBL (SPR 284) */ |
|
| 2856 |
spr_set_rights(O_TBL, SPR_SW); |
|
| 2857 |
/* TBU (SPR 285) */ |
|
| 2858 |
spr_set_rights(O_TBU, SPR_SW); |
|
| 2859 |
/* PVR (SPR 287) */ |
|
| 2860 |
spr_set_rights(PVR, SPR_SR); |
|
| 2861 |
/* IBAT0U (SPR 528) */ |
|
| 2862 |
spr_set_rights(IBAT0U, SPR_SR | SPR_SW); |
|
| 2863 |
/* IBAT0L (SPR 529) */ |
|
| 2864 |
spr_set_rights(IBAT0L, SPR_SR | SPR_SW); |
|
| 2865 |
/* IBAT1U (SPR 530) */ |
|
| 2866 |
spr_set_rights(IBAT1U, SPR_SR | SPR_SW); |
|
| 2867 |
/* IBAT1L (SPR 531) */ |
|
| 2868 |
spr_set_rights(IBAT1L, SPR_SR | SPR_SW); |
|
| 2869 |
/* IBAT2U (SPR 532) */ |
|
| 2870 |
spr_set_rights(IBAT2U, SPR_SR | SPR_SW); |
|
| 2871 |
/* IBAT2L (SPR 533) */ |
|
| 2872 |
spr_set_rights(IBAT2L, SPR_SR | SPR_SW); |
|
| 2873 |
/* IBAT3U (SPR 534) */ |
|
| 2874 |
spr_set_rights(IBAT3U, SPR_SR | SPR_SW); |
|
| 2875 |
/* IBAT3L (SPR 535) */ |
|
| 2876 |
spr_set_rights(IBAT3L, SPR_SR | SPR_SW); |
|
| 2877 |
/* DBAT0U (SPR 536) */ |
|
| 2878 |
spr_set_rights(DBAT0U, SPR_SR | SPR_SW); |
|
| 2879 |
/* DBAT0L (SPR 537) */ |
|
| 2880 |
spr_set_rights(DBAT0L, SPR_SR | SPR_SW); |
|
| 2881 |
/* DBAT1U (SPR 538) */ |
|
| 2882 |
spr_set_rights(DBAT1U, SPR_SR | SPR_SW); |
|
| 2883 |
/* DBAT1L (SPR 539) */ |
|
| 2884 |
spr_set_rights(DBAT1L, SPR_SR | SPR_SW); |
|
| 2885 |
/* DBAT2U (SPR 540) */ |
|
| 2886 |
spr_set_rights(DBAT2U, SPR_SR | SPR_SW); |
|
| 2887 |
/* DBAT2L (SPR 541) */ |
|
| 2888 |
spr_set_rights(DBAT2L, SPR_SR | SPR_SW); |
|
| 2889 |
/* DBAT3U (SPR 542) */ |
|
| 2890 |
spr_set_rights(DBAT3U, SPR_SR | SPR_SW); |
|
| 2891 |
/* DBAT3L (SPR 543) */ |
|
| 2892 |
spr_set_rights(DBAT3L, SPR_SR | SPR_SW); |
|
| 2893 |
/* FPECR (SPR 1022) */ |
|
| 2894 |
spr_set_rights(FPECR, SPR_SR | SPR_SW); |
|
| 2895 |
/* Special registers for PPC 604 */ |
|
| 2896 |
if ((pvr & 0xFFFF0000) == 0x00040000) {
|
|
| 2897 |
/* IABR */ |
|
| 2898 |
spr_set_rights(IABR , SPR_SR | SPR_SW); |
|
| 2899 |
/* DABR (SPR 1013) */ |
|
| 2900 |
spr_set_rights(DABR, SPR_SR | SPR_SW); |
|
| 2901 |
/* HID0 */ |
|
| 2902 |
spr_set_rights(HID0, SPR_SR | SPR_SW); |
|
| 2903 |
/* PIR */ |
|
| 2904 |
spr_set_rights(PIR, SPR_SR | SPR_SW); |
|
| 2905 |
/* PMC1 */ |
|
| 2906 |
spr_set_rights(PMC1, SPR_SR | SPR_SW); |
|
| 2907 |
/* PMC2 */ |
|
| 2908 |
spr_set_rights(PMC2, SPR_SR | SPR_SW); |
|
| 2909 |
/* MMCR0 */ |
|
| 2910 |
spr_set_rights(MMCR0, SPR_SR | SPR_SW); |
|
| 2911 |
/* SIA */ |
|
| 2912 |
spr_set_rights(SIA, SPR_SR | SPR_SW); |
|
| 2913 |
/* SDA */ |
|
| 2914 |
spr_set_rights(SDA, SPR_SR | SPR_SW); |
|
| 2915 |
} |
|
| 2916 |
/* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */ |
|
| 2917 |
if ((pvr & 0xFFFF0000) == 0x00080000 || |
|
| 2918 |
(pvr & 0xFFFF0000) == 0x70000000) {
|
|
| 2919 |
/* HID0 */ |
|
| 2920 |
spr_set_rights(HID0, SPR_SR | SPR_SW); |
|
| 2921 |
/* HID1 */ |
|
| 2922 |
spr_set_rights(HID1, SPR_SR | SPR_SW); |
|
| 2923 |
/* IABR */ |
|
| 2924 |
spr_set_rights(IABR, SPR_SR | SPR_SW); |
|
| 2925 |
/* ICTC */ |
|
| 2926 |
spr_set_rights(ICTC, SPR_SR | SPR_SW); |
|
| 2927 |
/* L2CR */ |
|
| 2928 |
spr_set_rights(L2CR, SPR_SR | SPR_SW); |
|
| 2929 |
/* MMCR0 */ |
|
| 2930 |
spr_set_rights(MMCR0, SPR_SR | SPR_SW); |
|
| 2931 |
/* MMCR1 */ |
|
| 2932 |
spr_set_rights(MMCR1, SPR_SR | SPR_SW); |
|
| 2933 |
/* PMC1 */ |
|
| 2934 |
spr_set_rights(PMC1, SPR_SR | SPR_SW); |
|
| 2935 |
/* PMC2 */ |
|
| 2936 |
spr_set_rights(PMC2, SPR_SR | SPR_SW); |
|
| 2937 |
/* PMC3 */ |
|
| 2938 |
spr_set_rights(PMC3, SPR_SR | SPR_SW); |
|
| 2939 |
/* PMC4 */ |
|
| 2940 |
spr_set_rights(PMC4, SPR_SR | SPR_SW); |
|
| 2941 |
/* SIA */ |
|
| 2942 |
spr_set_rights(SIA, SPR_SR | SPR_SW); |
|
| 2943 |
/* SDA */ |
|
| 2944 |
spr_set_rights(SDA, SPR_SR | SPR_SW); |
|
| 2945 |
/* THRM1 */ |
|
| 2946 |
spr_set_rights(THRM1, SPR_SR | SPR_SW); |
|
| 2947 |
/* THRM2 */ |
|
| 2948 |
spr_set_rights(THRM2, SPR_SR | SPR_SW); |
|
| 2949 |
/* THRM3 */ |
|
| 2950 |
spr_set_rights(THRM3, SPR_SR | SPR_SW); |
|
| 2951 |
/* UMMCR0 */ |
|
| 2952 |
spr_set_rights(UMMCR0, SPR_UR | SPR_UW); |
|
| 2953 |
/* UMMCR1 */ |
|
| 2954 |
spr_set_rights(UMMCR1, SPR_UR | SPR_UW); |
|
| 2955 |
/* UPMC1 */ |
|
| 2956 |
spr_set_rights(UPMC1, SPR_UR | SPR_UW); |
|
| 2957 |
/* UPMC2 */ |
|
| 2958 |
spr_set_rights(UPMC2, SPR_UR | SPR_UW); |
|
| 2959 |
/* UPMC3 */ |
|
| 2960 |
spr_set_rights(UPMC3, SPR_UR | SPR_UW); |
|
| 2961 |
/* UPMC4 */ |
|
| 2962 |
spr_set_rights(UPMC4, SPR_UR | SPR_UW); |
|
| 2963 |
/* USIA */ |
|
| 2964 |
spr_set_rights(USIA, SPR_UR | SPR_UW); |
|
| 2965 |
} |
|
| 2966 |
/* MPC755 has special registers */ |
|
| 2967 |
if (pvr == 0x00083100) {
|
|
| 2968 |
/* SPRG4 */ |
|
| 2969 |
spr_set_rights(SPRG4, SPR_SR | SPR_SW); |
|
| 2970 |
/* SPRG5 */ |
|
| 2971 |
spr_set_rights(SPRG5, SPR_SR | SPR_SW); |
|
| 2972 |
/* SPRG6 */ |
|
| 2973 |
spr_set_rights(SPRG6, SPR_SR | SPR_SW); |
|
| 2974 |
/* SPRG7 */ |
|
| 2975 |
spr_set_rights(SPRG7, SPR_SR | SPR_SW); |
|
| 2976 |
/* IBAT4U */ |
|
| 2977 |
spr_set_rights(IBAT4U, SPR_SR | SPR_SW); |
|
| 2978 |
/* IBAT4L */ |
|
| 2979 |
spr_set_rights(IBAT4L, SPR_SR | SPR_SW); |
|
| 2980 |
/* IBAT5U */ |
|
| 2981 |
spr_set_rights(IBAT5U, SPR_SR | SPR_SW); |
|
| 2982 |
/* IBAT5L */ |
|
| 2983 |
spr_set_rights(IBAT5L, SPR_SR | SPR_SW); |
|
| 2984 |
/* IBAT6U */ |
|
| 2985 |
spr_set_rights(IBAT6U, SPR_SR | SPR_SW); |
|
| 2986 |
/* IBAT6L */ |
|
| 2987 |
spr_set_rights(IBAT6L, SPR_SR | SPR_SW); |
|
| 2988 |
/* IBAT7U */ |
|
| 2989 |
spr_set_rights(IBAT7U, SPR_SR | SPR_SW); |
|
| 2990 |
/* IBAT7L */ |
|
| 2991 |
spr_set_rights(IBAT7L, SPR_SR | SPR_SW); |
|
| 2992 |
/* DBAT4U */ |
|
| 2993 |
spr_set_rights(DBAT4U, SPR_SR | SPR_SW); |
|
| 2994 |
/* DBAT4L */ |
|
| 2995 |
spr_set_rights(DBAT4L, SPR_SR | SPR_SW); |
|
| 2996 |
/* DBAT5U */ |
|
| 2997 |
spr_set_rights(DBAT5U, SPR_SR | SPR_SW); |
|
| 2998 |
/* DBAT5L */ |
|
| 2999 |
spr_set_rights(DBAT5L, SPR_SR | SPR_SW); |
|
| 3000 |
/* DBAT6U */ |
|
| 3001 |
spr_set_rights(DBAT6U, SPR_SR | SPR_SW); |
|
| 3002 |
/* DBAT6L */ |
|
| 3003 |
spr_set_rights(DBAT6L, SPR_SR | SPR_SW); |
|
| 3004 |
/* DBAT7U */ |
|
| 3005 |
spr_set_rights(DBAT7U, SPR_SR | SPR_SW); |
|
| 3006 |
/* DBAT7L */ |
|
| 3007 |
spr_set_rights(DBAT7L, SPR_SR | SPR_SW); |
|
| 3008 |
/* DMISS */ |
|
| 3009 |
spr_set_rights(DMISS, SPR_SR | SPR_SW); |
|
| 3010 |
/* DCMP */ |
|
| 3011 |
spr_set_rights(DCMP, SPR_SR | SPR_SW); |
|
| 3012 |
/* DHASH1 */ |
|
| 3013 |
spr_set_rights(DHASH1, SPR_SR | SPR_SW); |
|
| 3014 |
/* DHASH2 */ |
|
| 3015 |
spr_set_rights(DHASH2, SPR_SR | SPR_SW); |
|
| 3016 |
/* IMISS */ |
|
| 3017 |
spr_set_rights(IMISS, SPR_SR | SPR_SW); |
|
| 3018 |
/* ICMP */ |
|
| 3019 |
spr_set_rights(ICMP, SPR_SR | SPR_SW); |
|
| 3020 |
/* RPA */ |
|
| 3021 |
spr_set_rights(RPA, SPR_SR | SPR_SW); |
|
| 3022 |
/* HID2 */ |
|
| 3023 |
spr_set_rights(HID2, SPR_SR | SPR_SW); |
|
| 3024 |
/* L2PM */ |
|
| 3025 |
spr_set_rights(L2PM, SPR_SR | SPR_SW); |
|
| 3026 |
} |
|
| 3027 |
} |
|
| 3028 |
|
|
| 3029 |
/*****************************************************************************/ |
|
| 3030 |
/* PPC "main stream" common instructions (no optional ones) */ |
|
| 3031 |
|
|
| 3032 |
typedef struct ppc_proc_t {
|
|
| 3033 |
int flags; |
|
| 3034 |
void *specific; |
|
| 3035 |
} ppc_proc_t; |
|
| 3036 |
|
|
| 3037 |
typedef struct ppc_def_t {
|
|
| 3038 |
unsigned long pvr; |
|
| 3039 |
unsigned long pvr_mask; |
|
| 3040 |
ppc_proc_t *proc; |
|
| 3041 |
} ppc_def_t; |
|
| 3042 |
|
|
| 3043 |
static ppc_proc_t ppc_proc_common = {
|
|
| 3044 |
.flags = PPC_COMMON, |
|
| 3045 |
.specific = NULL, |
|
| 3046 |
}; |
|
| 3047 |
|
|
| 3048 |
static ppc_proc_t ppc_proc_G3 = {
|
|
| 3049 |
.flags = PPC_750, |
|
| 3050 |
.specific = NULL, |
|
| 3051 |
}; |
|
| 3052 |
|
|
| 3053 |
static ppc_def_t ppc_defs[] = |
|
| 3054 |
{
|
|
| 3055 |
/* MPC740/745/750/755 (G3) */ |
|
| 3056 |
{
|
|
| 3057 |
.pvr = 0x00080000, |
|
| 3058 |
.pvr_mask = 0xFFFF0000, |
|
| 3059 |
.proc = &ppc_proc_G3, |
|
| 3060 |
}, |
|
| 3061 |
/* IBM 750FX (G3 embedded) */ |
|
| 3062 |
{
|
|
| 3063 |
.pvr = 0x70000000, |
|
| 3064 |
.pvr_mask = 0xFFFF0000, |
|
| 3065 |
.proc = &ppc_proc_G3, |
|
| 3066 |
}, |
|
| 3067 |
/* Fallback (generic PPC) */ |
|
| 3068 |
{
|
|
| 3069 |
.pvr = 0x00000000, |
|
| 3070 |
.pvr_mask = 0x00000000, |
|
| 3071 |
.proc = &ppc_proc_common, |
|
| 3072 |
}, |
|
| 3073 |
}; |
|
| 3074 |
|
|
| 3075 |
static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr) |
|
| 3076 |
{
|
|
| 3077 |
opcode_t *opc, *start, *end; |
|
| 3078 |
int i, flags; |
|
| 3079 |
|
|
| 3080 |
fill_new_table(ppc_opcodes, 0x40); |
|
| 3081 |
for (i = 0; ; i++) {
|
|
| 3082 |
if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) == |
|
| 3083 |
(pvr & ppc_defs[i].pvr_mask)) {
|
|
| 3084 |
flags = ppc_defs[i].proc->flags; |
|
| 3085 |
break; |
|
| 3086 |
} |
|
| 3087 |
} |
|
| 3088 |
|
|
| 3089 |
if (&opc_start < &opc_end) {
|
|
| 3090 |
start = &opc_start; |
|
| 3091 |
end = &opc_end; |
|
| 3092 |
} else {
|
|
| 3093 |
start = &opc_end; |
|
| 3094 |
end = &opc_start; |
|
| 3095 |
} |
|
| 3096 |
for (opc = start + 1; opc != end; opc++) {
|
|
| 3097 |
if ((opc->handler.type & flags) != 0) |
|
| 3098 |
if (register_insn(ppc_opcodes, opc) < 0) {
|
|
| 3099 |
printf("*** ERROR initializing PPC instruction "
|
|
| 3100 |
"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2, |
|
| 3101 |
opc->opc3); |
|
| 3102 |
return -1; |
|
| 3103 |
} |
|
| 3104 |
} |
|
| 3105 |
fix_opcode_tables(ppc_opcodes); |
|
| 3106 |
|
|
| 3107 |
return 0; |
|
| 3108 |
} |
|
| 3109 |
|
|
| 2376 |
#include "translate_init.c" |
|
| 3110 | 2377 |
|
| 3111 | 2378 |
/*****************************************************************************/ |
| 3112 |
/* Misc PPC helpers */ |
|
| 3113 |
|
|
| 2379 |
/* Misc PowerPC helpers */ |
|
| 3114 | 2380 |
void cpu_dump_state(CPUState *env, FILE *f, |
| 3115 | 2381 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 3116 | 2382 |
int flags) |
| 3117 | 2383 |
{
|
| 2384 |
#if defined(TARGET_PPC64) || 1 |
|
| 2385 |
#define FILL "" |
|
| 2386 |
#define REGX "%016llx" |
|
| 2387 |
#define RGPL 4 |
|
| 2388 |
#define RFPL 4 |
|
| 2389 |
#else |
|
| 2390 |
#define FILL " " |
|
| 2391 |
#define REGX "%08llx" |
|
| 2392 |
#define RGPL 8 |
|
| 2393 |
#define RFPL 4 |
|
| 2394 |
#endif |
|
| 2395 |
|
|
| 3118 | 2396 |
int i; |
| 3119 | 2397 |
|
| 3120 |
cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x " |
|
| 3121 |
"MSR=0x%08x\n", env->nip, env->lr, env->ctr, |
|
| 3122 |
_load_xer(env), _load_msr(env)); |
|
| 2398 |
cpu_fprintf(f, "NIP " REGX " LR " REGX " CTR " REGX "\n", |
|
| 2399 |
env->nip, env->lr, env->ctr); |
|
| 2400 |
cpu_fprintf(f, "MSR " REGX FILL " XER %08x TB %08x %08x DECR %08x\n", |
|
| 2401 |
do_load_msr(env), do_load_xer(env), cpu_ppc_load_tbu(env), |
|
| 2402 |
cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env)); |
|
| 3123 | 2403 |
for (i = 0; i < 32; i++) {
|
| 3124 |
if ((i & 7) == 0)
|
|
| 3125 |
cpu_fprintf(f, "GPR%02d:", i);
|
|
| 3126 |
cpu_fprintf(f, " %08x", env->gpr[i]);
|
|
| 3127 |
if ((i & 7) == 7)
|
|
| 2404 |
if ((i & (RGPL - 1)) == 0)
|
|
| 2405 |
cpu_fprintf(f, "GPR%02d", i); |
|
| 2406 |
cpu_fprintf(f, " " REGX, env->gpr[i]);
|
|
| 2407 |
if ((i & (RGPL - 1)) == (RGPL - 1))
|
|
| 3128 | 2408 |
cpu_fprintf(f, "\n"); |
| 3129 | 2409 |
} |
| 3130 |
cpu_fprintf(f, "CR: 0x");
|
|
| 2410 |
cpu_fprintf(f, "CR ");
|
|
| 3131 | 2411 |
for (i = 0; i < 8; i++) |
| 3132 | 2412 |
cpu_fprintf(f, "%01x", env->crf[i]); |
| 3133 | 2413 |
cpu_fprintf(f, " ["); |
| ... | ... | |
| 3141 | 2421 |
a = 'E'; |
| 3142 | 2422 |
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
| 3143 | 2423 |
} |
| 3144 |
cpu_fprintf(f, " ] "); |
|
| 3145 |
cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env), |
|
| 3146 |
cpu_ppc_load_tbl(env)); |
|
| 3147 |
for (i = 0; i < 16; i++) {
|
|
| 3148 |
if ((i & 3) == 0) |
|
| 3149 |
cpu_fprintf(f, "FPR%02d:", i); |
|
| 2424 |
cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve); |
|
| 2425 |
for (i = 0; i < 32; i++) {
|
|
| 2426 |
if ((i & (RFPL - 1)) == 0) |
|
| 2427 |
cpu_fprintf(f, "FPR%02d", i); |
|
| 3150 | 2428 |
cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i])); |
| 3151 |
if ((i & 3) == 3)
|
|
| 2429 |
if ((i & (RFPL - 1)) == (RFPL - 1))
|
|
| 3152 | 2430 |
cpu_fprintf(f, "\n"); |
| 3153 | 2431 |
} |
| 3154 |
cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n", |
|
| 3155 |
env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env)); |
|
| 3156 |
cpu_fprintf(f, "reservation 0x%08x\n", env->reserve); |
|
| 3157 |
} |
|
| 3158 |
|
|
| 3159 |
CPUPPCState *cpu_ppc_init(void) |
|
| 3160 |
{
|
|
| 3161 |
CPUPPCState *env; |
|
| 3162 |
|
|
| 3163 |
cpu_exec_init(); |
|
| 3164 |
|
|
| 3165 |
env = qemu_mallocz(sizeof(CPUPPCState)); |
|
| 3166 |
if (!env) |
|
| 3167 |
return NULL; |
|
| 3168 |
// env->spr[PVR] = 0; /* Basic PPC */ |
|
| 3169 |
env->spr[PVR] = 0x00080100; /* G3 CPU */ |
|
| 3170 |
// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */ |
|
| 3171 |
// env->spr[PVR] = 0x00070100; /* IBM 750FX */ |
|
| 3172 |
tlb_flush(env, 1); |
|
| 3173 |
#if defined (DO_SINGLE_STEP) |
|
| 3174 |
/* Single step trace mode */ |
|
| 3175 |
msr_se = 1; |
|
| 3176 |
#endif |
|
| 3177 |
msr_fp = 1; /* Allow floating point exceptions */ |
|
| 3178 |
msr_me = 1; /* Allow machine check exceptions */ |
|
| 3179 |
#if defined(CONFIG_USER_ONLY) |
|
| 3180 |
msr_pr = 1; |
|
| 3181 |
cpu_ppc_register(env, 0x00080000); |
|
| 3182 |
#else |
|
| 3183 |
env->nip = 0xFFFFFFFC; |
|
| 3184 |
#endif |
|
| 3185 |
cpu_single_env = env; |
|
| 3186 |
return env; |
|
| 3187 |
} |
|
| 3188 |
|
|
| 3189 |
int cpu_ppc_register (CPUPPCState *env, uint32_t pvr) |
|
| 3190 |
{
|
|
| 3191 |
env->spr[PVR] = pvr; |
|
| 3192 |
if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0) |
|
| 3193 |
return -1; |
|
| 3194 |
init_spr_rights(env->spr[PVR]); |
|
| 2432 |
cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL |
|
| 2433 |
"SDR1 " REGX "\n", |
|
| 2434 |
env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1); |
|
| 3195 | 2435 |
|
| 3196 |
return 0; |
|
| 3197 |
} |
|
| 3198 |
|
|
| 3199 |
void cpu_ppc_close(CPUPPCState *env) |
|
| 3200 |
{
|
|
| 3201 |
/* Should also remove all opcode tables... */ |
|
| 3202 |
free(env); |
|
| 2436 |
#undef REGX |
|
| 2437 |
#undef RGPL |
|
| 2438 |
#undef RFPL |
|
| 2439 |
#undef FILL |
|
| 3203 | 2440 |
} |
| 3204 | 2441 |
|
| 3205 | 2442 |
/*****************************************************************************/ |
| ... | ... | |
| 3219 | 2456 |
ctx.nip = pc_start; |
| 3220 | 2457 |
ctx.tb = tb; |
| 3221 | 2458 |
ctx.exception = EXCP_NONE; |
| 2459 |
ctx.spr_cb = env->spr_cb; |
|
| 3222 | 2460 |
#if defined(CONFIG_USER_ONLY) |
| 3223 | 2461 |
ctx.mem_idx = msr_le; |
| 3224 | 2462 |
#else |
| ... | ... | |
| 3226 | 2464 |
ctx.mem_idx = ((1 - msr_pr) << 1) | msr_le; |
| 3227 | 2465 |
#endif |
| 3228 | 2466 |
ctx.fpu_enabled = msr_fp; |
| 3229 |
#if defined (DO_SINGLE_STEP) |
|
| 2467 |
#if defined (DO_SINGLE_STEP) && 0
|
|
| 3230 | 2468 |
/* Single step trace mode */ |
| 3231 | 2469 |
msr_se = 1; |
| 3232 | 2470 |
#endif |
| ... | ... | |
| 3264 | 2502 |
} |
| 3265 | 2503 |
#endif |
| 3266 | 2504 |
ctx.nip += 4; |
| 3267 |
table = ppc_opcodes;
|
|
| 2505 |
table = env->opcodes;
|
|
| 3268 | 2506 |
handler = table[opc1(ctx.opcode)]; |
| 3269 | 2507 |
if (is_indirect_opcode(handler)) {
|
| 3270 | 2508 |
table = ind_table(handler); |
| ... | ... | |
| 3322 | 2560 |
RET_EXCP(ctxp, EXCP_TRACE, 0); |
| 3323 | 2561 |
} |
| 3324 | 2562 |
/* if we reach a page boundary, stop generation */ |
| 3325 |
if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) |
|
| 2563 |
if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
|
|
| 3326 | 2564 |
break; |
| 3327 | 2565 |
} |
| 2566 |
#if defined (DO_SINGLE_STEP) |
|
| 2567 |
break; |
|
| 2568 |
#endif |
|
| 2569 |
} |
|
| 3328 | 2570 |
if (ctx.exception == EXCP_NONE) {
|
| 3329 | 2571 |
gen_op_b((unsigned long)ctx.tb, ctx.nip); |
| 3330 | 2572 |
} else if (ctx.exception != EXCP_BRANCH) {
|
Also available in: Unified diff