root / hw / ppc_chrp.c @ 3fc6c082
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/*
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* QEMU PPC CHRP/PMAC hardware System Emulator
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#define BIOS_FILENAME "ppc_rom.bin" |
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#define NVRAM_SIZE 0x2000 |
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#define KERNEL_LOAD_ADDR 0x01000000 |
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#define INITRD_LOAD_ADDR 0x01800000 |
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/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
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NVRAM (not implemented). */
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static int dbdma_mem_index; |
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static int cuda_mem_index; |
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static int ide0_mem_index = -1; |
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static int ide1_mem_index = -1; |
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static int openpic_mem_index = -1; |
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static int heathrow_pic_mem_index = -1; |
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/* DBDMA: currently no op - should suffice right now */
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static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
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} |
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static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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} |
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static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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} |
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static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
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return 0; |
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} |
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static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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return 0; |
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} |
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static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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return 0; |
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} |
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static CPUWriteMemoryFunc *dbdma_write[] = {
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&dbdma_writeb, |
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&dbdma_writew, |
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&dbdma_writel, |
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}; |
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static CPUReadMemoryFunc *dbdma_read[] = {
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&dbdma_readb, |
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&dbdma_readw, |
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&dbdma_readl, |
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}; |
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static void macio_map(PCIDevice *pci_dev, int region_num, |
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uint32_t addr, uint32_t size, int type)
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{ |
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if (heathrow_pic_mem_index >= 0) { |
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cpu_register_physical_memory(addr + 0x00000, 0x1000, |
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heathrow_pic_mem_index); |
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} |
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cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index); |
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cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index); |
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if (ide0_mem_index >= 0) |
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cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index); |
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if (ide1_mem_index >= 0) |
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cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index); |
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if (openpic_mem_index >= 0) { |
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cpu_register_physical_memory(addr + 0x40000, 0x40000, |
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openpic_mem_index); |
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} |
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} |
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static void macio_init(PCIBus *bus) |
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{ |
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PCIDevice *d; |
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d = pci_register_device(bus, "macio", sizeof(PCIDevice), |
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-1, NULL, NULL); |
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/* Note: this code is strongly inspirated from the corresponding code
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in PearPC */
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d->config[0x00] = 0x6b; // vendor_id |
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d->config[0x01] = 0x10; |
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d->config[0x02] = 0x22; |
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d->config[0x03] = 0x00; |
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d->config[0x0a] = 0x00; // class_sub = pci2pci |
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d->config[0x0b] = 0xff; // class_base = bridge |
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d->config[0x0e] = 0x00; // header_type |
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d->config[0x3d] = 0x01; // interrupt on pin 1 |
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dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL); |
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pci_register_io_region(d, 0, 0x80000, |
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PCI_ADDRESS_SPACE_MEM, macio_map); |
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} |
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/* UniN device */
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static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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} |
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static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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return 0; |
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} |
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static CPUWriteMemoryFunc *unin_write[] = {
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&unin_writel, |
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&unin_writel, |
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&unin_writel, |
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}; |
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static CPUReadMemoryFunc *unin_read[] = {
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&unin_readl, |
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&unin_readl, |
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&unin_readl, |
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}; |
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/* temporary frame buffer OSI calls for the video.x driver. The right
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solution is to modify the driver to use VGA PCI I/Os */
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static int vga_osi_call(CPUState *env) |
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{ |
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static int vga_vbl_enabled; |
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int linesize;
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// printf("osi_call R5=%d\n", env->gpr[5]);
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/* same handler as PearPC, coming from the original MOL video
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driver. */
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switch(env->gpr[5]) { |
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case 4: |
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break;
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case 28: /* set_vmode */ |
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if (env->gpr[6] != 1 || env->gpr[7] != 0) |
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env->gpr[3] = 1; |
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else
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env->gpr[3] = 0; |
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break;
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case 29: /* get_vmode_info */ |
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if (env->gpr[6] != 0) { |
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if (env->gpr[6] != 1 || env->gpr[7] != 0) { |
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env->gpr[3] = 1; |
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break;
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} |
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} |
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env->gpr[3] = 0; |
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env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ |
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env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ |
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env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ |
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env->gpr[7] = 85 << 16; /* refresh rate */ |
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env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ |
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linesize = ((graphic_depth + 7) >> 3) * graphic_width; |
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linesize = (linesize + 3) & ~3; |
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env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ |
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break;
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case 31: /* set_video power */ |
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env->gpr[3] = 0; |
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break;
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case 39: /* video_ctrl */ |
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if (env->gpr[6] == 0 || env->gpr[6] == 1) |
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vga_vbl_enabled = env->gpr[6];
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env->gpr[3] = 0; |
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break;
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case 47: |
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break;
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case 59: /* set_color */ |
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/* R6 = index, R7 = RGB */
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env->gpr[3] = 0; |
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break;
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case 64: /* get color */ |
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/* R6 = index */
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env->gpr[3] = 0; |
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break;
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case 116: /* set hwcursor */ |
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/* R6 = x, R7 = y, R8 = visible, R9 = data */
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break;
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default:
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fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]); |
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break;
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} |
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return 1; /* osi_call handled */ |
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} |
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/* XXX: suppress that */
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static void pic_irq_request(void *opaque, int level) |
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{ |
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} |
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/* PowerPC CHRP hardware initialisation */
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static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, |
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DisplayState *ds, const char **fd_filename, |
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int snapshot,
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const char *kernel_filename, |
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const char *kernel_cmdline, |
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const char *initrd_filename, |
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int is_heathrow)
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{ |
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char buf[1024]; |
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SetIRQFunc *set_irq; |
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void *pic;
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m48t59_t *nvram; |
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int PPC_io_memory, unin_memory;
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int ret, linux_boot, i;
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unsigned long bios_offset; |
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
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ppc_def_t *def; |
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PCIBus *pci_bus; |
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const char *arch_name; |
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linux_boot = (kernel_filename != NULL);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* allocate and load BIOS */
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bios_offset = ram_size + vga_ram_size; |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
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ret = load_image(buf, phys_ram_base + bios_offset); |
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if (ret != BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
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exit(1);
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} |
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cpu_register_physical_memory((uint32_t)(-BIOS_SIZE), |
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BIOS_SIZE, bios_offset | IO_MEM_ROM); |
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cpu_single_env->nip = 0xfffffffc;
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR; |
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
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if (kernel_size < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR; |
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initrd_size = load_image(initrd_filename, |
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phys_ram_base + initrd_base); |
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if (initrd_size < 0) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
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exit(1);
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} |
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} else {
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initrd_base = 0;
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initrd_size = 0;
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} |
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boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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} |
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/* Register CPU as a 74x/75x */
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/* XXX: CPU model (or PVR) should be provided on command line */
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// ppc_find_by_name("750gx", &def); // Linux boot OK
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// ppc_find_by_name("750fx", &def); // Linux boot OK
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/* Linux does not boot on 750cxe (and probably other 750cx based)
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* because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
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*/
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// ppc_find_by_name("750cxe", &def);
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// ppc_find_by_name("750p", &def);
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// ppc_find_by_name("740p", &def);
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ppc_find_by_name("750", &def);
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// ppc_find_by_name("740", &def);
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// ppc_find_by_name("G3", &def);
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// ppc_find_by_name("604r", &def);
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// ppc_find_by_name("604e", &def);
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// ppc_find_by_name("604", &def);
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if (def == NULL) { |
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cpu_abort(cpu_single_env, "Unable to find PowerPC CPU definition\n");
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} |
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cpu_ppc_register(cpu_single_env, def); |
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/* Set time-base frequency to 10 Mhz */
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cpu_ppc_tb_init(cpu_single_env, 10UL * 1000UL * 1000UL); |
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cpu_single_env->osi_call = vga_osi_call; |
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if (is_heathrow) {
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isa_mem_base = 0x80000000;
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pci_bus = pci_grackle_init(0xfec00000);
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/* Register 2 MB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); |
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cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory); |
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/* init basic PC hardware */
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vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
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vga_ram_size); |
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pic = heathrow_pic_init(&heathrow_pic_mem_index); |
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set_irq = heathrow_pic_set_irq; |
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pci_set_pic(pci_bus, set_irq, pic); |
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/* XXX: suppress that */
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pic_init(pic_irq_request, NULL);
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hds[0]); |
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for(i = 0; i < nb_nics; i++) { |
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pci_ne2000_init(pci_bus, &nd_table[i]); |
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} |
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pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
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/* cuda also initialize ADB */
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cuda_mem_index = cuda_init(set_irq, pic, 0x12);
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adb_kbd_init(&adb_bus); |
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adb_mouse_init(&adb_bus); |
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macio_init(pci_bus); |
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE); |
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arch_name = "HEATHROW";
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} else {
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isa_mem_base = 0x80000000;
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pci_bus = pci_pmac_init(); |
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/* Register 8 MB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); |
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cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory); |
360 |
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/* UniN init */
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unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); |
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cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); |
364 |
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/* init basic PC hardware */
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vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
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vga_ram_size); |
368 |
pic = openpic_init(NULL, &openpic_mem_index, 1); |
369 |
set_irq = openpic_set_irq; |
370 |
pci_set_pic(pci_bus, set_irq, pic); |
371 |
|
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/* XXX: suppress that */
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pic_init(pic_irq_request, NULL);
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|
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hds[0]); |
377 |
|
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for(i = 0; i < nb_nics; i++) { |
379 |
pci_ne2000_init(pci_bus, &nd_table[i]); |
380 |
} |
381 |
|
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#if 1 |
383 |
ide0_mem_index = pmac_ide_init(&bs_table[0], set_irq, pic, 0x13); |
384 |
ide1_mem_index = pmac_ide_init(&bs_table[2], set_irq, pic, 0x14); |
385 |
#else
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pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
387 |
#endif
|
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/* cuda also initialize ADB */
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cuda_mem_index = cuda_init(set_irq, pic, 0x19);
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|
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adb_kbd_init(&adb_bus); |
392 |
adb_mouse_init(&adb_bus); |
393 |
|
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macio_init(pci_bus); |
395 |
|
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE); |
397 |
|
398 |
arch_name = "MAC99";
|
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} |
400 |
|
401 |
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
402 |
graphic_depth = 15;
|
403 |
|
404 |
PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device, |
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kernel_base, kernel_size, |
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kernel_cmdline, |
407 |
initrd_base, initrd_size, |
408 |
/* XXX: need an option to load a NVRAM image */
|
409 |
0,
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graphic_width, graphic_height, graphic_depth); |
411 |
/* No PCI init: the BIOS will do it */
|
412 |
|
413 |
/* Special port to get debug messages from Open-Firmware */
|
414 |
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
415 |
} |
416 |
|
417 |
static void ppc_core99_init(int ram_size, int vga_ram_size, int boot_device, |
418 |
DisplayState *ds, const char **fd_filename, |
419 |
int snapshot,
|
420 |
const char *kernel_filename, |
421 |
const char *kernel_cmdline, |
422 |
const char *initrd_filename) |
423 |
{ |
424 |
ppc_chrp_init(ram_size, vga_ram_size, boot_device, |
425 |
ds, fd_filename, snapshot, |
426 |
kernel_filename, kernel_cmdline, |
427 |
initrd_filename, 0);
|
428 |
} |
429 |
|
430 |
static void ppc_heathrow_init(int ram_size, int vga_ram_size, int boot_device, |
431 |
DisplayState *ds, const char **fd_filename, |
432 |
int snapshot,
|
433 |
const char *kernel_filename, |
434 |
const char *kernel_cmdline, |
435 |
const char *initrd_filename) |
436 |
{ |
437 |
ppc_chrp_init(ram_size, vga_ram_size, boot_device, |
438 |
ds, fd_filename, snapshot, |
439 |
kernel_filename, kernel_cmdline, |
440 |
initrd_filename, 1);
|
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} |
442 |
|
443 |
QEMUMachine core99_machine = { |
444 |
"core99",
|
445 |
"Core99 based PowerMAC",
|
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ppc_core99_init, |
447 |
}; |
448 |
|
449 |
QEMUMachine heathrow_machine = { |
450 |
"heathrow",
|
451 |
"Heathrow based PowerMAC",
|
452 |
ppc_heathrow_init, |
453 |
}; |