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/*
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* PowerPC emulation cpu definitions for qemu.
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*
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* Copyright (c) 2003-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#include "config.h" |
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#define TARGET_LONG_BITS 32 |
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#include "cpu-defs.h" |
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#include <setjmp.h> |
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#include "softfloat.h" |
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#define TARGET_HAS_ICE 1 |
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/*****************************************************************************/
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/* PVR definitions for most known PowerPC */
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enum {
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/* PowerPC 401 cores */
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CPU_PPC_401A1 = 0x00210000,
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CPU_PPC_401B2 = 0x00220000,
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CPU_PPC_401C2 = 0x00230000,
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CPU_PPC_401D2 = 0x00240000,
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CPU_PPC_401E2 = 0x00250000,
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CPU_PPC_401F2 = 0x00260000,
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CPU_PPC_401G2 = 0x00270000,
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CPU_PPC_IOP480 = 0x40100000,
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/* PowerPC 403 cores */
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CPU_PPC_403GA = 0x00200000,
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CPU_PPC_403GB = 0x00200100,
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CPU_PPC_403GC = 0x00200200,
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CPU_PPC_403GCX = 0x00201400,
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/* PowerPC 405 cores */
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CPU_PPC_405 = 0x40110000,
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CPU_PPC_405EP = 0x51210000,
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CPU_PPC_405GPR = 0x50910000,
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CPU_PPC_405D2 = 0x20010000,
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CPU_PPC_405D4 = 0x41810000,
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CPU_PPC_NPE405H = 0x41410000,
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CPU_PPC_NPE405L = 0x41610000,
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#if 0
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CPU_PPC_STB02 = xxx,
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#endif
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CPU_PPC_STB03 = 0x40310000,
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#if 0
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CPU_PPC_STB04 = xxx,
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#endif
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CPU_PPC_STB25 = 0x51510000,
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#if 0
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CPU_PPC_STB130 = xxx,
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#endif
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/* PowerPC 440 cores */
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CPU_PPC_440EP = 0x42220000,
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CPU_PPC_440GP = 0x40120400,
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CPU_PPC_440GX = 0x51B20000,
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/* PowerPC MPC 8xx cores */
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CPU_PPC_8540 = 0x80200000,
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CPU_PPC_8xx = 0x00500000,
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CPU_PPC_8240 = 0x00810100,
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CPU_PPC_8245 = 0x00811014,
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/* PowerPC 6xx cores */
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CPU_PPC_601 = 0x00010000,
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CPU_PPC_602 = 0x00050000,
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CPU_PPC_603 = 0x00030000,
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CPU_PPC_603E = 0x00060000,
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CPU_PPC_603EV = 0x00070000,
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CPU_PPC_603R = 0x00071000,
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CPU_PPC_G2 = 0x80810000,
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CPU_PPC_G2LE = 0x80820000,
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CPU_PPC_604 = 0x00040000,
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CPU_PPC_604E = 0x00090000,
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CPU_PPC_604R = 0x000a0000,
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/* PowerPC 74x/75x cores (aka G3) */
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CPU_PPC_74x = 0x00080000,
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CPU_PPC_755 = 0x00083000,
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CPU_PPC_74xP = 0x10080000,
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CPU_PPC_750CXE22 = 0x00082202,
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CPU_PPC_750CXE24 = 0x00082214,
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CPU_PPC_750CXE24b = 0x00083214,
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CPU_PPC_750CXE31 = 0x00083211,
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CPU_PPC_750CXE31b = 0x00083311,
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#define CPU_PPC_750CXE CPU_PPC_750CXE31b
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CPU_PPC_750FX = 0x70000000,
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CPU_PPC_750GX = 0x70020000,
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/* PowerPC 74xx cores (aka G4) */
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CPU_PPC_7400 = 0x000C0000,
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CPU_PPC_7410 = 0x800C0000,
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CPU_PPC_7441 = 0x80000200,
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CPU_PPC_7450 = 0x80000000,
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CPU_PPC_7451 = 0x80000203,
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CPU_PPC_7455 = 0x80010000,
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CPU_PPC_7457 = 0x80020000,
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CPU_PPC_7457A = 0x80030000,
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/* 64 bits PowerPC */
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CPU_PPC_620 = 0x00140000,
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CPU_PPC_630 = 0x00400000,
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CPU_PPC_631 = 0x00410000,
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CPU_PPC_POWER4 = 0x00350000,
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CPU_PPC_POWER4P = 0x00380000,
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CPU_PPC_POWER5 = 0x003A0000,
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CPU_PPC_POWER5P = 0x003B0000,
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CPU_PPC_970 = 0x00390000,
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CPU_PPC_970FX = 0x003C0000,
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CPU_PPC_RS64 = 0x00330000,
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CPU_PPC_RS64II = 0x00340000,
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CPU_PPC_RS64III = 0x00360000,
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CPU_PPC_RS64IV = 0x00370000,
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/* Original POWER */
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/* XXX: should be POWER (RIOS), RSC3308, RSC4608,
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* POWER2 (RIOS2) & RSC2 (P2SC) here
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*/
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#if 0
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CPU_POWER = xxx,
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#endif
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#if 0
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CPU_POWER2 = xxx,
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#endif
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}; |
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/* System version register (used on MPC 8xx) */
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enum {
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PPC_SVR_8540 = 0x80300000,
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PPC_SVR_8541E = 0x807A0000,
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PPC_SVR_8555E = 0x80790000,
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PPC_SVR_8560 = 0x80700000,
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}; |
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/*****************************************************************************/
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/* Instruction types */
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enum {
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PPC_NONE = 0x00000000,
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/* integer operations instructions */
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/* flow control instructions */
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/* virtual memory instructions */
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/* ld/st with reservation instructions */
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/* cache control instructions */
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/* spr/msr access instructions */
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PPC_INSNS_BASE = 0x00000001,
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#define PPC_INTEGER PPC_INSNS_BASE
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#define PPC_FLOW PPC_INSNS_BASE
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#define PPC_MEM PPC_INSNS_BASE
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#define PPC_RES PPC_INSNS_BASE
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#define PPC_CACHE PPC_INSNS_BASE
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#define PPC_MISC PPC_INSNS_BASE
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/* floating point operations instructions */
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PPC_FLOAT = 0x00000002,
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/* more floating point operations instructions */
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PPC_FLOAT_EXT = 0x00000004,
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/* external control instructions */
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PPC_EXTERN = 0x00000008,
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/* segment register access instructions */
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PPC_SEGMENT = 0x00000010,
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/* Optional cache control instructions */
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PPC_CACHE_OPT = 0x00000020,
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/* Optional floating point op instructions */
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PPC_FLOAT_OPT = 0x00000040,
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/* Optional memory control instructions */
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PPC_MEM_TLBIA = 0x00000080,
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PPC_MEM_TLBIE = 0x00000100,
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PPC_MEM_TLBSYNC = 0x00000200,
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/* eieio & sync */
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PPC_MEM_SYNC = 0x00000400,
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/* PowerPC 6xx TLB management instructions */
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PPC_6xx_TLB = 0x00000800,
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/* Altivec support */
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PPC_ALTIVEC = 0x00001000,
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/* Time base support */
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PPC_TB = 0x00002000,
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/* Embedded PowerPC dedicated instructions */
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PPC_4xx_COMMON = 0x00004000,
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/* PowerPC 40x exception model */
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PPC_40x_EXCP = 0x00008000,
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/* PowerPC 40x specific instructions */
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PPC_40x_SPEC = 0x00010000,
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/* PowerPC 405 Mac instructions */
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PPC_405_MAC = 0x00020000,
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/* PowerPC 440 specific instructions */
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PPC_440_SPEC = 0x00040000,
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/* Specific extensions */
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/* Power-to-PowerPC bridge (601) */
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PPC_POWER_BR = 0x00080000,
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/* PowerPC 602 specific */
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PPC_602_SPEC = 0x00100000,
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/* Deprecated instructions */
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/* Original POWER instruction set */
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PPC_POWER = 0x00200000,
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/* POWER2 instruction set extension */
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PPC_POWER2 = 0x00400000,
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/* Power RTC support */
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PPC_POWER_RTC = 0x00800000,
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/* 64 bits PowerPC instructions */
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/* 64 bits PowerPC instruction set */
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PPC_64B = 0x01000000,
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/* 64 bits hypervisor extensions */
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PPC_64H = 0x02000000,
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/* 64 bits PowerPC "bridge" features */
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PPC_64_BRIDGE = 0x04000000,
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}; |
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/* CPU run-time flags (MMU and exception model) */
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enum {
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/* MMU model */
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#define PPC_FLAGS_MMU_MASK (0x0000000F) |
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/* Standard 32 bits PowerPC MMU */
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PPC_FLAGS_MMU_32B = 0x00000000,
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/* Standard 64 bits PowerPC MMU */
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PPC_FLAGS_MMU_64B = 0x00000001,
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/* PowerPC 601 MMU */
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PPC_FLAGS_MMU_601 = 0x00000002,
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/* PowerPC 6xx MMU with software TLB */
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PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
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/* PowerPC 4xx MMU with software TLB */
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PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
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/* PowerPC 403 MMU */
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PPC_FLAGS_MMU_403 = 0x00000005,
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/* Exception model */
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#define PPC_FLAGS_EXCP_MASK (0x000000F0) |
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/* Standard PowerPC exception model */
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PPC_FLAGS_EXCP_STD = 0x00000000,
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/* PowerPC 40x exception model */
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PPC_FLAGS_EXCP_40x = 0x00000010,
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/* PowerPC 601 exception model */
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PPC_FLAGS_EXCP_601 = 0x00000020,
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/* PowerPC 602 exception model */
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PPC_FLAGS_EXCP_602 = 0x00000030,
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/* PowerPC 603 exception model */
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PPC_FLAGS_EXCP_603 = 0x00000040,
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/* PowerPC 604 exception model */
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PPC_FLAGS_EXCP_604 = 0x00000050,
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/* PowerPC 7x0 exception model */
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PPC_FLAGS_EXCP_7x0 = 0x00000060,
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/* PowerPC 7x5 exception model */
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PPC_FLAGS_EXCP_7x5 = 0x00000070,
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/* PowerPC 74xx exception model */
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PPC_FLAGS_EXCP_74xx = 0x00000080,
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/* PowerPC 970 exception model */
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PPC_FLAGS_EXCP_970 = 0x00000090,
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}; |
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#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
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#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
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/*****************************************************************************/
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/* Supported instruction set definitions */
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/* This generates an empty opcode table... */
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#define PPC_INSNS_TODO (PPC_NONE)
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#define PPC_FLAGS_TODO (0x00000000) |
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/* PowerPC 40x instruction set */
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#define PPC_INSNS_4xx (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_4xx_COMMON)
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/* PowerPC 401 */
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#define PPC_INSNS_401 (PPC_INSNS_TODO)
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#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
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/* PowerPC 403 */
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#define PPC_INSNS_403 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_MEM_TLBIA | \
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PPC_40x_EXCP | PPC_40x_SPEC) |
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#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
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/* PowerPC 405 */
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#define PPC_INSNS_405 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_CACHE_OPT | \
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PPC_MEM_TLBIA | PPC_TB | PPC_40x_SPEC | PPC_40x_EXCP | \ |
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PPC_405_MAC) |
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#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
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/* PowerPC 440 */
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#define PPC_INSNS_440 (PPC_INSNS_4xx | PPC_CACHE_OPT | PPC_405_MAC | \
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PPC_440_SPEC) |
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#define PPC_FLAGS_440 (PPC_FLAGS_TODO)
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/* Non-embedded PowerPC */
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#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
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PPC_SEGMENT | PPC_MEM_TLBIE) |
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/* PowerPC 601 */
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#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
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#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
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/* PowerPC 602 */
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#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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PPC_MEM_TLBSYNC | PPC_TB) |
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#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
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/* PowerPC 603 */
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#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
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#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
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/* PowerPC G2 */
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#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
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#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
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/* PowerPC 604 */
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#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
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PPC_MEM_TLBSYNC | PPC_TB) |
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#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
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/* PowerPC 740/750 (aka G3) */
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#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
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PPC_MEM_TLBSYNC | PPC_TB) |
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#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
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/* PowerPC 745/755 */
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#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
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PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB) |
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#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
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/* PowerPC 74xx (aka G4) */
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#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
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PPC_MEM_TLBSYNC | PPC_TB) |
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#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
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/* Default PowerPC will be 604/970 */
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#define PPC_INSNS_PPC32 PPC_INSNS_604
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#define PPC_FLAGS_PPC32 PPC_FLAGS_604
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#if 0
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#define PPC_INSNS_PPC64 PPC_INSNS_970
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#define PPC_FLAGS_PPC64 PPC_FLAGS_970
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#endif
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#define PPC_INSNS_DEFAULT PPC_INSNS_604
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#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
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typedef struct ppc_def_t ppc_def_t; |
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/*****************************************************************************/
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/* Types used to describe some PowerPC registers */
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typedef struct CPUPPCState CPUPPCState; |
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typedef struct opc_handler_t opc_handler_t; |
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typedef struct ppc_tb_t ppc_tb_t; |
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typedef struct ppc_spr_t ppc_spr_t; |
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typedef struct ppc_dcr_t ppc_dcr_t; |
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typedef struct ppc_avr_t ppc_avr_t; |
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/* SPR access micro-ops generations callbacks */
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struct ppc_spr_t {
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void (*uea_read)(void *opaque, int spr_num); |
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void (*uea_write)(void *opaque, int spr_num); |
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void (*oea_read)(void *opaque, int spr_num); |
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void (*oea_write)(void *opaque, int spr_num); |
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const unsigned char *name; |
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}; |
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/* Altivec registers (128 bits) */
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struct ppc_avr_t {
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uint32_t u[4];
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}; |
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/* Software TLB cache */
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typedef struct ppc_tlb_t ppc_tlb_t; |
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struct ppc_tlb_t {
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/* Physical page number */
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target_phys_addr_t RPN; |
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/* Virtual page number */
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target_ulong VPN; |
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/* Page size */
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target_ulong size; |
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/* Protection bits */
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int prot;
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int is_user;
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uint32_t private; |
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uint32_t flags; |
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}; |
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/*****************************************************************************/
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/* Machine state register bits definition */
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#define MSR_SF 63 /* Sixty-four-bit mode */ |
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#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
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#define MSR_HV 60 /* hypervisor state */ |
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#define MSR_VR 25 /* altivec available */ |
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#define MSR_AP 23 /* Access privilege state on 602 */ |
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#define MSR_SA 22 /* Supervisor access mode on 602 */ |
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#define MSR_KEY 19 /* key bit on 603e */ |
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#define MSR_POW 18 /* Power management */ |
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#define MSR_WE 18 /* Wait state enable on embedded PowerPC */ |
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#define MSR_TGPR 17 /* TGPR usage on 602/603 */ |
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#define MSR_TLB 17 /* TLB on ? */ |
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#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */ |
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#define MSR_ILE 16 /* Interrupt little-endian mode */ |
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#define MSR_EE 15 /* External interrupt enable */ |
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#define MSR_PR 14 /* Problem state */ |
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#define MSR_FP 13 /* Floating point available */ |
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#define MSR_ME 12 /* Machine check interrupt enable */ |
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#define MSR_FE0 11 /* Floating point exception mode 0 */ |
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#define MSR_SE 10 /* Single-step trace enable */ |
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#define MSR_DWE 10 /* Debug wait enable on 405 */ |
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#define MSR_BE 9 /* Branch trace enable */ |
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#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */ |
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#define MSR_FE1 8 /* Floating point exception mode 1 */ |
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#define MSR_AL 7 /* AL bit on POWER */ |
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#define MSR_IP 6 /* Interrupt prefix */ |
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#define MSR_IR 5 /* Instruction relocate */ |
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#define MSR_IS 5 /* Instruction address space on embedded PowerPC */ |
400 |
#define MSR_DR 4 /* Data relocate */ |
401 |
#define MSR_DS 4 /* Data address space on embedded PowerPC */ |
402 |
#define MSR_PE 3 /* Protection enable on 403 */ |
403 |
#define MSR_EP 3 /* Exception prefix on 601 */ |
404 |
#define MSR_PX 2 /* Protection exclusive on 403 */ |
405 |
#define MSR_PMM 2 /* Performance monitor mark on POWER */ |
406 |
#define MSR_RI 1 /* Recoverable interrupt */ |
407 |
#define MSR_LE 0 /* Little-endian mode */ |
408 |
#define msr_sf env->msr[MSR_SF]
|
409 |
#define msr_isf env->msr[MSR_ISF]
|
410 |
#define msr_hv env->msr[MSR_HV]
|
411 |
#define msr_vr env->msr[MSR_VR]
|
412 |
#define msr_ap env->msr[MSR_AP]
|
413 |
#define msr_sa env->msr[MSR_SA]
|
414 |
#define msr_key env->msr[MSR_KEY]
|
415 |
#define msr_pow env->msr[MSR_POW]
|
416 |
#define msr_we env->msr[MSR_WE]
|
417 |
#define msr_tgpr env->msr[MSR_TGPR]
|
418 |
#define msr_tlb env->msr[MSR_TLB]
|
419 |
#define msr_ce env->msr[MSR_CE]
|
420 |
#define msr_ile env->msr[MSR_ILE]
|
421 |
#define msr_ee env->msr[MSR_EE]
|
422 |
#define msr_pr env->msr[MSR_PR]
|
423 |
#define msr_fp env->msr[MSR_FP]
|
424 |
#define msr_me env->msr[MSR_ME]
|
425 |
#define msr_fe0 env->msr[MSR_FE0]
|
426 |
#define msr_se env->msr[MSR_SE]
|
427 |
#define msr_dwe env->msr[MSR_DWE]
|
428 |
#define msr_be env->msr[MSR_BE]
|
429 |
#define msr_de env->msr[MSR_DE]
|
430 |
#define msr_fe1 env->msr[MSR_FE1]
|
431 |
#define msr_al env->msr[MSR_AL]
|
432 |
#define msr_ip env->msr[MSR_IP]
|
433 |
#define msr_ir env->msr[MSR_IR]
|
434 |
#define msr_is env->msr[MSR_IS]
|
435 |
#define msr_dr env->msr[MSR_DR]
|
436 |
#define msr_ds env->msr[MSR_DS]
|
437 |
#define msr_pe env->msr[MSR_PE]
|
438 |
#define msr_ep env->msr[MSR_EP]
|
439 |
#define msr_px env->msr[MSR_PX]
|
440 |
#define msr_pmm env->msr[MSR_PMM]
|
441 |
#define msr_ri env->msr[MSR_RI]
|
442 |
#define msr_le env->msr[MSR_LE]
|
443 |
|
444 |
/*****************************************************************************/
|
445 |
/* The whole PowerPC CPU context */
|
446 |
struct CPUPPCState {
|
447 |
/* First are the most commonly used resources
|
448 |
* during translated code execution
|
449 |
*/
|
450 |
#if TARGET_LONG_BITS > HOST_LONG_BITS
|
451 |
/* temporary fixed-point registers
|
452 |
* used to emulate 64 bits target on 32 bits hosts
|
453 |
*/
|
454 |
target_ulong t0, t1, t2; |
455 |
#endif
|
456 |
/* general purpose registers */
|
457 |
target_ulong gpr[32];
|
458 |
/* LR */
|
459 |
target_ulong lr; |
460 |
/* CTR */
|
461 |
target_ulong ctr; |
462 |
/* condition register */
|
463 |
uint8_t crf[8];
|
464 |
/* XER */
|
465 |
/* XXX: We use only 5 fields, but we want to keep the structure aligned */
|
466 |
uint8_t xer[8];
|
467 |
/* Reservation address */
|
468 |
target_ulong reserve; |
469 |
|
470 |
/* Those ones are used in supervisor mode only */
|
471 |
/* machine state register */
|
472 |
uint8_t msr[64];
|
473 |
/* temporary general purpose registers */
|
474 |
target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ |
475 |
|
476 |
/* Floating point execution context */
|
477 |
/* temporary float registers */
|
478 |
float64 ft0; |
479 |
float64 ft1; |
480 |
float64 ft2; |
481 |
float_status fp_status; |
482 |
/* floating point registers */
|
483 |
float64 fpr[32];
|
484 |
/* floating point status and control register */
|
485 |
uint8_t fpscr[8];
|
486 |
|
487 |
/* soft mmu support */
|
488 |
/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
|
489 |
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
|
490 |
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
|
491 |
int access_type; /* when a memory exception occurs, the access |
492 |
type is stored here */
|
493 |
/* in order to avoid passing too many arguments to the memory
|
494 |
write helpers, we store some rarely used information in the CPU
|
495 |
context) */
|
496 |
unsigned long mem_write_pc; /* host pc at which the memory was |
497 |
written */
|
498 |
unsigned long mem_write_vaddr; /* target virtual addr at which the |
499 |
memory was written */
|
500 |
|
501 |
/* MMU context */
|
502 |
/* Address space register */
|
503 |
target_ulong asr; |
504 |
/* segment registers */
|
505 |
target_ulong sdr1; |
506 |
target_ulong sr[16];
|
507 |
/* BATs */
|
508 |
int nb_BATs;
|
509 |
target_ulong DBAT[2][8]; |
510 |
target_ulong IBAT[2][8]; |
511 |
|
512 |
/* Other registers */
|
513 |
/* Special purpose registers */
|
514 |
target_ulong spr[1024];
|
515 |
/* Altivec registers */
|
516 |
ppc_avr_t avr[32];
|
517 |
uint32_t vscr; |
518 |
|
519 |
/* Internal devices resources */
|
520 |
/* Time base and decrementer */
|
521 |
ppc_tb_t *tb_env; |
522 |
/* Device control registers */
|
523 |
int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val); |
524 |
int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val); |
525 |
ppc_dcr_t *dcr_env; |
526 |
|
527 |
/* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
|
528 |
int nb_tlb;
|
529 |
int nb_ways, last_way;
|
530 |
ppc_tlb_t tlb[128];
|
531 |
/* Callbacks for specific checks on some implementations */
|
532 |
int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot, |
533 |
target_ulong vaddr, int rw, int acc_type, |
534 |
int is_user);
|
535 |
/* 403 dedicated access protection registers */
|
536 |
target_ulong pb[4];
|
537 |
|
538 |
/* Those resources are used during exception processing */
|
539 |
/* CPU model definition */
|
540 |
uint64_t msr_mask; |
541 |
uint32_t flags; |
542 |
|
543 |
int exception_index;
|
544 |
int error_code;
|
545 |
int interrupt_request;
|
546 |
|
547 |
/* Those resources are used only during code translation */
|
548 |
/* Next instruction pointer */
|
549 |
target_ulong nip; |
550 |
/* SPR translation callbacks */
|
551 |
ppc_spr_t spr_cb[1024];
|
552 |
/* opcode handlers */
|
553 |
opc_handler_t *opcodes[0x40];
|
554 |
|
555 |
/* Those resources are used only in Qemu core */
|
556 |
jmp_buf jmp_env; |
557 |
int user_mode_only; /* user mode only simulation */ |
558 |
struct TranslationBlock *current_tb; /* currently executing TB */ |
559 |
uint32_t hflags; |
560 |
|
561 |
/* ice debug support */
|
562 |
target_ulong breakpoints[MAX_BREAKPOINTS]; |
563 |
int nb_breakpoints;
|
564 |
int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
565 |
|
566 |
/* Power management */
|
567 |
int power_mode;
|
568 |
|
569 |
/* temporary hack to handle OSI calls (only used if non NULL) */
|
570 |
int (*osi_call)(struct CPUPPCState *env); |
571 |
|
572 |
/* user data */
|
573 |
void *opaque;
|
574 |
}; |
575 |
|
576 |
/*****************************************************************************/
|
577 |
CPUPPCState *cpu_ppc_init(void);
|
578 |
int cpu_ppc_exec(CPUPPCState *s);
|
579 |
void cpu_ppc_close(CPUPPCState *s);
|
580 |
/* you can call this signal handler from your SIGBUS and SIGSEGV
|
581 |
signal handlers to inform the virtual CPU of exceptions. non zero
|
582 |
is returned if the signal was handled by the virtual CPU. */
|
583 |
struct siginfo;
|
584 |
int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, |
585 |
void *puc);
|
586 |
|
587 |
void do_interrupt (CPUPPCState *env);
|
588 |
void cpu_loop_exit(void); |
589 |
|
590 |
void dump_stack (CPUPPCState *env);
|
591 |
|
592 |
target_ulong do_load_ibatu (CPUPPCState *env, int nr);
|
593 |
target_ulong do_load_ibatl (CPUPPCState *env, int nr);
|
594 |
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
595 |
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
596 |
target_ulong do_load_dbatu (CPUPPCState *env, int nr);
|
597 |
target_ulong do_load_dbatl (CPUPPCState *env, int nr);
|
598 |
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
599 |
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
600 |
|
601 |
target_ulong do_load_nip (CPUPPCState *env); |
602 |
void do_store_nip (CPUPPCState *env, target_ulong value);
|
603 |
target_ulong do_load_sdr1 (CPUPPCState *env); |
604 |
void do_store_sdr1 (CPUPPCState *env, target_ulong value);
|
605 |
target_ulong do_load_asr (CPUPPCState *env); |
606 |
void do_store_asr (CPUPPCState *env, target_ulong value);
|
607 |
target_ulong do_load_sr (CPUPPCState *env, int srnum);
|
608 |
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
609 |
uint32_t do_load_cr (CPUPPCState *env); |
610 |
void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask);
|
611 |
uint32_t do_load_xer (CPUPPCState *env); |
612 |
void do_store_xer (CPUPPCState *env, uint32_t value);
|
613 |
target_ulong do_load_msr (CPUPPCState *env); |
614 |
void do_store_msr (CPUPPCState *env, target_ulong value);
|
615 |
float64 do_load_fpscr (CPUPPCState *env); |
616 |
void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask);
|
617 |
|
618 |
void do_compute_hflags (CPUPPCState *env);
|
619 |
|
620 |
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def); |
621 |
int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
|
622 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
623 |
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
|
624 |
|
625 |
/* Time-base and decrementer management */
|
626 |
#ifndef NO_CPU_IO_DEFS
|
627 |
uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
628 |
uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
629 |
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
|
630 |
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
|
631 |
uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
632 |
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
|
633 |
#endif
|
634 |
|
635 |
#define TARGET_PAGE_BITS 12 |
636 |
#include "cpu-all.h" |
637 |
|
638 |
/*****************************************************************************/
|
639 |
/* Registers definitions */
|
640 |
#define ugpr(n) (env->gpr[n])
|
641 |
|
642 |
#define XER_SO 31 |
643 |
#define XER_OV 30 |
644 |
#define XER_CA 29 |
645 |
#define XER_CMP 8 |
646 |
#define XER_BC 0 |
647 |
#define xer_so env->xer[4] |
648 |
#define xer_ov env->xer[6] |
649 |
#define xer_ca env->xer[2] |
650 |
#define xer_cmp env->xer[1] |
651 |
#define xer_bc env->xer[0] |
652 |
|
653 |
/* SPR definitions */
|
654 |
#define SPR_MQ (0x000) |
655 |
#define SPR_XER (0x001) |
656 |
#define SPR_601_VRTCU (0x004) |
657 |
#define SPR_601_VRTCL (0x005) |
658 |
#define SPR_601_UDECR (0x006) |
659 |
#define SPR_LR (0x008) |
660 |
#define SPR_CTR (0x009) |
661 |
#define SPR_DSISR (0x012) |
662 |
#define SPR_DAR (0x013) |
663 |
#define SPR_601_RTCU (0x014) |
664 |
#define SPR_601_RTCL (0x015) |
665 |
#define SPR_DECR (0x016) |
666 |
#define SPR_SDR1 (0x019) |
667 |
#define SPR_SRR0 (0x01A) |
668 |
#define SPR_SRR1 (0x01B) |
669 |
#define SPR_440_PID (0x030) |
670 |
#define SPR_440_DECAR (0x036) |
671 |
#define SPR_CSRR0 (0x03A) |
672 |
#define SPR_CSRR1 (0x03B) |
673 |
#define SPR_440_DEAR (0x03D) |
674 |
#define SPR_440_ESR (0x03E) |
675 |
#define SPR_440_IVPR (0x03F) |
676 |
#define SPR_8xx_EIE (0x050) |
677 |
#define SPR_8xx_EID (0x051) |
678 |
#define SPR_8xx_NRE (0x052) |
679 |
#define SPR_58x_CMPA (0x090) |
680 |
#define SPR_58x_CMPB (0x091) |
681 |
#define SPR_58x_CMPC (0x092) |
682 |
#define SPR_58x_CMPD (0x093) |
683 |
#define SPR_58x_ICR (0x094) |
684 |
#define SPR_58x_DER (0x094) |
685 |
#define SPR_58x_COUNTA (0x096) |
686 |
#define SPR_58x_COUNTB (0x097) |
687 |
#define SPR_58x_CMPE (0x098) |
688 |
#define SPR_58x_CMPF (0x099) |
689 |
#define SPR_58x_CMPG (0x09A) |
690 |
#define SPR_58x_CMPH (0x09B) |
691 |
#define SPR_58x_LCTRL1 (0x09C) |
692 |
#define SPR_58x_LCTRL2 (0x09D) |
693 |
#define SPR_58x_ICTRL (0x09E) |
694 |
#define SPR_58x_BAR (0x09F) |
695 |
#define SPR_VRSAVE (0x100) |
696 |
#define SPR_USPRG0 (0x100) |
697 |
#define SPR_USPRG4 (0x104) |
698 |
#define SPR_USPRG5 (0x105) |
699 |
#define SPR_USPRG6 (0x106) |
700 |
#define SPR_USPRG7 (0x107) |
701 |
#define SPR_VTBL (0x10C) |
702 |
#define SPR_VTBU (0x10D) |
703 |
#define SPR_SPRG0 (0x110) |
704 |
#define SPR_SPRG1 (0x111) |
705 |
#define SPR_SPRG2 (0x112) |
706 |
#define SPR_SPRG3 (0x113) |
707 |
#define SPR_SPRG4 (0x114) |
708 |
#define SPR_SCOMC (0x114) |
709 |
#define SPR_SPRG5 (0x115) |
710 |
#define SPR_SCOMD (0x115) |
711 |
#define SPR_SPRG6 (0x116) |
712 |
#define SPR_SPRG7 (0x117) |
713 |
#define SPR_ASR (0x118) |
714 |
#define SPR_EAR (0x11A) |
715 |
#define SPR_TBL (0x11C) |
716 |
#define SPR_TBU (0x11D) |
717 |
#define SPR_SVR (0x11E) |
718 |
#define SPR_440_PIR (0x11E) |
719 |
#define SPR_PVR (0x11F) |
720 |
#define SPR_HSPRG0 (0x130) |
721 |
#define SPR_440_DBSR (0x130) |
722 |
#define SPR_HSPRG1 (0x131) |
723 |
#define SPR_440_DBCR0 (0x134) |
724 |
#define SPR_IBCR (0x135) |
725 |
#define SPR_440_DBCR1 (0x135) |
726 |
#define SPR_DBCR (0x136) |
727 |
#define SPR_HDEC (0x136) |
728 |
#define SPR_440_DBCR2 (0x136) |
729 |
#define SPR_HIOR (0x137) |
730 |
#define SPR_MBAR (0x137) |
731 |
#define SPR_RMOR (0x138) |
732 |
#define SPR_440_IAC1 (0x138) |
733 |
#define SPR_HRMOR (0x139) |
734 |
#define SPR_440_IAC2 (0x139) |
735 |
#define SPR_HSSR0 (0x13A) |
736 |
#define SPR_440_IAC3 (0x13A) |
737 |
#define SPR_HSSR1 (0x13B) |
738 |
#define SPR_440_IAC4 (0x13B) |
739 |
#define SPR_LPCR (0x13C) |
740 |
#define SPR_440_DAC1 (0x13C) |
741 |
#define SPR_LPIDR (0x13D) |
742 |
#define SPR_DABR2 (0x13D) |
743 |
#define SPR_440_DAC2 (0x13D) |
744 |
#define SPR_440_DVC1 (0x13E) |
745 |
#define SPR_440_DVC2 (0x13F) |
746 |
#define SPR_440_TSR (0x150) |
747 |
#define SPR_440_TCR (0x154) |
748 |
#define SPR_440_IVOR0 (0x190) |
749 |
#define SPR_440_IVOR1 (0x191) |
750 |
#define SPR_440_IVOR2 (0x192) |
751 |
#define SPR_440_IVOR3 (0x193) |
752 |
#define SPR_440_IVOR4 (0x194) |
753 |
#define SPR_440_IVOR5 (0x195) |
754 |
#define SPR_440_IVOR6 (0x196) |
755 |
#define SPR_440_IVOR7 (0x197) |
756 |
#define SPR_440_IVOR8 (0x198) |
757 |
#define SPR_440_IVOR9 (0x199) |
758 |
#define SPR_440_IVOR10 (0x19A) |
759 |
#define SPR_440_IVOR11 (0x19B) |
760 |
#define SPR_440_IVOR12 (0x19C) |
761 |
#define SPR_440_IVOR13 (0x19D) |
762 |
#define SPR_440_IVOR14 (0x19E) |
763 |
#define SPR_440_IVOR15 (0x19F) |
764 |
#define SPR_IBAT0U (0x210) |
765 |
#define SPR_IBAT0L (0x211) |
766 |
#define SPR_IBAT1U (0x212) |
767 |
#define SPR_IBAT1L (0x213) |
768 |
#define SPR_IBAT2U (0x214) |
769 |
#define SPR_IBAT2L (0x215) |
770 |
#define SPR_IBAT3U (0x216) |
771 |
#define SPR_IBAT3L (0x217) |
772 |
#define SPR_DBAT0U (0x218) |
773 |
#define SPR_DBAT0L (0x219) |
774 |
#define SPR_DBAT1U (0x21A) |
775 |
#define SPR_DBAT1L (0x21B) |
776 |
#define SPR_DBAT2U (0x21C) |
777 |
#define SPR_DBAT2L (0x21D) |
778 |
#define SPR_DBAT3U (0x21E) |
779 |
#define SPR_DBAT3L (0x21F) |
780 |
#define SPR_IBAT4U (0x230) |
781 |
#define SPR_IBAT4L (0x231) |
782 |
#define SPR_IBAT5U (0x232) |
783 |
#define SPR_IBAT5L (0x233) |
784 |
#define SPR_IBAT6U (0x234) |
785 |
#define SPR_IBAT6L (0x235) |
786 |
#define SPR_IBAT7U (0x236) |
787 |
#define SPR_IBAT7L (0x237) |
788 |
#define SPR_DBAT4U (0x238) |
789 |
#define SPR_DBAT4L (0x239) |
790 |
#define SPR_DBAT5U (0x23A) |
791 |
#define SPR_DBAT5L (0x23B) |
792 |
#define SPR_DBAT6U (0x23C) |
793 |
#define SPR_DBAT6L (0x23D) |
794 |
#define SPR_DBAT7U (0x23E) |
795 |
#define SPR_DBAT7L (0x23F) |
796 |
#define SPR_440_INV0 (0x370) |
797 |
#define SPR_440_INV1 (0x371) |
798 |
#define SPR_440_INV2 (0x372) |
799 |
#define SPR_440_INV3 (0x373) |
800 |
#define SPR_440_IVT0 (0x374) |
801 |
#define SPR_440_IVT1 (0x375) |
802 |
#define SPR_440_IVT2 (0x376) |
803 |
#define SPR_440_IVT3 (0x377) |
804 |
#define SPR_440_DNV0 (0x390) |
805 |
#define SPR_440_DNV1 (0x391) |
806 |
#define SPR_440_DNV2 (0x392) |
807 |
#define SPR_440_DNV3 (0x393) |
808 |
#define SPR_440_DVT0 (0x394) |
809 |
#define SPR_440_DVT1 (0x395) |
810 |
#define SPR_440_DVT2 (0x396) |
811 |
#define SPR_440_DVT3 (0x397) |
812 |
#define SPR_440_DVLIM (0x398) |
813 |
#define SPR_440_IVLIM (0x399) |
814 |
#define SPR_440_RSTCFG (0x39B) |
815 |
#define SPR_440_DCBTRL (0x39C) |
816 |
#define SPR_440_DCBTRH (0x39D) |
817 |
#define SPR_440_ICBTRL (0x39E) |
818 |
#define SPR_440_ICBTRH (0x39F) |
819 |
#define SPR_UMMCR0 (0x3A8) |
820 |
#define SPR_UPMC1 (0x3A9) |
821 |
#define SPR_UPMC2 (0x3AA) |
822 |
#define SPR_USIA (0x3AB) |
823 |
#define SPR_UMMCR1 (0x3AC) |
824 |
#define SPR_UPMC3 (0x3AD) |
825 |
#define SPR_UPMC4 (0x3AE) |
826 |
#define SPR_USDA (0x3AF) |
827 |
#define SPR_40x_ZPR (0x3B0) |
828 |
#define SPR_40x_PID (0x3B1) |
829 |
#define SPR_440_MMUCR (0x3B2) |
830 |
#define SPR_4xx_CCR0 (0x3B3) |
831 |
#define SPR_405_IAC3 (0x3B4) |
832 |
#define SPR_405_IAC4 (0x3B5) |
833 |
#define SPR_405_DVC1 (0x3B6) |
834 |
#define SPR_405_DVC2 (0x3B7) |
835 |
#define SPR_MMCR0 (0x3B8) |
836 |
#define SPR_PMC1 (0x3B9) |
837 |
#define SPR_40x_SGR (0x3B9) |
838 |
#define SPR_PMC2 (0x3BA) |
839 |
#define SPR_40x_DCWR (0x3BA) |
840 |
#define SPR_SIA (0x3BB) |
841 |
#define SPR_405_SLER (0x3BB) |
842 |
#define SPR_MMCR1 (0x3BC) |
843 |
#define SPR_405_SU0R (0x3BC) |
844 |
#define SPR_PMC3 (0x3BD) |
845 |
#define SPR_405_DBCR1 (0x3BD) |
846 |
#define SPR_PMC4 (0x3BE) |
847 |
#define SPR_SDA (0x3BF) |
848 |
#define SPR_403_VTBL (0x3CC) |
849 |
#define SPR_403_VTBU (0x3CD) |
850 |
#define SPR_DMISS (0x3D0) |
851 |
#define SPR_DCMP (0x3D1) |
852 |
#define SPR_DHASH1 (0x3D2) |
853 |
#define SPR_DHASH2 (0x3D3) |
854 |
#define SPR_4xx_ICDBDR (0x3D3) |
855 |
#define SPR_IMISS (0x3D4) |
856 |
#define SPR_40x_ESR (0x3D4) |
857 |
#define SPR_ICMP (0x3D5) |
858 |
#define SPR_40x_DEAR (0x3D5) |
859 |
#define SPR_RPA (0x3D6) |
860 |
#define SPR_40x_EVPR (0x3D6) |
861 |
#define SPR_403_CDBCR (0x3D7) |
862 |
#define SPR_TCR (0x3D8) |
863 |
#define SPR_40x_TSR (0x3D8) |
864 |
#define SPR_IBR (0x3DA) |
865 |
#define SPR_40x_TCR (0x3DA) |
866 |
#define SPR_ESASR (0x3DB) |
867 |
#define SPR_40x_PIT (0x3DB) |
868 |
#define SPR_403_TBL (0x3DC) |
869 |
#define SPR_403_TBU (0x3DD) |
870 |
#define SPR_SEBR (0x3DE) |
871 |
#define SPR_40x_SRR2 (0x3DE) |
872 |
#define SPR_SER (0x3DF) |
873 |
#define SPR_40x_SRR3 (0x3DF) |
874 |
#define SPR_HID0 (0x3F0) |
875 |
#define SPR_40x_DBSR (0x3F0) |
876 |
#define SPR_HID1 (0x3F1) |
877 |
#define SPR_IABR (0x3F2) |
878 |
#define SPR_40x_DBCR0 (0x3F2) |
879 |
#define SPR_601_HID2 (0x3F2) |
880 |
#define SPR_HID2 (0x3F3) |
881 |
#define SPR_440_DBDR (0x3F3) |
882 |
#define SPR_40x_IAC1 (0x3F4) |
883 |
#define SPR_DABR (0x3F5) |
884 |
#define DABR_MASK (~(target_ulong)0x7) |
885 |
#define SPR_40x_IAC2 (0x3F5) |
886 |
#define SPR_601_HID5 (0x3F5) |
887 |
#define SPR_40x_DAC1 (0x3F6) |
888 |
#define SPR_40x_DAC2 (0x3F7) |
889 |
#define SPR_L2PM (0x3F8) |
890 |
#define SPR_750_HID2 (0x3F8) |
891 |
#define SPR_L2CR (0x3F9) |
892 |
#define SPR_IABR2 (0x3FA) |
893 |
#define SPR_40x_DCCR (0x3FA) |
894 |
#define SPR_ICTC (0x3FB) |
895 |
#define SPR_40x_ICCR (0x3FB) |
896 |
#define SPR_THRM1 (0x3FC) |
897 |
#define SPR_403_PBL1 (0x3FC) |
898 |
#define SPR_SP (0x3FD) |
899 |
#define SPR_THRM2 (0x3FD) |
900 |
#define SPR_403_PBU1 (0x3FD) |
901 |
#define SPR_LT (0x3FE) |
902 |
#define SPR_THRM3 (0x3FE) |
903 |
#define SPR_FPECR (0x3FE) |
904 |
#define SPR_403_PBL2 (0x3FE) |
905 |
#define SPR_PIR (0x3FF) |
906 |
#define SPR_403_PBU2 (0x3FF) |
907 |
#define SPR_601_HID15 (0x3FF) |
908 |
|
909 |
/* Memory access type :
|
910 |
* may be needed for precise access rights control and precise exceptions.
|
911 |
*/
|
912 |
enum {
|
913 |
/* 1 bit to define user level / supervisor access */
|
914 |
ACCESS_USER = 0x00,
|
915 |
ACCESS_SUPER = 0x01,
|
916 |
/* Type of instruction that generated the access */
|
917 |
ACCESS_CODE = 0x10, /* Code fetch access */ |
918 |
ACCESS_INT = 0x20, /* Integer load/store access */ |
919 |
ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
920 |
ACCESS_RES = 0x40, /* load/store with reservation */ |
921 |
ACCESS_EXT = 0x50, /* external access */ |
922 |
ACCESS_CACHE = 0x60, /* Cache manipulation */ |
923 |
}; |
924 |
|
925 |
/*****************************************************************************/
|
926 |
/* Exceptions */
|
927 |
enum {
|
928 |
EXCP_NONE = -1,
|
929 |
/* PowerPC hardware exceptions : exception vector / 0x100 */
|
930 |
EXCP_RESET = 0x01, /* System reset */ |
931 |
EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */ |
932 |
EXCP_DSI = 0x03, /* Impossible memory access */ |
933 |
EXCP_ISI = 0x04, /* Impossible instruction fetch */ |
934 |
EXCP_EXTERNAL = 0x05, /* External interruption */ |
935 |
EXCP_ALIGN = 0x06, /* Alignment exception */ |
936 |
EXCP_PROGRAM = 0x07, /* Program exception */ |
937 |
EXCP_NO_FP = 0x08, /* No floating point */ |
938 |
EXCP_DECR = 0x09, /* Decrementer exception */ |
939 |
EXCP_RESA = 0x0A, /* Implementation specific */ |
940 |
EXCP_RESB = 0x0B, /* Implementation specific */ |
941 |
EXCP_SYSCALL = 0x0C, /* System call */ |
942 |
EXCP_TRACE = 0x0D, /* Trace exception (optional) */ |
943 |
EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */ |
944 |
/* MPC740/745/750 & IBM 750 */
|
945 |
EXCP_PERF = 0x0F, /* Performance monitor */ |
946 |
EXCP_IABR = 0x13, /* Instruction address breakpoint */ |
947 |
EXCP_SMI = 0x14, /* System management interrupt */ |
948 |
EXCP_THRM = 0x15, /* Thermal management interrupt */ |
949 |
/* MPC755 */
|
950 |
EXCP_TLBMISS = 0x10, /* Instruction TLB miss */ |
951 |
EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */ |
952 |
EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */ |
953 |
EXCP_PPC_MAX = 0x16,
|
954 |
/* Qemu exception */
|
955 |
EXCP_OFCALL = 0x20, /* Call open-firmware emulator */ |
956 |
EXCP_RTASCALL = 0x21, /* Call RTAS emulator */ |
957 |
/* Special cases where we want to stop translation */
|
958 |
EXCP_MTMSR = 0x104, /* mtmsr instruction: */ |
959 |
/* may change privilege level */
|
960 |
EXCP_BRANCH = 0x108, /* branch instruction */ |
961 |
EXCP_RFI = 0x10C, /* return from interrupt */ |
962 |
EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ |
963 |
}; |
964 |
/* Error codes */
|
965 |
enum {
|
966 |
/* Exception subtypes for EXCP_DSI */
|
967 |
EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */ |
968 |
EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */ |
969 |
EXCP_DSI_PROT = 0x03, /* Memory protection violation */ |
970 |
EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */ |
971 |
EXCP_DSI_DABR = 0x05, /* Data address breakpoint */ |
972 |
/* flags for EXCP_DSI */
|
973 |
EXCP_DSI_DIRECT = 0x10,
|
974 |
EXCP_DSI_STORE = 0x20,
|
975 |
EXCP_DSI_ECXW = 0x40,
|
976 |
/* Exception subtypes for EXCP_ISI */
|
977 |
EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */ |
978 |
EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */ |
979 |
EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */ |
980 |
EXCP_ISI_PROT = 0x04, /* Memory protection violation */ |
981 |
EXCP_ISI_DIRECT = 0x05, /* Trying to fetch from * |
982 |
* a direct store segment */
|
983 |
/* Exception subtypes for EXCP_ALIGN */
|
984 |
EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
985 |
EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
986 |
EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
987 |
EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
988 |
EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
989 |
EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
990 |
/* Exception subtypes for EXCP_PROGRAM */
|
991 |
/* FP exceptions */
|
992 |
EXCP_FP = 0x10,
|
993 |
EXCP_FP_OX = 0x01, /* FP overflow */ |
994 |
EXCP_FP_UX = 0x02, /* FP underflow */ |
995 |
EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
996 |
EXCP_FP_XX = 0x04, /* FP inexact */ |
997 |
EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
998 |
EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */ |
999 |
EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
1000 |
EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
1001 |
EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
1002 |
EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
1003 |
EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
1004 |
EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
1005 |
EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
1006 |
/* Invalid instruction */
|
1007 |
EXCP_INVAL = 0x20,
|
1008 |
EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
1009 |
EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
1010 |
EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
1011 |
EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
1012 |
/* Privileged instruction */
|
1013 |
EXCP_PRIV = 0x30,
|
1014 |
EXCP_PRIV_OPC = 0x01,
|
1015 |
EXCP_PRIV_REG = 0x02,
|
1016 |
/* Trap */
|
1017 |
EXCP_TRAP = 0x40,
|
1018 |
}; |
1019 |
|
1020 |
/*****************************************************************************/
|
1021 |
|
1022 |
#endif /* !defined (__CPU_PPC_H__) */ |