Revision 405ee3ad

b/target-arm/helper.c
704 704 
        break;
705 705 
    case 3: /* MMU Domain access control / MPU write buffer control.  */
706 706 
        env->cp15.c3 = val;
707 
        tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
707 708 
        break;
708 709 
    case 4: /* Reserved.  */
709 710 
        goto bad_reg;
......
814 815 
    case 13: /* Process ID.  */
815 816 
        switch (op2) {
816 817 
        case 0:
817 
            if (!arm_feature(env, ARM_FEATURE_MPU))
818 
                goto bad_reg;
819 818 
            /* Unlike real hardware the qemu TLB uses virtual addresses,
820 819 
               not modified virtual addresses, so this causes a TLB flush.
821 820 
             */

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