Revision 409570a7 hw/ide/cmd646.c

b/hw/ide/cmd646.c
206 206
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
207 207
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
208 208

  
209
    pci_conf[0x08] = 0x07; // IDE controller revision
210
    pci_conf[0x09] = 0x8f;
209
    pci_conf[PCI_REVISION_ID] = 0x07; // IDE controller revision
210
    pci_conf[PCI_CLASS_PROG] = 0x8f;
211 211

  
212 212
    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
213 213
    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
......
224 224
    pci_register_bar(dev, 3, 0x4, PCI_BASE_ADDRESS_SPACE_IO, ide_map);
225 225
    pci_register_bar(dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
226 226

  
227
    pci_conf[0x3d] = 0x01; // interrupt on pin 1
227
    /* TODO: RST# value should be 0 */
228
    pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
228 229

  
229 230
    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
230 231
    ide_bus_new(&d->bus[0], &d->dev.qdev);

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