Revision 40ac17cd
| b/hw/hpet.c | ||
|---|---|---|
| 71 | 71 |
uint64_t config; /* configuration */ |
| 72 | 72 |
uint64_t isr; /* interrupt status reg */ |
| 73 | 73 |
uint64_t hpet_counter; /* main counter */ |
| 74 |
uint8_t hpet_id; /* instance id */ |
|
| 74 | 75 |
} HPETState; |
| 75 | 76 |
|
| 77 |
struct hpet_fw_config hpet_cfg = {.count = ~0};
|
|
| 78 |
|
|
| 76 | 79 |
static uint32_t hpet_in_legacy_mode(HPETState *s) |
| 77 | 80 |
{
|
| 78 | 81 |
return s->config & HPET_CFG_LEGACY; |
| ... | ... | |
| 228 | 231 |
/* Push number of timers into capability returned via HPET_ID */ |
| 229 | 232 |
s->capability &= ~HPET_ID_NUM_TIM_MASK; |
| 230 | 233 |
s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; |
| 234 |
hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
|
| 231 | 235 |
|
| 232 | 236 |
/* Derive HPET_MSI_SUPPORT from the capability of the first timer. */ |
| 233 | 237 |
s->flags &= ~(1 << HPET_MSI_SUPPORT); |
| ... | ... | |
| 657 | 661 |
*/ |
| 658 | 662 |
hpet_pit_enable(); |
| 659 | 663 |
} |
| 664 |
hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
|
| 665 |
hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr; |
|
| 660 | 666 |
count = 1; |
| 661 | 667 |
} |
| 662 | 668 |
|
| ... | ... | |
| 676 | 682 |
int i, iomemtype; |
| 677 | 683 |
HPETTimer *timer; |
| 678 | 684 |
|
| 685 |
if (hpet_cfg.count == ~0) /* first instance */ |
|
| 686 |
hpet_cfg.count = 0; |
|
| 687 |
|
|
| 688 |
if (hpet_cfg.count == 8) {
|
|
| 689 |
fprintf(stderr, "Only 8 instances of HPET is allowed\n"); |
|
| 690 |
return -1; |
|
| 691 |
} |
|
| 692 |
|
|
| 693 |
s->hpet_id = hpet_cfg.count++; |
|
| 694 |
|
|
| 679 | 695 |
for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
|
| 680 | 696 |
sysbus_init_irq(dev, &s->irqs[i]); |
| 681 | 697 |
} |
| b/hw/hpet_emul.h | ||
|---|---|---|
| 53 | 53 |
#define HPET_TN_INT_ROUTE_CAP_SHIFT 32 |
| 54 | 54 |
#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U |
| 55 | 55 |
|
| 56 |
struct hpet_fw_entry |
|
| 57 |
{
|
|
| 58 |
uint32_t event_timer_block_id; |
|
| 59 |
uint64_t address; |
|
| 60 |
uint16_t min_tick; |
|
| 61 |
uint8_t page_prot; |
|
| 62 |
} __attribute__ ((packed)); |
|
| 63 |
|
|
| 64 |
struct hpet_fw_config |
|
| 65 |
{
|
|
| 66 |
uint8_t count; |
|
| 67 |
struct hpet_fw_entry hpet[8]; |
|
| 68 |
} __attribute__ ((packed)); |
|
| 69 |
|
|
| 70 |
extern struct hpet_fw_config hpet_cfg; |
|
| 56 | 71 |
#endif |
| b/hw/pc.c | ||
|---|---|---|
| 62 | 62 |
#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
| 63 | 63 |
#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
| 64 | 64 |
#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
| 65 |
#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
|
| 65 | 66 |
|
| 66 | 67 |
#define E820_NR_ENTRIES 16 |
| 67 | 68 |
|
| ... | ... | |
| 485 | 486 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
| 486 | 487 |
sizeof(struct e820_table)); |
| 487 | 488 |
|
| 489 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, |
|
| 490 |
sizeof(struct hpet_fw_config)); |
|
| 488 | 491 |
/* allocate memory for the NUMA channel: one (64bit) word for the number |
| 489 | 492 |
* of nodes, one word for each VCPU->node and one word for each node to |
| 490 | 493 |
* hold the amount of memory. |
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