Revision 40ac17cd hw/hpet.c
| b/hw/hpet.c | ||
|---|---|---|
| 71 | 71 |
uint64_t config; /* configuration */ |
| 72 | 72 |
uint64_t isr; /* interrupt status reg */ |
| 73 | 73 |
uint64_t hpet_counter; /* main counter */ |
| 74 |
uint8_t hpet_id; /* instance id */ |
|
| 74 | 75 |
} HPETState; |
| 75 | 76 |
|
| 77 |
struct hpet_fw_config hpet_cfg = {.count = ~0};
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|
| 78 |
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|
| 76 | 79 |
static uint32_t hpet_in_legacy_mode(HPETState *s) |
| 77 | 80 |
{
|
| 78 | 81 |
return s->config & HPET_CFG_LEGACY; |
| ... | ... | |
| 228 | 231 |
/* Push number of timers into capability returned via HPET_ID */ |
| 229 | 232 |
s->capability &= ~HPET_ID_NUM_TIM_MASK; |
| 230 | 233 |
s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; |
| 234 |
hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
|
| 231 | 235 |
|
| 232 | 236 |
/* Derive HPET_MSI_SUPPORT from the capability of the first timer. */ |
| 233 | 237 |
s->flags &= ~(1 << HPET_MSI_SUPPORT); |
| ... | ... | |
| 657 | 661 |
*/ |
| 658 | 662 |
hpet_pit_enable(); |
| 659 | 663 |
} |
| 664 |
hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
|
| 665 |
hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr; |
|
| 660 | 666 |
count = 1; |
| 661 | 667 |
} |
| 662 | 668 |
|
| ... | ... | |
| 676 | 682 |
int i, iomemtype; |
| 677 | 683 |
HPETTimer *timer; |
| 678 | 684 |
|
| 685 |
if (hpet_cfg.count == ~0) /* first instance */ |
|
| 686 |
hpet_cfg.count = 0; |
|
| 687 |
|
|
| 688 |
if (hpet_cfg.count == 8) {
|
|
| 689 |
fprintf(stderr, "Only 8 instances of HPET is allowed\n"); |
|
| 690 |
return -1; |
|
| 691 |
} |
|
| 692 |
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|
| 693 |
s->hpet_id = hpet_cfg.count++; |
|
| 694 |
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|
| 679 | 695 |
for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
|
| 680 | 696 |
sysbus_init_irq(dev, &s->irqs[i]); |
| 681 | 697 |
} |
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