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/*
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   SPARC micro operations
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   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   This library is free software; you can redistribute it and/or
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   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
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   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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*/
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#include "exec.h"
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 /*XXX*/
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#define REGNAME g0
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#define REG (env->gregs[0])
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#include "op_template.h"
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#define REGNAME g1
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#define REG (env->gregs[1])
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#include "op_template.h"
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#define REGNAME g2
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#define REG (env->gregs[2])
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#include "op_template.h"
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#define REGNAME g3
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#define REG (env->gregs[3])
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#include "op_template.h"
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#define REGNAME g4
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#define REG (env->gregs[4])
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#include "op_template.h"
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#define REGNAME g5
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#define REG (env->gregs[5])
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#include "op_template.h"
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#define REGNAME g6
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#define REG (env->gregs[6])
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#include "op_template.h"
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#define REGNAME g7
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#define REG (env->gregs[7])
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#include "op_template.h"
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#define REGNAME i0
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#define REG (REGWPTR[16])
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#include "op_template.h"
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#define REGNAME i1
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#define REG (REGWPTR[17])
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#include "op_template.h"
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#define REGNAME i2
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#define REG (REGWPTR[18])
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#include "op_template.h"
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#define REGNAME i3
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#define REG (REGWPTR[19])
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#include "op_template.h"
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#define REGNAME i4
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#define REG (REGWPTR[20])
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#include "op_template.h"
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#define REGNAME i5
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#define REG (REGWPTR[21])
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#include "op_template.h"
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#define REGNAME i6
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#define REG (REGWPTR[22])
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#include "op_template.h"
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#define REGNAME i7
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#define REG (REGWPTR[23])
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#include "op_template.h"
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#define REGNAME l0
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#define REG (REGWPTR[8])
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#include "op_template.h"
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#define REGNAME l1
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#define REG (REGWPTR[9])
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#include "op_template.h"
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#define REGNAME l2
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#define REG (REGWPTR[10])
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#include "op_template.h"
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#define REGNAME l3
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#define REG (REGWPTR[11])
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#include "op_template.h"
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#define REGNAME l4
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#define REG (REGWPTR[12])
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#include "op_template.h"
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#define REGNAME l5
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#define REG (REGWPTR[13])
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#include "op_template.h"
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#define REGNAME l6
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#define REG (REGWPTR[14])
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#include "op_template.h"
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#define REGNAME l7
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#define REG (REGWPTR[15])
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#include "op_template.h"
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#define REGNAME o0
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#define REG (REGWPTR[0])
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#include "op_template.h"
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#define REGNAME o1
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#define REG (REGWPTR[1])
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#include "op_template.h"
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#define REGNAME o2
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#define REG (REGWPTR[2])
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#include "op_template.h"
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#define REGNAME o3
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#define REG (REGWPTR[3])
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#include "op_template.h"
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#define REGNAME o4
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#define REG (REGWPTR[4])
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#include "op_template.h"
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#define REGNAME o5
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#define REG (REGWPTR[5])
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#include "op_template.h"
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#define REGNAME o6
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#define REG (REGWPTR[6])
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#include "op_template.h"
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#define REGNAME o7
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#define REG (REGWPTR[7])
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#include "op_template.h"
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#define REGNAME f0
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#define REG (env->fpr[0])
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#include "fop_template.h"
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#define REGNAME f1
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#define REG (env->fpr[1])
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#include "fop_template.h"
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#define REGNAME f2
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#define REG (env->fpr[2])
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#include "fop_template.h"
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#define REGNAME f3
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#define REG (env->fpr[3])
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#include "fop_template.h"
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#define REGNAME f4
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#define REG (env->fpr[4])
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#include "fop_template.h"
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#define REGNAME f5
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#define REG (env->fpr[5])
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#include "fop_template.h"
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#define REGNAME f6
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#define REG (env->fpr[6])
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#include "fop_template.h"
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#define REGNAME f7
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#define REG (env->fpr[7])
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#include "fop_template.h"
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#define REGNAME f8
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#define REG (env->fpr[8])
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#include "fop_template.h"
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#define REGNAME f9
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#define REG (env->fpr[9])
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#include "fop_template.h"
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#define REGNAME f10
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#define REG (env->fpr[10])
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#include "fop_template.h"
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#define REGNAME f11
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#define REG (env->fpr[11])
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#include "fop_template.h"
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#define REGNAME f12
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#define REG (env->fpr[12])
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#include "fop_template.h"
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#define REGNAME f13
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#define REG (env->fpr[13])
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#include "fop_template.h"
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#define REGNAME f14
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#define REG (env->fpr[14])
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#include "fop_template.h"
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#define REGNAME f15
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#define REG (env->fpr[15])
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#include "fop_template.h"
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#define REGNAME f16
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#define REG (env->fpr[16])
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#include "fop_template.h"
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#define REGNAME f17
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#define REG (env->fpr[17])
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#include "fop_template.h"
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#define REGNAME f18
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#define REG (env->fpr[18])
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#include "fop_template.h"
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#define REGNAME f19
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#define REG (env->fpr[19])
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#include "fop_template.h"
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#define REGNAME f20
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#define REG (env->fpr[20])
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#include "fop_template.h"
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#define REGNAME f21
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#define REG (env->fpr[21])
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#include "fop_template.h"
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#define REGNAME f22
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#define REG (env->fpr[22])
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#include "fop_template.h"
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#define REGNAME f23
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#define REG (env->fpr[23])
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#include "fop_template.h"
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#define REGNAME f24
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#define REG (env->fpr[24])
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#include "fop_template.h"
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#define REGNAME f25
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#define REG (env->fpr[25])
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#include "fop_template.h"
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#define REGNAME f26
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#define REG (env->fpr[26])
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#include "fop_template.h"
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#define REGNAME f27
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#define REG (env->fpr[27])
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#include "fop_template.h"
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#define REGNAME f28
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#define REG (env->fpr[28])
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#include "fop_template.h"
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#define REGNAME f29
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#define REG (env->fpr[29])
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#include "fop_template.h"
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#define REGNAME f30
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#define REG (env->fpr[30])
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#include "fop_template.h"
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#define REGNAME f31
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#define REG (env->fpr[31])
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#include "fop_template.h"
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#ifdef TARGET_SPARC64
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#define REGNAME f32
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#define REG (env->fpr[32])
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#include "fop_template.h"
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#define REGNAME f34
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#define REG (env->fpr[34])
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#include "fop_template.h"
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#define REGNAME f36
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#define REG (env->fpr[36])
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#include "fop_template.h"
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#define REGNAME f38
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#define REG (env->fpr[38])
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#include "fop_template.h"
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#define REGNAME f40
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#define REG (env->fpr[40])
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#include "fop_template.h"
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#define REGNAME f42
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#define REG (env->fpr[42])
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#include "fop_template.h"
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#define REGNAME f44
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#define REG (env->fpr[44])
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#include "fop_template.h"
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#define REGNAME f46
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#define REG (env->fpr[46])
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#include "fop_template.h"
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#define REGNAME f48
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#define REG (env->fpr[47])
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#include "fop_template.h"
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#define REGNAME f50
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#define REG (env->fpr[50])
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#include "fop_template.h"
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#define REGNAME f52
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#define REG (env->fpr[52])
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#include "fop_template.h"
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#define REGNAME f54
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#define REG (env->fpr[54])
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#include "fop_template.h"
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#define REGNAME f56
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#define REG (env->fpr[56])
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#include "fop_template.h"
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#define REGNAME f58
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#define REG (env->fpr[58])
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#include "fop_template.h"
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#define REGNAME f60
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#define REG (env->fpr[60])
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#include "fop_template.h"
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#define REGNAME f62
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#define REG (env->fpr[62])
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#include "fop_template.h"
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#endif
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#ifdef TARGET_SPARC64
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#ifdef WORDS_BIGENDIAN
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typedef union UREG64 {
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    struct { uint16_t v3, v2, v1, v0; } w;
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    struct { uint32_t v1, v0; } l;
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    uint64_t q;
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} UREG64;
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#else
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typedef union UREG64 {
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    struct { uint16_t v0, v1, v2, v3; } w;
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    struct { uint32_t v0, v1; } l;
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    uint64_t q;
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} UREG64;
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#endif
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#define PARAMQ1 \
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({\
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    UREG64 __p;\
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    __p.l.v1 = PARAM1;\
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    __p.l.v0 = PARAM2;\
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    __p.q;\
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}) 
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void OPPROTO op_movq_T0_im64(void)
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{
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    T0 = PARAMQ1;
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}
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void OPPROTO op_movq_T1_im64(void)
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{
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    T1 = PARAMQ1;
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}
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#define XFLAG_SET(x) ((env->xcc&x)?1:0)
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#else
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#define EIP (env->pc)
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#endif
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#define FLAG_SET(x) ((env->psr&x)?1:0)
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void OPPROTO op_movl_T0_0(void)
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{
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    T0 = 0;
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}
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void OPPROTO op_movl_T0_im(void)
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{
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    T0 = (uint32_t)PARAM1;
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}
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void OPPROTO op_movl_T1_im(void)
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{
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    T1 = (uint32_t)PARAM1;
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}
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void OPPROTO op_movl_T2_im(void)
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{
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    T2 = (uint32_t)PARAM1;
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}
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void OPPROTO op_movl_T0_sim(void)
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{
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    T0 = (int32_t)PARAM1;
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}
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void OPPROTO op_movl_T1_sim(void)
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{
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    T1 = (int32_t)PARAM1;
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}
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void OPPROTO op_movl_T2_sim(void)
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{
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    T2 = (int32_t)PARAM1;
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}
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void OPPROTO op_movl_T0_env(void)
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{
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    T0 = *(uint32_t *)((char *)env + PARAM1);
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}
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void OPPROTO op_movl_env_T0(void)
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{
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    *(uint32_t *)((char *)env + PARAM1) = T0;
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}
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void OPPROTO op_movtl_T0_env(void)
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{
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    T0 = *(target_ulong *)((char *)env + PARAM1);
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}
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void OPPROTO op_movtl_env_T0(void)
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{
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    *(target_ulong *)((char *)env + PARAM1) = T0;
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}
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void OPPROTO op_add_T1_T0(void)
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{
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    T0 += T1;
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}
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void OPPROTO op_add_T1_T0_cc(void)
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{
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    target_ulong src1;
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    src1 = T0;
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    T0 += T1;
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    env->psr = 0;
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#ifdef TARGET_SPARC64
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    if (!(T0 & 0xffffffff))
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        env->psr |= PSR_ZERO;
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    if ((int32_t) T0 < 0)
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        env->psr |= PSR_NEG;
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    if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
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        env->psr |= PSR_CARRY;
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    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
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         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
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        env->psr |= PSR_OVF;
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    env->xcc = 0;
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    if (!T0)
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        env->xcc |= PSR_ZERO;
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    if ((int64_t) T0 < 0)
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        env->xcc |= PSR_NEG;
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    if (T0 < src1)
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        env->xcc |= PSR_CARRY;
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    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
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        env->xcc |= PSR_OVF;
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#else
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    if (!T0)
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        env->psr |= PSR_ZERO;
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    if ((int32_t) T0 < 0)
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        env->psr |= PSR_NEG;
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    if (T0 < src1)
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        env->psr |= PSR_CARRY;
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    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
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        env->psr |= PSR_OVF;
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#endif
407 af7bf89b bellard
    FORCE_RET();
408 7a3f1944 bellard
}
409 7a3f1944 bellard
410 af7bf89b bellard
void OPPROTO op_addx_T1_T0(void)
411 7a3f1944 bellard
{
412 af7bf89b bellard
    T0 += T1 + FLAG_SET(PSR_CARRY);
413 7a3f1944 bellard
}
414 7a3f1944 bellard
415 af7bf89b bellard
void OPPROTO op_addx_T1_T0_cc(void)
416 7a3f1944 bellard
{
417 af7bf89b bellard
    target_ulong src1;
418 cf495bcf bellard
    src1 = T0;
419 b854608e bellard
    if (FLAG_SET(PSR_CARRY))
420 b854608e bellard
    {
421 b854608e bellard
      T0 += T1 + 1;
422 b854608e bellard
      env->psr = 0;
423 b854608e bellard
#ifdef TARGET_SPARC64
424 b854608e bellard
      if ((T0 & 0xffffffff) <= (src1 & 0xffffffff))
425 b854608e bellard
        env->psr |= PSR_CARRY;
426 b854608e bellard
      env->xcc = 0;
427 b854608e bellard
      if (T0 <= src1)
428 b854608e bellard
        env->xcc |= PSR_CARRY;
429 b854608e bellard
#else
430 b854608e bellard
      if (T0 <= src1)
431 b854608e bellard
        env->psr |= PSR_CARRY;
432 b854608e bellard
#endif
433 b854608e bellard
    }
434 b854608e bellard
    else
435 b854608e bellard
    {
436 b854608e bellard
      T0 += T1;
437 b854608e bellard
      env->psr = 0;
438 b854608e bellard
#ifdef TARGET_SPARC64
439 b854608e bellard
      if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
440 b854608e bellard
        env->psr |= PSR_CARRY;
441 b854608e bellard
      env->xcc = 0;
442 b854608e bellard
      if (T0 < src1)
443 b854608e bellard
        env->xcc |= PSR_CARRY;
444 b854608e bellard
#else
445 b854608e bellard
      if (T0 < src1)
446 b854608e bellard
        env->psr |= PSR_CARRY;
447 b854608e bellard
#endif
448 b854608e bellard
    }
449 3475187d bellard
#ifdef TARGET_SPARC64
450 3475187d bellard
    if (!(T0 & 0xffffffff))
451 3475187d bellard
        env->psr |= PSR_ZERO;
452 3475187d bellard
    if ((int32_t) T0 < 0)
453 3475187d bellard
        env->psr |= PSR_NEG;
454 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
455 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
456 3475187d bellard
        env->psr |= PSR_OVF;
457 3475187d bellard
458 3475187d bellard
    if (!T0)
459 3475187d bellard
        env->xcc |= PSR_ZERO;
460 3475187d bellard
    if ((int64_t) T0 < 0)
461 3475187d bellard
        env->xcc |= PSR_NEG;
462 3475187d bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
463 3475187d bellard
        env->xcc |= PSR_OVF;
464 3475187d bellard
#else
465 cf495bcf bellard
    if (!T0)
466 cf495bcf bellard
        env->psr |= PSR_ZERO;
467 af7bf89b bellard
    if ((int32_t) T0 < 0)
468 cf495bcf bellard
        env->psr |= PSR_NEG;
469 cf495bcf bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
470 cf495bcf bellard
        env->psr |= PSR_OVF;
471 3475187d bellard
#endif
472 cf495bcf bellard
    FORCE_RET();
473 7a3f1944 bellard
}
474 7a3f1944 bellard
475 e32f879d blueswir1
void OPPROTO op_tadd_T1_T0_cc(void)
476 e32f879d blueswir1
{
477 e32f879d blueswir1
    target_ulong src1;
478 e32f879d blueswir1
479 e32f879d blueswir1
    src1 = T0;
480 e32f879d blueswir1
    T0 += T1;
481 e32f879d blueswir1
    env->psr = 0;
482 e32f879d blueswir1
#ifdef TARGET_SPARC64
483 e32f879d blueswir1
    if (!(T0 & 0xffffffff))
484 e32f879d blueswir1
        env->psr |= PSR_ZERO;
485 e32f879d blueswir1
    if ((int32_t) T0 < 0)
486 e32f879d blueswir1
        env->psr |= PSR_NEG;
487 e32f879d blueswir1
    if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
488 e32f879d blueswir1
        env->psr |= PSR_CARRY;
489 e32f879d blueswir1
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
490 e32f879d blueswir1
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
491 e32f879d blueswir1
        env->psr |= PSR_OVF;
492 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
493 e32f879d blueswir1
        env->psr |= PSR_OVF;
494 e32f879d blueswir1
495 e32f879d blueswir1
    env->xcc = 0;
496 e32f879d blueswir1
    if (!T0)
497 e32f879d blueswir1
        env->xcc |= PSR_ZERO;
498 e32f879d blueswir1
    if ((int64_t) T0 < 0)
499 e32f879d blueswir1
        env->xcc |= PSR_NEG;
500 e32f879d blueswir1
    if (T0 < src1)
501 e32f879d blueswir1
        env->xcc |= PSR_CARRY;
502 e32f879d blueswir1
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
503 e32f879d blueswir1
        env->xcc |= PSR_OVF;
504 e32f879d blueswir1
#else
505 e32f879d blueswir1
    if (!T0)
506 e32f879d blueswir1
        env->psr |= PSR_ZERO;
507 e32f879d blueswir1
    if ((int32_t) T0 < 0)
508 e32f879d blueswir1
        env->psr |= PSR_NEG;
509 e32f879d blueswir1
    if (T0 < src1)
510 e32f879d blueswir1
        env->psr |= PSR_CARRY;
511 e32f879d blueswir1
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
512 e32f879d blueswir1
        env->psr |= PSR_OVF;
513 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
514 e32f879d blueswir1
        env->psr |= PSR_OVF;
515 e32f879d blueswir1
#endif
516 e32f879d blueswir1
    FORCE_RET();
517 e32f879d blueswir1
}
518 e32f879d blueswir1
519 e32f879d blueswir1
void OPPROTO op_tadd_T1_T0_ccTV(void)
520 e32f879d blueswir1
{
521 e32f879d blueswir1
    target_ulong src1;
522 e32f879d blueswir1
523 e32f879d blueswir1
    if ((T0 & 0x03) || (T1 & 0x03))
524 e32f879d blueswir1
        raise_exception(TT_TOVF);
525 e32f879d blueswir1
526 e32f879d blueswir1
    src1 = T0;
527 e32f879d blueswir1
    T0 += T1;
528 e32f879d blueswir1
529 e32f879d blueswir1
#ifdef TARGET_SPARC64
530 e32f879d blueswir1
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
531 e32f879d blueswir1
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
532 e32f879d blueswir1
        raise_exception(TT_TOVF);
533 e32f879d blueswir1
#else
534 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
535 e32f879d blueswir1
        raise_exception(TT_TOVF);
536 e32f879d blueswir1
#endif
537 e32f879d blueswir1
538 e32f879d blueswir1
    env->psr = 0;
539 e32f879d blueswir1
#ifdef TARGET_SPARC64
540 e32f879d blueswir1
    if (!(T0 & 0xffffffff))
541 e32f879d blueswir1
        env->psr |= PSR_ZERO;
542 e32f879d blueswir1
    if ((int32_t) T0 < 0)
543 e32f879d blueswir1
        env->psr |= PSR_NEG;
544 e32f879d blueswir1
    if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
545 e32f879d blueswir1
        env->psr |= PSR_CARRY;
546 e32f879d blueswir1
547 e32f879d blueswir1
    env->xcc = 0;
548 e32f879d blueswir1
    if (!T0)
549 e32f879d blueswir1
        env->xcc |= PSR_ZERO;
550 e32f879d blueswir1
    if ((int64_t) T0 < 0)
551 e32f879d blueswir1
        env->xcc |= PSR_NEG;
552 e32f879d blueswir1
    if (T0 < src1)
553 e32f879d blueswir1
        env->xcc |= PSR_CARRY;
554 e32f879d blueswir1
#else
555 e32f879d blueswir1
    if (!T0)
556 e32f879d blueswir1
        env->psr |= PSR_ZERO;
557 e32f879d blueswir1
    if ((int32_t) T0 < 0)
558 e32f879d blueswir1
        env->psr |= PSR_NEG;
559 e32f879d blueswir1
    if (T0 < src1)
560 e32f879d blueswir1
        env->psr |= PSR_CARRY;
561 e32f879d blueswir1
#endif
562 e32f879d blueswir1
    FORCE_RET();
563 e32f879d blueswir1
}
564 e32f879d blueswir1
565 cf495bcf bellard
void OPPROTO op_sub_T1_T0(void)
566 7a3f1944 bellard
{
567 cf495bcf bellard
    T0 -= T1;
568 7a3f1944 bellard
}
569 7a3f1944 bellard
570 cf495bcf bellard
void OPPROTO op_sub_T1_T0_cc(void)
571 7a3f1944 bellard
{
572 af7bf89b bellard
    target_ulong src1;
573 cf495bcf bellard
574 cf495bcf bellard
    src1 = T0;
575 cf495bcf bellard
    T0 -= T1;
576 cf495bcf bellard
    env->psr = 0;
577 3475187d bellard
#ifdef TARGET_SPARC64
578 3475187d bellard
    if (!(T0 & 0xffffffff))
579 3475187d bellard
        env->psr |= PSR_ZERO;
580 3475187d bellard
    if ((int32_t) T0 < 0)
581 3475187d bellard
        env->psr |= PSR_NEG;
582 83469015 bellard
    if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
583 3475187d bellard
        env->psr |= PSR_CARRY;
584 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
585 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
586 3475187d bellard
        env->psr |= PSR_OVF;
587 3475187d bellard
588 3475187d bellard
    env->xcc = 0;
589 3475187d bellard
    if (!T0)
590 3475187d bellard
        env->xcc |= PSR_ZERO;
591 3475187d bellard
    if ((int64_t) T0 < 0)
592 3475187d bellard
        env->xcc |= PSR_NEG;
593 bb3911a6 bellard
    if (src1 < T1)
594 3475187d bellard
        env->xcc |= PSR_CARRY;
595 3475187d bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
596 3475187d bellard
        env->xcc |= PSR_OVF;
597 3475187d bellard
#else
598 cf495bcf bellard
    if (!T0)
599 cf495bcf bellard
        env->psr |= PSR_ZERO;
600 af7bf89b bellard
    if ((int32_t) T0 < 0)
601 cf495bcf bellard
        env->psr |= PSR_NEG;
602 cf495bcf bellard
    if (src1 < T1)
603 cf495bcf bellard
        env->psr |= PSR_CARRY;
604 cf495bcf bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
605 cf495bcf bellard
        env->psr |= PSR_OVF;
606 3475187d bellard
#endif
607 af7bf89b bellard
    FORCE_RET();
608 af7bf89b bellard
}
609 af7bf89b bellard
610 af7bf89b bellard
void OPPROTO op_subx_T1_T0(void)
611 af7bf89b bellard
{
612 af7bf89b bellard
    T0 -= T1 + FLAG_SET(PSR_CARRY);
613 af7bf89b bellard
}
614 af7bf89b bellard
615 af7bf89b bellard
void OPPROTO op_subx_T1_T0_cc(void)
616 af7bf89b bellard
{
617 af7bf89b bellard
    target_ulong src1;
618 af7bf89b bellard
    src1 = T0;
619 b854608e bellard
    if (FLAG_SET(PSR_CARRY))
620 b854608e bellard
    {
621 b854608e bellard
      T0 -= T1 + 1;
622 b854608e bellard
      env->psr = 0;
623 b854608e bellard
#ifdef TARGET_SPARC64
624 b854608e bellard
      if ((src1 & 0xffffffff) <= (T1 & 0xffffffff))
625 b854608e bellard
        env->psr |= PSR_CARRY;
626 b854608e bellard
      env->xcc = 0;
627 b854608e bellard
      if (src1 <= T1)
628 b854608e bellard
        env->xcc |= PSR_CARRY;
629 b854608e bellard
#else
630 b854608e bellard
      if (src1 <= T1)
631 b854608e bellard
        env->psr |= PSR_CARRY;
632 b854608e bellard
#endif
633 b854608e bellard
    }
634 b854608e bellard
    else
635 b854608e bellard
    {
636 b854608e bellard
      T0 -= T1;
637 b854608e bellard
      env->psr = 0;
638 b854608e bellard
#ifdef TARGET_SPARC64
639 b854608e bellard
      if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
640 b854608e bellard
        env->psr |= PSR_CARRY;
641 b854608e bellard
      env->xcc = 0;
642 b854608e bellard
      if (src1 < T1)
643 b854608e bellard
        env->xcc |= PSR_CARRY;
644 b854608e bellard
#else
645 b854608e bellard
      if (src1 < T1)
646 b854608e bellard
        env->psr |= PSR_CARRY;
647 b854608e bellard
#endif
648 b854608e bellard
    }
649 3475187d bellard
#ifdef TARGET_SPARC64
650 3475187d bellard
    if (!(T0 & 0xffffffff))
651 3475187d bellard
        env->psr |= PSR_ZERO;
652 3475187d bellard
    if ((int32_t) T0 < 0)
653 3475187d bellard
        env->psr |= PSR_NEG;
654 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
655 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
656 3475187d bellard
        env->psr |= PSR_OVF;
657 3475187d bellard
658 3475187d bellard
    if (!T0)
659 3475187d bellard
        env->xcc |= PSR_ZERO;
660 3475187d bellard
    if ((int64_t) T0 < 0)
661 3475187d bellard
        env->xcc |= PSR_NEG;
662 3475187d bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
663 3475187d bellard
        env->xcc |= PSR_OVF;
664 3475187d bellard
#else
665 af7bf89b bellard
    if (!T0)
666 af7bf89b bellard
        env->psr |= PSR_ZERO;
667 af7bf89b bellard
    if ((int32_t) T0 < 0)
668 af7bf89b bellard
        env->psr |= PSR_NEG;
669 af7bf89b bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
670 af7bf89b bellard
        env->psr |= PSR_OVF;
671 3475187d bellard
#endif
672 cf495bcf bellard
    FORCE_RET();
673 7a3f1944 bellard
}
674 7a3f1944 bellard
675 e32f879d blueswir1
void OPPROTO op_tsub_T1_T0_cc(void)
676 e32f879d blueswir1
{
677 e32f879d blueswir1
    target_ulong src1;
678 e32f879d blueswir1
679 e32f879d blueswir1
    src1 = T0;
680 e32f879d blueswir1
    T0 -= T1;
681 e32f879d blueswir1
    env->psr = 0;
682 e32f879d blueswir1
#ifdef TARGET_SPARC64
683 e32f879d blueswir1
    if (!(T0 & 0xffffffff))
684 e32f879d blueswir1
        env->psr |= PSR_ZERO;
685 e32f879d blueswir1
    if ((int32_t) T0 < 0)
686 e32f879d blueswir1
        env->psr |= PSR_NEG;
687 e32f879d blueswir1
    if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
688 e32f879d blueswir1
        env->psr |= PSR_CARRY;
689 e32f879d blueswir1
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
690 e32f879d blueswir1
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
691 e32f879d blueswir1
        env->psr |= PSR_OVF;
692 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
693 e32f879d blueswir1
        env->psr |= PSR_OVF;
694 e32f879d blueswir1
695 e32f879d blueswir1
    env->xcc = 0;
696 e32f879d blueswir1
    if (!T0)
697 e32f879d blueswir1
        env->xcc |= PSR_ZERO;
698 e32f879d blueswir1
    if ((int64_t) T0 < 0)
699 e32f879d blueswir1
        env->xcc |= PSR_NEG;
700 e32f879d blueswir1
    if (src1 < T1)
701 e32f879d blueswir1
        env->xcc |= PSR_CARRY;
702 e32f879d blueswir1
    if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
703 e32f879d blueswir1
        env->xcc |= PSR_OVF;
704 e32f879d blueswir1
#else
705 e32f879d blueswir1
    if (!T0)
706 e32f879d blueswir1
        env->psr |= PSR_ZERO;
707 e32f879d blueswir1
    if ((int32_t) T0 < 0)
708 e32f879d blueswir1
        env->psr |= PSR_NEG;
709 e32f879d blueswir1
    if (src1 < T1)
710 e32f879d blueswir1
        env->psr |= PSR_CARRY;
711 e32f879d blueswir1
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
712 e32f879d blueswir1
        env->psr |= PSR_OVF;
713 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
714 e32f879d blueswir1
        env->psr |= PSR_OVF;
715 e32f879d blueswir1
#endif
716 e32f879d blueswir1
    FORCE_RET();
717 e32f879d blueswir1
}
718 e32f879d blueswir1
719 e32f879d blueswir1
void OPPROTO op_tsub_T1_T0_ccTV(void)
720 e32f879d blueswir1
{
721 e32f879d blueswir1
    target_ulong src1;
722 e32f879d blueswir1
723 e32f879d blueswir1
    if ((T0 & 0x03) || (T1 & 0x03))
724 e32f879d blueswir1
        raise_exception(TT_TOVF);
725 e32f879d blueswir1
726 e32f879d blueswir1
    src1 = T0;
727 e32f879d blueswir1
    T0 -= T1;
728 e32f879d blueswir1
729 e32f879d blueswir1
#ifdef TARGET_SPARC64
730 e32f879d blueswir1
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
731 e32f879d blueswir1
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
732 e32f879d blueswir1
        raise_exception(TT_TOVF);
733 e32f879d blueswir1
#else
734 e32f879d blueswir1
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
735 e32f879d blueswir1
        raise_exception(TT_TOVF);
736 e32f879d blueswir1
#endif
737 e32f879d blueswir1
738 e32f879d blueswir1
    env->psr = 0;
739 e32f879d blueswir1
#ifdef TARGET_SPARC64
740 e32f879d blueswir1
    if (!(T0 & 0xffffffff))
741 e32f879d blueswir1
        env->psr |= PSR_ZERO;
742 e32f879d blueswir1
    if ((int32_t) T0 < 0)
743 e32f879d blueswir1
        env->psr |= PSR_NEG;
744 e32f879d blueswir1
    if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
745 e32f879d blueswir1
        env->psr |= PSR_CARRY;
746 e32f879d blueswir1
747 e32f879d blueswir1
    env->xcc = 0;
748 e32f879d blueswir1
    if (!T0)
749 e32f879d blueswir1
        env->xcc |= PSR_ZERO;
750 e32f879d blueswir1
    if ((int64_t) T0 < 0)
751 e32f879d blueswir1
        env->xcc |= PSR_NEG;
752 e32f879d blueswir1
    if (src1 < T1)
753 e32f879d blueswir1
        env->xcc |= PSR_CARRY;
754 e32f879d blueswir1
#else
755 e32f879d blueswir1
    if (!T0)
756 e32f879d blueswir1
        env->psr |= PSR_ZERO;
757 e32f879d blueswir1
    if ((int32_t) T0 < 0)
758 e32f879d blueswir1
        env->psr |= PSR_NEG;
759 e32f879d blueswir1
    if (src1 < T1)
760 e32f879d blueswir1
        env->psr |= PSR_CARRY;
761 e32f879d blueswir1
#endif
762 e32f879d blueswir1
    FORCE_RET();
763 e32f879d blueswir1
}
764 e32f879d blueswir1
765 cf495bcf bellard
void OPPROTO op_and_T1_T0(void)
766 7a3f1944 bellard
{
767 cf495bcf bellard
    T0 &= T1;
768 7a3f1944 bellard
}
769 7a3f1944 bellard
770 cf495bcf bellard
void OPPROTO op_or_T1_T0(void)
771 7a3f1944 bellard
{
772 cf495bcf bellard
    T0 |= T1;
773 7a3f1944 bellard
}
774 7a3f1944 bellard
775 cf495bcf bellard
void OPPROTO op_xor_T1_T0(void)
776 7a3f1944 bellard
{
777 cf495bcf bellard
    T0 ^= T1;
778 7a3f1944 bellard
}
779 7a3f1944 bellard
780 cf495bcf bellard
void OPPROTO op_andn_T1_T0(void)
781 7a3f1944 bellard
{
782 cf495bcf bellard
    T0 &= ~T1;
783 7a3f1944 bellard
}
784 7a3f1944 bellard
785 cf495bcf bellard
void OPPROTO op_orn_T1_T0(void)
786 7a3f1944 bellard
{
787 cf495bcf bellard
    T0 |= ~T1;
788 7a3f1944 bellard
}
789 7a3f1944 bellard
790 cf495bcf bellard
void OPPROTO op_xnor_T1_T0(void)
791 7a3f1944 bellard
{
792 cf495bcf bellard
    T0 ^= ~T1;
793 7a3f1944 bellard
}
794 7a3f1944 bellard
795 cf495bcf bellard
void OPPROTO op_umul_T1_T0(void)
796 7a3f1944 bellard
{
797 cf495bcf bellard
    uint64_t res;
798 af7bf89b bellard
    res = (uint64_t) T0 * (uint64_t) T1;
799 83469015 bellard
#ifdef TARGET_SPARC64
800 83469015 bellard
    T0 = res;
801 83469015 bellard
#else
802 cf495bcf bellard
    T0 = res & 0xffffffff;
803 83469015 bellard
#endif
804 cf495bcf bellard
    env->y = res >> 32;
805 7a3f1944 bellard
}
806 7a3f1944 bellard
807 cf495bcf bellard
void OPPROTO op_smul_T1_T0(void)
808 7a3f1944 bellard
{
809 cf495bcf bellard
    uint64_t res;
810 cf495bcf bellard
    res = (int64_t) ((int32_t) T0) * (int64_t) ((int32_t) T1);
811 83469015 bellard
#ifdef TARGET_SPARC64
812 83469015 bellard
    T0 = res;
813 83469015 bellard
#else
814 cf495bcf bellard
    T0 = res & 0xffffffff;
815 83469015 bellard
#endif
816 cf495bcf bellard
    env->y = res >> 32;
817 7a3f1944 bellard
}
818 7a3f1944 bellard
819 cf495bcf bellard
void OPPROTO op_mulscc_T1_T0(void)
820 7a3f1944 bellard
{
821 af7bf89b bellard
    unsigned int b1, N, V, b2;
822 af7bf89b bellard
    target_ulong src1;
823 af7bf89b bellard
824 4e8b5da2 bellard
    N = FLAG_SET(PSR_NEG);
825 cf495bcf bellard
    V = FLAG_SET(PSR_OVF);
826 4e8b5da2 bellard
    b1 = N ^ V;
827 cf495bcf bellard
    b2 = T0 & 1;
828 cf495bcf bellard
    T0 = (b1 << 31) | (T0 >> 1);
829 cf495bcf bellard
    if (!(env->y & 1))
830 cf495bcf bellard
        T1 = 0;
831 cf495bcf bellard
    /* do addition and update flags */
832 cf495bcf bellard
    src1 = T0;
833 cf495bcf bellard
    T0 += T1;
834 cf495bcf bellard
    env->psr = 0;
835 cf495bcf bellard
    if (!T0)
836 cf495bcf bellard
        env->psr |= PSR_ZERO;
837 af7bf89b bellard
    if ((int32_t) T0 < 0)
838 cf495bcf bellard
        env->psr |= PSR_NEG;
839 cf495bcf bellard
    if (T0 < src1)
840 cf495bcf bellard
        env->psr |= PSR_CARRY;
841 cf495bcf bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
842 cf495bcf bellard
        env->psr |= PSR_OVF;
843 cf495bcf bellard
    env->y = (b2 << 31) | (env->y >> 1);
844 cf495bcf bellard
    FORCE_RET();
845 cf495bcf bellard
}
846 cf495bcf bellard
847 cf495bcf bellard
void OPPROTO op_udiv_T1_T0(void)
848 cf495bcf bellard
{
849 cf495bcf bellard
    uint64_t x0;
850 cf495bcf bellard
    uint32_t x1;
851 cf495bcf bellard
852 cf495bcf bellard
    x0 = T0 | ((uint64_t) (env->y) << 32);
853 cf495bcf bellard
    x1 = T1;
854 9bb234b3 ths
855 9bb234b3 ths
    if (x1 == 0) {
856 9bb234b3 ths
        raise_exception(TT_DIV_ZERO);
857 9bb234b3 ths
    }
858 9bb234b3 ths
859 cf495bcf bellard
    x0 = x0 / x1;
860 cf495bcf bellard
    if (x0 > 0xffffffff) {
861 cf495bcf bellard
        T0 = 0xffffffff;
862 cf495bcf bellard
        T1 = 1;
863 cf495bcf bellard
    } else {
864 cf495bcf bellard
        T0 = x0;
865 cf495bcf bellard
        T1 = 0;
866 cf495bcf bellard
    }
867 cf495bcf bellard
    FORCE_RET();
868 7a3f1944 bellard
}
869 7a3f1944 bellard
870 cf495bcf bellard
void OPPROTO op_sdiv_T1_T0(void)
871 7a3f1944 bellard
{
872 cf495bcf bellard
    int64_t x0;
873 cf495bcf bellard
    int32_t x1;
874 cf495bcf bellard
875 af7bf89b bellard
    x0 = T0 | ((int64_t) (env->y) << 32);
876 cf495bcf bellard
    x1 = T1;
877 9bb234b3 ths
878 9bb234b3 ths
    if (x1 == 0) {
879 9bb234b3 ths
        raise_exception(TT_DIV_ZERO);
880 9bb234b3 ths
    }
881 9bb234b3 ths
882 cf495bcf bellard
    x0 = x0 / x1;
883 cf495bcf bellard
    if ((int32_t) x0 != x0) {
884 af7bf89b bellard
        T0 = x0 < 0? 0x80000000: 0x7fffffff;
885 cf495bcf bellard
        T1 = 1;
886 cf495bcf bellard
    } else {
887 cf495bcf bellard
        T0 = x0;
888 cf495bcf bellard
        T1 = 0;
889 cf495bcf bellard
    }
890 cf495bcf bellard
    FORCE_RET();
891 7a3f1944 bellard
}
892 7a3f1944 bellard
893 cf495bcf bellard
void OPPROTO op_div_cc(void)
894 7a3f1944 bellard
{
895 cf495bcf bellard
    env->psr = 0;
896 3475187d bellard
#ifdef TARGET_SPARC64
897 3475187d bellard
    if (!T0)
898 3475187d bellard
        env->psr |= PSR_ZERO;
899 3475187d bellard
    if ((int32_t) T0 < 0)
900 3475187d bellard
        env->psr |= PSR_NEG;
901 3475187d bellard
    if (T1)
902 3475187d bellard
        env->psr |= PSR_OVF;
903 3475187d bellard
904 3475187d bellard
    env->xcc = 0;
905 3475187d bellard
    if (!T0)
906 3475187d bellard
        env->xcc |= PSR_ZERO;
907 3475187d bellard
    if ((int64_t) T0 < 0)
908 3475187d bellard
        env->xcc |= PSR_NEG;
909 3475187d bellard
#else
910 cf495bcf bellard
    if (!T0)
911 cf495bcf bellard
        env->psr |= PSR_ZERO;
912 af7bf89b bellard
    if ((int32_t) T0 < 0)
913 cf495bcf bellard
        env->psr |= PSR_NEG;
914 cf495bcf bellard
    if (T1)
915 cf495bcf bellard
        env->psr |= PSR_OVF;
916 3475187d bellard
#endif
917 cf495bcf bellard
    FORCE_RET();
918 7a3f1944 bellard
}
919 7a3f1944 bellard
920 3475187d bellard
#ifdef TARGET_SPARC64
921 3475187d bellard
void OPPROTO op_mulx_T1_T0(void)
922 3475187d bellard
{
923 3475187d bellard
    T0 *= T1;
924 3475187d bellard
    FORCE_RET();
925 3475187d bellard
}
926 3475187d bellard
927 3475187d bellard
void OPPROTO op_udivx_T1_T0(void)
928 3475187d bellard
{
929 3475187d bellard
    T0 /= T1;
930 3475187d bellard
    FORCE_RET();
931 3475187d bellard
}
932 3475187d bellard
933 3475187d bellard
void OPPROTO op_sdivx_T1_T0(void)
934 3475187d bellard
{
935 3475187d bellard
    if (T0 == INT64_MIN && T1 == -1)
936 3475187d bellard
        T0 = INT64_MIN;
937 3475187d bellard
    else
938 3475187d bellard
        T0 /= (target_long) T1;
939 3475187d bellard
    FORCE_RET();
940 3475187d bellard
}
941 3475187d bellard
#endif
942 3475187d bellard
943 cf495bcf bellard
void OPPROTO op_logic_T0_cc(void)
944 7a3f1944 bellard
{
945 cf495bcf bellard
    env->psr = 0;
946 3475187d bellard
#ifdef TARGET_SPARC64
947 3475187d bellard
    if (!(T0 & 0xffffffff))
948 3475187d bellard
        env->psr |= PSR_ZERO;
949 3475187d bellard
    if ((int32_t) T0 < 0)
950 3475187d bellard
        env->psr |= PSR_NEG;
951 3475187d bellard
952 3475187d bellard
    env->xcc = 0;
953 3475187d bellard
    if (!T0)
954 3475187d bellard
        env->xcc |= PSR_ZERO;
955 3475187d bellard
    if ((int64_t) T0 < 0)
956 3475187d bellard
        env->xcc |= PSR_NEG;
957 3475187d bellard
#else
958 cf495bcf bellard
    if (!T0)
959 cf495bcf bellard
        env->psr |= PSR_ZERO;
960 af7bf89b bellard
    if ((int32_t) T0 < 0)
961 cf495bcf bellard
        env->psr |= PSR_NEG;
962 3475187d bellard
#endif
963 cf495bcf bellard
    FORCE_RET();
964 7a3f1944 bellard
}
965 7a3f1944 bellard
966 cf495bcf bellard
void OPPROTO op_sll(void)
967 7a3f1944 bellard
{
968 8a08f9a8 blueswir1
    T0 <<= (T1 & 0x1f);
969 7a3f1944 bellard
}
970 7a3f1944 bellard
971 3475187d bellard
#ifdef TARGET_SPARC64
972 8a08f9a8 blueswir1
void OPPROTO op_sllx(void)
973 8a08f9a8 blueswir1
{
974 8a08f9a8 blueswir1
    T0 <<= (T1 & 0x3f);
975 8a08f9a8 blueswir1
}
976 8a08f9a8 blueswir1
977 3475187d bellard
void OPPROTO op_srl(void)
978 3475187d bellard
{
979 8a08f9a8 blueswir1
    T0 = (T0 & 0xffffffff) >> (T1 & 0x1f);
980 3475187d bellard
}
981 3475187d bellard
982 3475187d bellard
void OPPROTO op_srlx(void)
983 3475187d bellard
{
984 8a08f9a8 blueswir1
    T0 >>= (T1 & 0x3f);
985 3475187d bellard
}
986 3475187d bellard
987 3475187d bellard
void OPPROTO op_sra(void)
988 3475187d bellard
{
989 8a08f9a8 blueswir1
    T0 = ((int32_t) (T0 & 0xffffffff)) >> (T1 & 0x1f);
990 3475187d bellard
}
991 3475187d bellard
992 3475187d bellard
void OPPROTO op_srax(void)
993 3475187d bellard
{
994 8a08f9a8 blueswir1
    T0 = ((int64_t) T0) >> (T1 & 0x3f);
995 3475187d bellard
}
996 3475187d bellard
#else
997 cf495bcf bellard
void OPPROTO op_srl(void)
998 7a3f1944 bellard
{
999 8a08f9a8 blueswir1
    T0 >>= (T1 & 0x1f);
1000 7a3f1944 bellard
}
1001 7a3f1944 bellard
1002 cf495bcf bellard
void OPPROTO op_sra(void)
1003 7a3f1944 bellard
{
1004 8a08f9a8 blueswir1
    T0 = ((int32_t) T0) >> (T1 & 0x1f);
1005 7a3f1944 bellard
}
1006 3475187d bellard
#endif
1007 7a3f1944 bellard
1008 e8af50a3 bellard
/* Load and store */
1009 e8af50a3 bellard
#define MEMSUFFIX _raw
1010 e8af50a3 bellard
#include "op_mem.h"
1011 e8af50a3 bellard
#if !defined(CONFIG_USER_ONLY)
1012 e8af50a3 bellard
#define MEMSUFFIX _user
1013 e8af50a3 bellard
#include "op_mem.h"
1014 e8af50a3 bellard
1015 e8af50a3 bellard
#define MEMSUFFIX _kernel
1016 e8af50a3 bellard
#include "op_mem.h"
1017 e8af50a3 bellard
#endif
1018 e8af50a3 bellard
1019 e8af50a3 bellard
void OPPROTO op_ldfsr(void)
1020 e8af50a3 bellard
{
1021 3475187d bellard
    PUT_FSR32(env, *((uint32_t *) &FT0));
1022 8d5f07fa bellard
    helper_ldfsr();
1023 e8af50a3 bellard
}
1024 e8af50a3 bellard
1025 e8af50a3 bellard
void OPPROTO op_stfsr(void)
1026 e8af50a3 bellard
{
1027 3475187d bellard
    *((uint32_t *) &FT0) = GET_FSR32(env);
1028 e8af50a3 bellard
}
1029 e8af50a3 bellard
1030 3475187d bellard
#ifndef TARGET_SPARC64
1031 3475187d bellard
void OPPROTO op_rdpsr(void)
1032 7a3f1944 bellard
{
1033 3475187d bellard
    do_rdpsr();
1034 7a3f1944 bellard
}
1035 7a3f1944 bellard
1036 3475187d bellard
void OPPROTO op_wrpsr(void)
1037 7a3f1944 bellard
{
1038 3475187d bellard
    do_wrpsr();
1039 3475187d bellard
    FORCE_RET();
1040 7a3f1944 bellard
}
1041 7a3f1944 bellard
1042 c688a6eb bellard
void OPPROTO op_wrwim(void)
1043 c688a6eb bellard
{
1044 c688a6eb bellard
#if NWINDOWS == 32
1045 c688a6eb bellard
    env->wim = T0;
1046 c688a6eb bellard
#else
1047 c688a6eb bellard
    env->wim = T0 & ((1 << NWINDOWS) - 1);
1048 c688a6eb bellard
#endif
1049 c688a6eb bellard
}
1050 c688a6eb bellard
1051 3475187d bellard
void OPPROTO op_rett(void)
1052 cf495bcf bellard
{
1053 3475187d bellard
    helper_rett();
1054 3475187d bellard
    FORCE_RET();
1055 e8af50a3 bellard
}
1056 e8af50a3 bellard
1057 3475187d bellard
/* XXX: use another pointer for %iN registers to avoid slow wrapping
1058 3475187d bellard
   handling ? */
1059 3475187d bellard
void OPPROTO op_save(void)
1060 e8af50a3 bellard
{
1061 3475187d bellard
    uint32_t cwp;
1062 3475187d bellard
    cwp = (env->cwp - 1) & (NWINDOWS - 1); 
1063 3475187d bellard
    if (env->wim & (1 << cwp)) {
1064 3475187d bellard
        raise_exception(TT_WIN_OVF);
1065 3475187d bellard
    }
1066 3475187d bellard
    set_cwp(cwp);
1067 e8af50a3 bellard
    FORCE_RET();
1068 e8af50a3 bellard
}
1069 e8af50a3 bellard
1070 3475187d bellard
void OPPROTO op_restore(void)
1071 e8af50a3 bellard
{
1072 3475187d bellard
    uint32_t cwp;
1073 3475187d bellard
    cwp = (env->cwp + 1) & (NWINDOWS - 1); 
1074 3475187d bellard
    if (env->wim & (1 << cwp)) {
1075 3475187d bellard
        raise_exception(TT_WIN_UNF);
1076 3475187d bellard
    }
1077 3475187d bellard
    set_cwp(cwp);
1078 3475187d bellard
    FORCE_RET();
1079 3475187d bellard
}
1080 3475187d bellard
#else
1081 3475187d bellard
void OPPROTO op_rdccr(void)
1082 3475187d bellard
{
1083 3475187d bellard
    T0 = GET_CCR(env);
1084 e8af50a3 bellard
}
1085 e8af50a3 bellard
1086 3475187d bellard
void OPPROTO op_wrccr(void)
1087 e8af50a3 bellard
{
1088 3475187d bellard
    PUT_CCR(env, T0);
1089 e8af50a3 bellard
}
1090 e8af50a3 bellard
1091 3475187d bellard
void OPPROTO op_rdtick(void)
1092 e8af50a3 bellard
{
1093 3475187d bellard
    T0 = 0; // XXX read cycle counter and bit 31
1094 e8af50a3 bellard
}
1095 cf495bcf bellard
1096 3475187d bellard
void OPPROTO op_wrtick(void)
1097 7a3f1944 bellard
{
1098 3475187d bellard
    // XXX write cycle counter and bit 31
1099 7a3f1944 bellard
}
1100 7a3f1944 bellard
1101 3475187d bellard
void OPPROTO op_rdtpc(void)
1102 cf495bcf bellard
{
1103 3475187d bellard
    T0 = env->tpc[env->tl];
1104 3475187d bellard
}
1105 3475187d bellard
1106 3475187d bellard
void OPPROTO op_wrtpc(void)
1107 3475187d bellard
{
1108 3475187d bellard
    env->tpc[env->tl] = T0;
1109 3475187d bellard
}
1110 3475187d bellard
1111 3475187d bellard
void OPPROTO op_rdtnpc(void)
1112 3475187d bellard
{
1113 3475187d bellard
    T0 = env->tnpc[env->tl];
1114 3475187d bellard
}
1115 3475187d bellard
1116 3475187d bellard
void OPPROTO op_wrtnpc(void)
1117 3475187d bellard
{
1118 3475187d bellard
    env->tnpc[env->tl] = T0;
1119 3475187d bellard
}
1120 3475187d bellard
1121 3475187d bellard
void OPPROTO op_rdtstate(void)
1122 3475187d bellard
{
1123 3475187d bellard
    T0 = env->tstate[env->tl];
1124 3475187d bellard
}
1125 3475187d bellard
1126 3475187d bellard
void OPPROTO op_wrtstate(void)
1127 3475187d bellard
{
1128 3475187d bellard
    env->tstate[env->tl] = T0;
1129 3475187d bellard
}
1130 3475187d bellard
1131 3475187d bellard
void OPPROTO op_rdtt(void)
1132 3475187d bellard
{
1133 3475187d bellard
    T0 = env->tt[env->tl];
1134 3475187d bellard
}
1135 3475187d bellard
1136 3475187d bellard
void OPPROTO op_wrtt(void)
1137 3475187d bellard
{
1138 3475187d bellard
    env->tt[env->tl] = T0;
1139 3475187d bellard
}
1140 3475187d bellard
1141 3475187d bellard
void OPPROTO op_rdpstate(void)
1142 3475187d bellard
{
1143 3475187d bellard
    T0 = env->pstate;
1144 3475187d bellard
}
1145 3475187d bellard
1146 3475187d bellard
void OPPROTO op_wrpstate(void)
1147 3475187d bellard
{
1148 83469015 bellard
    do_wrpstate();
1149 3475187d bellard
}
1150 3475187d bellard
1151 3475187d bellard
// CWP handling is reversed in V9, but we still use the V8 register
1152 3475187d bellard
// order.
1153 3475187d bellard
void OPPROTO op_rdcwp(void)
1154 3475187d bellard
{
1155 3475187d bellard
    T0 = NWINDOWS - 1 - env->cwp;
1156 3475187d bellard
}
1157 3475187d bellard
1158 3475187d bellard
void OPPROTO op_wrcwp(void)
1159 3475187d bellard
{
1160 3475187d bellard
    env->cwp = NWINDOWS - 1 - T0;
1161 cf495bcf bellard
}
1162 7a3f1944 bellard
1163 cf495bcf bellard
/* XXX: use another pointer for %iN registers to avoid slow wrapping
1164 cf495bcf bellard
   handling ? */
1165 cf495bcf bellard
void OPPROTO op_save(void)
1166 7a3f1944 bellard
{
1167 af7bf89b bellard
    uint32_t cwp;
1168 cf495bcf bellard
    cwp = (env->cwp - 1) & (NWINDOWS - 1); 
1169 3475187d bellard
    if (env->cansave == 0) {
1170 3475187d bellard
        raise_exception(TT_SPILL | (env->otherwin != 0 ? 
1171 3475187d bellard
                                    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1172 3475187d bellard
                                    ((env->wstate & 0x7) << 2)));
1173 3475187d bellard
    } else {
1174 3475187d bellard
        if (env->cleanwin - env->canrestore == 0) {
1175 3475187d bellard
            // XXX Clean windows without trap
1176 3475187d bellard
            raise_exception(TT_CLRWIN);
1177 3475187d bellard
        } else {
1178 3475187d bellard
            env->cansave--;
1179 3475187d bellard
            env->canrestore++;
1180 3475187d bellard
            set_cwp(cwp);
1181 3475187d bellard
        }
1182 cf495bcf bellard
    }
1183 cf495bcf bellard
    FORCE_RET();
1184 7a3f1944 bellard
}
1185 7a3f1944 bellard
1186 cf495bcf bellard
void OPPROTO op_restore(void)
1187 7a3f1944 bellard
{
1188 af7bf89b bellard
    uint32_t cwp;
1189 cf495bcf bellard
    cwp = (env->cwp + 1) & (NWINDOWS - 1); 
1190 3475187d bellard
    if (env->canrestore == 0) {
1191 3475187d bellard
        raise_exception(TT_FILL | (env->otherwin != 0 ? 
1192 3475187d bellard
                                   (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1193 3475187d bellard
                                   ((env->wstate & 0x7) << 2)));
1194 3475187d bellard
    } else {
1195 3475187d bellard
        env->cansave++;
1196 3475187d bellard
        env->canrestore--;
1197 3475187d bellard
        set_cwp(cwp);
1198 cf495bcf bellard
    }
1199 cf495bcf bellard
    FORCE_RET();
1200 7a3f1944 bellard
}
1201 3475187d bellard
#endif
1202 7a3f1944 bellard
1203 cf495bcf bellard
void OPPROTO op_exception(void)
1204 7a3f1944 bellard
{
1205 cf495bcf bellard
    env->exception_index = PARAM1;
1206 cf495bcf bellard
    cpu_loop_exit();
1207 7a3f1944 bellard
}
1208 7a3f1944 bellard
1209 cf495bcf bellard
void OPPROTO op_trap_T0(void)
1210 7a3f1944 bellard
{
1211 cf495bcf bellard
    env->exception_index = TT_TRAP + (T0 & 0x7f);
1212 cf495bcf bellard
    cpu_loop_exit();
1213 7a3f1944 bellard
}
1214 7a3f1944 bellard
1215 cf495bcf bellard
void OPPROTO op_trapcc_T0(void)
1216 7a3f1944 bellard
{
1217 cf495bcf bellard
    if (T2) {
1218 cf495bcf bellard
        env->exception_index = TT_TRAP + (T0 & 0x7f);
1219 cf495bcf bellard
        cpu_loop_exit();
1220 cf495bcf bellard
    }
1221 cf495bcf bellard
    FORCE_RET();
1222 7a3f1944 bellard
}
1223 7a3f1944 bellard
1224 e80cfcfc bellard
void OPPROTO op_fpexception_im(void)
1225 e8af50a3 bellard
{
1226 e80cfcfc bellard
    env->exception_index = TT_FP_EXCP;
1227 e80cfcfc bellard
    env->fsr &= ~FSR_FTT_MASK;
1228 e80cfcfc bellard
    env->fsr |= PARAM1;
1229 e8af50a3 bellard
    cpu_loop_exit();
1230 e80cfcfc bellard
    FORCE_RET();
1231 e80cfcfc bellard
}
1232 e80cfcfc bellard
1233 e80cfcfc bellard
void OPPROTO op_debug(void)
1234 e80cfcfc bellard
{
1235 e80cfcfc bellard
    helper_debug();
1236 e8af50a3 bellard
}
1237 e8af50a3 bellard
1238 cf495bcf bellard
void OPPROTO op_exit_tb(void)
1239 7a3f1944 bellard
{
1240 cf495bcf bellard
    EXIT_TB();
1241 7a3f1944 bellard
}
1242 7a3f1944 bellard
1243 3475187d bellard
void OPPROTO op_eval_ba(void)
1244 3475187d bellard
{
1245 3475187d bellard
    T2 = 1;
1246 3475187d bellard
}
1247 3475187d bellard
1248 cf495bcf bellard
void OPPROTO op_eval_be(void)
1249 7a3f1944 bellard
{
1250 af7bf89b bellard
    T2 = FLAG_SET(PSR_ZERO);
1251 7a3f1944 bellard
}
1252 7a3f1944 bellard
1253 cf495bcf bellard
void OPPROTO op_eval_ble(void)
1254 7a3f1944 bellard
{
1255 af7bf89b bellard
    target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
1256 612b477d bellard
    
1257 cf495bcf bellard
    T2 = Z | (N ^ V);
1258 7a3f1944 bellard
}
1259 7a3f1944 bellard
1260 cf495bcf bellard
void OPPROTO op_eval_bl(void)
1261 7a3f1944 bellard
{
1262 af7bf89b bellard
    target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
1263 612b477d bellard
1264 cf495bcf bellard
    T2 = N ^ V;
1265 7a3f1944 bellard
}
1266 7a3f1944 bellard
1267 cf495bcf bellard
void OPPROTO op_eval_bleu(void)
1268 7a3f1944 bellard
{
1269 af7bf89b bellard
    target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
1270 612b477d bellard
1271 cf495bcf bellard
    T2 = C | Z;
1272 7a3f1944 bellard
}
1273 7a3f1944 bellard
1274 cf495bcf bellard
void OPPROTO op_eval_bcs(void)
1275 7a3f1944 bellard
{
1276 af7bf89b bellard
    T2 = FLAG_SET(PSR_CARRY);
1277 7a3f1944 bellard
}
1278 7a3f1944 bellard
1279 cf495bcf bellard
void OPPROTO op_eval_bvs(void)
1280 7a3f1944 bellard
{
1281 af7bf89b bellard
    T2 = FLAG_SET(PSR_OVF);
1282 7a3f1944 bellard
}
1283 7a3f1944 bellard
1284 3475187d bellard
void OPPROTO op_eval_bn(void)
1285 3475187d bellard
{
1286 3475187d bellard
    T2 = 0;
1287 3475187d bellard
}
1288 3475187d bellard
1289 cf495bcf bellard
void OPPROTO op_eval_bneg(void)
1290 7a3f1944 bellard
{
1291 af7bf89b bellard
    T2 = FLAG_SET(PSR_NEG);
1292 7a3f1944 bellard
}
1293 7a3f1944 bellard
1294 cf495bcf bellard
void OPPROTO op_eval_bne(void)
1295 7a3f1944 bellard
{
1296 af7bf89b bellard
    T2 = !FLAG_SET(PSR_ZERO);
1297 7a3f1944 bellard
}
1298 7a3f1944 bellard
1299 cf495bcf bellard
void OPPROTO op_eval_bg(void)
1300 7a3f1944 bellard
{
1301 af7bf89b bellard
    target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
1302 612b477d bellard
1303 cf495bcf bellard
    T2 = !(Z | (N ^ V));
1304 7a3f1944 bellard
}
1305 7a3f1944 bellard
1306 cf495bcf bellard
void OPPROTO op_eval_bge(void)
1307 7a3f1944 bellard
{
1308 af7bf89b bellard
    target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
1309 612b477d bellard
1310 cf495bcf bellard
    T2 = !(N ^ V);
1311 7a3f1944 bellard
}
1312 7a3f1944 bellard
1313 cf495bcf bellard
void OPPROTO op_eval_bgu(void)
1314 7a3f1944 bellard
{
1315 af7bf89b bellard
    target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
1316 612b477d bellard
1317 cf495bcf bellard
    T2 = !(C | Z);
1318 7a3f1944 bellard
}
1319 7a3f1944 bellard
1320 cf495bcf bellard
void OPPROTO op_eval_bcc(void)
1321 7a3f1944 bellard
{
1322 af7bf89b bellard
    T2 = !FLAG_SET(PSR_CARRY);
1323 7a3f1944 bellard
}
1324 7a3f1944 bellard
1325 cf495bcf bellard
void OPPROTO op_eval_bpos(void)
1326 cf495bcf bellard
{
1327 af7bf89b bellard
    T2 = !FLAG_SET(PSR_NEG);
1328 cf495bcf bellard
}
1329 cf495bcf bellard
1330 cf495bcf bellard
void OPPROTO op_eval_bvc(void)
1331 cf495bcf bellard
{
1332 af7bf89b bellard
    T2 = !FLAG_SET(PSR_OVF);
1333 cf495bcf bellard
}
1334 cf495bcf bellard
1335 3475187d bellard
#ifdef TARGET_SPARC64
1336 3475187d bellard
void OPPROTO op_eval_xbe(void)
1337 3475187d bellard
{
1338 3475187d bellard
    T2 = XFLAG_SET(PSR_ZERO);
1339 3475187d bellard
}
1340 e8af50a3 bellard
1341 3475187d bellard
void OPPROTO op_eval_xble(void)
1342 e8af50a3 bellard
{
1343 3475187d bellard
    target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1344 3475187d bellard
    
1345 3475187d bellard
    T2 = Z | (N ^ V);
1346 e8af50a3 bellard
}
1347 e8af50a3 bellard
1348 3475187d bellard
void OPPROTO op_eval_xbl(void)
1349 e8af50a3 bellard
{
1350 3475187d bellard
    target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1351 3475187d bellard
1352 3475187d bellard
    T2 = N ^ V;
1353 e8af50a3 bellard
}
1354 e8af50a3 bellard
1355 3475187d bellard
void OPPROTO op_eval_xbleu(void)
1356 e8af50a3 bellard
{
1357 3475187d bellard
    target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
1358 3475187d bellard
1359 3475187d bellard
    T2 = C | Z;
1360 e8af50a3 bellard
}
1361 e8af50a3 bellard
1362 3475187d bellard
void OPPROTO op_eval_xbcs(void)
1363 e8af50a3 bellard
{
1364 3475187d bellard
    T2 = XFLAG_SET(PSR_CARRY);
1365 e8af50a3 bellard
}
1366 e8af50a3 bellard
1367 3475187d bellard
void OPPROTO op_eval_xbvs(void)
1368 e8af50a3 bellard
{
1369 3475187d bellard
    T2 = XFLAG_SET(PSR_OVF);
1370 e8af50a3 bellard
}
1371 e8af50a3 bellard
1372 3475187d bellard
void OPPROTO op_eval_xbneg(void)
1373 e8af50a3 bellard
{
1374 3475187d bellard
    T2 = XFLAG_SET(PSR_NEG);
1375 e8af50a3 bellard
}
1376 e8af50a3 bellard
1377 3475187d bellard
void OPPROTO op_eval_xbne(void)
1378 e8af50a3 bellard
{
1379 3475187d bellard
    T2 = !XFLAG_SET(PSR_ZERO);
1380 e8af50a3 bellard
}
1381 e8af50a3 bellard
1382 3475187d bellard
void OPPROTO op_eval_xbg(void)
1383 e8af50a3 bellard
{
1384 3475187d bellard
    target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1385 3475187d bellard
1386 3475187d bellard
    T2 = !(Z | (N ^ V));
1387 e8af50a3 bellard
}
1388 e8af50a3 bellard
1389 3475187d bellard
void OPPROTO op_eval_xbge(void)
1390 e8af50a3 bellard
{
1391 3475187d bellard
    target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1392 3475187d bellard
1393 3475187d bellard
    T2 = !(N ^ V);
1394 3475187d bellard
}
1395 3475187d bellard
1396 3475187d bellard
void OPPROTO op_eval_xbgu(void)
1397 3475187d bellard
{
1398 3475187d bellard
    target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
1399 3475187d bellard
1400 3475187d bellard
    T2 = !(C | Z);
1401 3475187d bellard
}
1402 3475187d bellard
1403 3475187d bellard
void OPPROTO op_eval_xbcc(void)
1404 3475187d bellard
{
1405 3475187d bellard
    T2 = !XFLAG_SET(PSR_CARRY);
1406 3475187d bellard
}
1407 3475187d bellard
1408 3475187d bellard
void OPPROTO op_eval_xbpos(void)
1409 3475187d bellard
{
1410 3475187d bellard
    T2 = !XFLAG_SET(PSR_NEG);
1411 3475187d bellard
}
1412 3475187d bellard
1413 3475187d bellard
void OPPROTO op_eval_xbvc(void)
1414 3475187d bellard
{
1415 3475187d bellard
    T2 = !XFLAG_SET(PSR_OVF);
1416 3475187d bellard
}
1417 3475187d bellard
#endif
1418 3475187d bellard
1419 3475187d bellard
#define FCC
1420 3475187d bellard
#define FFLAG_SET(x) (env->fsr & x? 1: 0)
1421 3475187d bellard
#include "fbranch_template.h"
1422 3475187d bellard
1423 3475187d bellard
#ifdef TARGET_SPARC64
1424 3475187d bellard
#define FCC _fcc1
1425 3475187d bellard
#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 32))? 1: 0)
1426 3475187d bellard
#include "fbranch_template.h"
1427 3475187d bellard
#define FCC _fcc2
1428 3475187d bellard
#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 34))? 1: 0)
1429 3475187d bellard
#include "fbranch_template.h"
1430 3475187d bellard
#define FCC _fcc3
1431 3475187d bellard
#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 36))? 1: 0)
1432 3475187d bellard
#include "fbranch_template.h"
1433 3475187d bellard
#endif
1434 3475187d bellard
1435 3475187d bellard
#ifdef TARGET_SPARC64
1436 3475187d bellard
void OPPROTO op_eval_brz(void)
1437 3475187d bellard
{
1438 83469015 bellard
    T2 = (T0 == 0);
1439 e8af50a3 bellard
}
1440 e8af50a3 bellard
1441 3475187d bellard
void OPPROTO op_eval_brnz(void)
1442 e8af50a3 bellard
{
1443 83469015 bellard
    T2 = (T0 != 0);
1444 e8af50a3 bellard
}
1445 e8af50a3 bellard
1446 3475187d bellard
void OPPROTO op_eval_brlz(void)
1447 e8af50a3 bellard
{
1448 3475187d bellard
    T2 = ((int64_t)T0 < 0);
1449 e8af50a3 bellard
}
1450 e8af50a3 bellard
1451 3475187d bellard
void OPPROTO op_eval_brlez(void)
1452 e8af50a3 bellard
{
1453 3475187d bellard
    T2 = ((int64_t)T0 <= 0);
1454 e8af50a3 bellard
}
1455 e8af50a3 bellard
1456 3475187d bellard
void OPPROTO op_eval_brgz(void)
1457 e8af50a3 bellard
{
1458 3475187d bellard
    T2 = ((int64_t)T0 > 0);
1459 e8af50a3 bellard
}
1460 e8af50a3 bellard
1461 3475187d bellard
void OPPROTO op_eval_brgez(void)
1462 e8af50a3 bellard
{
1463 3475187d bellard
    T2 = ((int64_t)T0 >= 0);
1464 e8af50a3 bellard
}
1465 e8af50a3 bellard
1466 3475187d bellard
void OPPROTO op_jmp_im64(void)
1467 3475187d bellard
{
1468 3475187d bellard
    env->pc = PARAMQ1;
1469 3475187d bellard
}
1470 3475187d bellard
1471 3475187d bellard
void OPPROTO op_movq_npc_im64(void)
1472 3475187d bellard
{
1473 3475187d bellard
    env->npc = PARAMQ1;
1474 3475187d bellard
}
1475 3475187d bellard
#endif
1476 3475187d bellard
1477 cf495bcf bellard
void OPPROTO op_jmp_im(void)
1478 cf495bcf bellard
{
1479 3475187d bellard
    env->pc = (uint32_t)PARAM1;
1480 cf495bcf bellard
}
1481 cf495bcf bellard
1482 cf495bcf bellard
void OPPROTO op_movl_npc_im(void)
1483 cf495bcf bellard
{
1484 3475187d bellard
    env->npc = (uint32_t)PARAM1;
1485 cf495bcf bellard
}
1486 7a3f1944 bellard
1487 cf495bcf bellard
void OPPROTO op_movl_npc_T0(void)
1488 7a3f1944 bellard
{
1489 cf495bcf bellard
    env->npc = T0;
1490 7a3f1944 bellard
}
1491 7a3f1944 bellard
1492 0bee699e bellard
void OPPROTO op_mov_pc_npc(void)
1493 0bee699e bellard
{
1494 0bee699e bellard
    env->pc = env->npc;
1495 0bee699e bellard
}
1496 0bee699e bellard
1497 cf495bcf bellard
void OPPROTO op_next_insn(void)
1498 7a3f1944 bellard
{
1499 cf495bcf bellard
    env->pc = env->npc;
1500 cf495bcf bellard
    env->npc = env->npc + 4;
1501 7a3f1944 bellard
}
1502 7a3f1944 bellard
1503 83469015 bellard
void OPPROTO op_goto_tb0(void)
1504 72cbca10 bellard
{
1505 83469015 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
1506 72cbca10 bellard
}
1507 72cbca10 bellard
1508 83469015 bellard
void OPPROTO op_goto_tb1(void)
1509 7a3f1944 bellard
{
1510 83469015 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
1511 72cbca10 bellard
}
1512 72cbca10 bellard
1513 83469015 bellard
void OPPROTO op_jmp_label(void)
1514 72cbca10 bellard
{
1515 83469015 bellard
    GOTO_LABEL_PARAM(1);
1516 83469015 bellard
}
1517 83469015 bellard
1518 83469015 bellard
void OPPROTO op_jnz_T2_label(void)
1519 83469015 bellard
{
1520 83469015 bellard
    if (T2)
1521 83469015 bellard
        GOTO_LABEL_PARAM(1);
1522 cf495bcf bellard
    FORCE_RET();
1523 7a3f1944 bellard
}
1524 7a3f1944 bellard
1525 83469015 bellard
void OPPROTO op_jz_T2_label(void)
1526 7a3f1944 bellard
{
1527 83469015 bellard
    if (!T2)
1528 83469015 bellard
        GOTO_LABEL_PARAM(1);
1529 cf495bcf bellard
    FORCE_RET();
1530 7a3f1944 bellard
}
1531 72cbca10 bellard
1532 658138bc bellard
void OPPROTO op_flush_T0(void)
1533 658138bc bellard
{
1534 658138bc bellard
    helper_flush(T0);
1535 658138bc bellard
}
1536 e8af50a3 bellard
1537 417454b0 blueswir1
void OPPROTO op_clear_ieee_excp_and_FTT(void)
1538 417454b0 blueswir1
{
1539 417454b0 blueswir1
    env->fsr &= ~(FSR_FTT_MASK | FSR_CEXC_MASK);;
1540 417454b0 blueswir1
}
1541 417454b0 blueswir1
1542 65ce8c2f bellard
#define F_OP(name, p) void OPPROTO op_f##name##p(void)
1543 65ce8c2f bellard
1544 65ce8c2f bellard
#define F_BINOP(name)                                           \
1545 65ce8c2f bellard
    F_OP(name, s)                                               \
1546 65ce8c2f bellard
    {                                                           \
1547 417454b0 blueswir1
        set_float_exception_flags(0, &env->fp_status);                \
1548 65ce8c2f bellard
        FT0 = float32_ ## name (FT0, FT1, &env->fp_status);     \
1549 417454b0 blueswir1
        check_ieee_exceptions();                                \
1550 65ce8c2f bellard
    }                                                           \
1551 65ce8c2f bellard
    F_OP(name, d)                                               \
1552 65ce8c2f bellard
    {                                                           \
1553 417454b0 blueswir1
        set_float_exception_flags(0, &env->fp_status);                \
1554 65ce8c2f bellard
        DT0 = float64_ ## name (DT0, DT1, &env->fp_status);     \
1555 417454b0 blueswir1
        check_ieee_exceptions();                                \
1556 65ce8c2f bellard
    }
1557 e8af50a3 bellard
1558 65ce8c2f bellard
F_BINOP(add);
1559 65ce8c2f bellard
F_BINOP(sub);
1560 65ce8c2f bellard
F_BINOP(mul);
1561 65ce8c2f bellard
F_BINOP(div);
1562 65ce8c2f bellard
#undef F_BINOP
1563 e8af50a3 bellard
1564 e8af50a3 bellard
void OPPROTO op_fsmuld(void)
1565 e8af50a3 bellard
{
1566 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1567 65ce8c2f bellard
    DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
1568 65ce8c2f bellard
                      float32_to_float64(FT1, &env->fp_status),
1569 65ce8c2f bellard
                      &env->fp_status);
1570 417454b0 blueswir1
    check_ieee_exceptions();
1571 e8af50a3 bellard
}
1572 e8af50a3 bellard
1573 65ce8c2f bellard
#define F_HELPER(name)    \
1574 65ce8c2f bellard
    F_OP(name, s)         \
1575 65ce8c2f bellard
    {                     \
1576 65ce8c2f bellard
        do_f##name##s();  \
1577 65ce8c2f bellard
    }                     \
1578 65ce8c2f bellard
    F_OP(name, d)         \
1579 65ce8c2f bellard
    {                     \
1580 65ce8c2f bellard
        do_f##name##d();  \
1581 65ce8c2f bellard
    }
1582 e8af50a3 bellard
1583 65ce8c2f bellard
F_HELPER(sqrt);
1584 e8af50a3 bellard
1585 65ce8c2f bellard
F_OP(neg, s)
1586 e8af50a3 bellard
{
1587 65ce8c2f bellard
    FT0 = float32_chs(FT1);
1588 e8af50a3 bellard
}
1589 e8af50a3 bellard
1590 65ce8c2f bellard
F_OP(abs, s)
1591 e8af50a3 bellard
{
1592 65ce8c2f bellard
    do_fabss();
1593 e8af50a3 bellard
}
1594 e8af50a3 bellard
1595 65ce8c2f bellard
F_HELPER(cmp);
1596 417454b0 blueswir1
F_HELPER(cmpe);
1597 e8af50a3 bellard
1598 65ce8c2f bellard
#ifdef TARGET_SPARC64
1599 65ce8c2f bellard
F_OP(neg, d)
1600 e8af50a3 bellard
{
1601 65ce8c2f bellard
    DT0 = float64_chs(DT1);
1602 e8af50a3 bellard
}
1603 e8af50a3 bellard
1604 65ce8c2f bellard
F_OP(abs, d)
1605 e8af50a3 bellard
{
1606 65ce8c2f bellard
    do_fabsd();
1607 e8af50a3 bellard
}
1608 e8af50a3 bellard
1609 3475187d bellard
void OPPROTO op_fcmps_fcc1(void)
1610 3475187d bellard
{
1611 3475187d bellard
    do_fcmps_fcc1();
1612 3475187d bellard
}
1613 3475187d bellard
1614 3475187d bellard
void OPPROTO op_fcmpd_fcc1(void)
1615 3475187d bellard
{
1616 3475187d bellard
    do_fcmpd_fcc1();
1617 3475187d bellard
}
1618 3475187d bellard
1619 3475187d bellard
void OPPROTO op_fcmps_fcc2(void)
1620 3475187d bellard
{
1621 3475187d bellard
    do_fcmps_fcc2();
1622 3475187d bellard
}
1623 3475187d bellard
1624 3475187d bellard
void OPPROTO op_fcmpd_fcc2(void)
1625 3475187d bellard
{
1626 3475187d bellard
    do_fcmpd_fcc2();
1627 3475187d bellard
}
1628 3475187d bellard
1629 3475187d bellard
void OPPROTO op_fcmps_fcc3(void)
1630 3475187d bellard
{
1631 3475187d bellard
    do_fcmps_fcc3();
1632 3475187d bellard
}
1633 3475187d bellard
1634 3475187d bellard
void OPPROTO op_fcmpd_fcc3(void)
1635 3475187d bellard
{
1636 3475187d bellard
    do_fcmpd_fcc3();
1637 3475187d bellard
}
1638 417454b0 blueswir1
1639 417454b0 blueswir1
void OPPROTO op_fcmpes_fcc1(void)
1640 417454b0 blueswir1
{
1641 417454b0 blueswir1
    do_fcmpes_fcc1();
1642 417454b0 blueswir1
}
1643 417454b0 blueswir1
1644 417454b0 blueswir1
void OPPROTO op_fcmped_fcc1(void)
1645 417454b0 blueswir1
{
1646 417454b0 blueswir1
    do_fcmped_fcc1();
1647 417454b0 blueswir1
}
1648 417454b0 blueswir1
1649 417454b0 blueswir1
void OPPROTO op_fcmpes_fcc2(void)
1650 417454b0 blueswir1
{
1651 417454b0 blueswir1
    do_fcmpes_fcc2();
1652 417454b0 blueswir1
}
1653 417454b0 blueswir1
1654 417454b0 blueswir1
void OPPROTO op_fcmped_fcc2(void)
1655 417454b0 blueswir1
{
1656 417454b0 blueswir1
    do_fcmped_fcc2();
1657 417454b0 blueswir1
}
1658 417454b0 blueswir1
1659 417454b0 blueswir1
void OPPROTO op_fcmpes_fcc3(void)
1660 417454b0 blueswir1
{
1661 417454b0 blueswir1
    do_fcmpes_fcc3();
1662 417454b0 blueswir1
}
1663 417454b0 blueswir1
1664 417454b0 blueswir1
void OPPROTO op_fcmped_fcc3(void)
1665 417454b0 blueswir1
{
1666 417454b0 blueswir1
    do_fcmped_fcc3();
1667 417454b0 blueswir1
}
1668 417454b0 blueswir1
1669 3475187d bellard
#endif
1670 3475187d bellard
1671 65ce8c2f bellard
/* Integer to float conversion.  */
1672 a0c4cb4a bellard
#ifdef USE_INT_TO_FLOAT_HELPERS
1673 65ce8c2f bellard
F_HELPER(ito);
1674 a0c4cb4a bellard
#else
1675 65ce8c2f bellard
F_OP(ito, s)
1676 a0c4cb4a bellard
{
1677 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1678 65ce8c2f bellard
    FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
1679 417454b0 blueswir1
    check_ieee_exceptions();
1680 e8af50a3 bellard
}
1681 e8af50a3 bellard
1682 65ce8c2f bellard
F_OP(ito, d)
1683 e8af50a3 bellard
{
1684 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1685 65ce8c2f bellard
    DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
1686 417454b0 blueswir1
    check_ieee_exceptions();
1687 e8af50a3 bellard
}
1688 3475187d bellard
1689 3475187d bellard
#ifdef TARGET_SPARC64
1690 65ce8c2f bellard
F_OP(xto, s)
1691 3475187d bellard
{
1692 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1693 65ce8c2f bellard
    FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1694 417454b0 blueswir1
    check_ieee_exceptions();
1695 3475187d bellard
}
1696 3475187d bellard
1697 65ce8c2f bellard
F_OP(xto, d)
1698 3475187d bellard
{
1699 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1700 65ce8c2f bellard
    DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1701 417454b0 blueswir1
    check_ieee_exceptions();
1702 3475187d bellard
}
1703 3475187d bellard
#endif
1704 a0c4cb4a bellard
#endif
1705 65ce8c2f bellard
#undef F_HELPER
1706 a0c4cb4a bellard
1707 65ce8c2f bellard
/* floating point conversion */
1708 a0c4cb4a bellard
void OPPROTO op_fdtos(void)
1709 a0c4cb4a bellard
{
1710 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1711 65ce8c2f bellard
    FT0 = float64_to_float32(DT1, &env->fp_status);
1712 417454b0 blueswir1
    check_ieee_exceptions();
1713 a0c4cb4a bellard
}
1714 e8af50a3 bellard
1715 e8af50a3 bellard
void OPPROTO op_fstod(void)
1716 e8af50a3 bellard
{
1717 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1718 65ce8c2f bellard
    DT0 = float32_to_float64(FT1, &env->fp_status);
1719 417454b0 blueswir1
    check_ieee_exceptions();
1720 e8af50a3 bellard
}
1721 e8af50a3 bellard
1722 65ce8c2f bellard
/* Float to integer conversion.  */
1723 e8af50a3 bellard
void OPPROTO op_fstoi(void)
1724 e8af50a3 bellard
{
1725 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1726 bd59780c ths
    *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
1727 417454b0 blueswir1
    check_ieee_exceptions();
1728 e8af50a3 bellard
}
1729 e8af50a3 bellard
1730 e8af50a3 bellard
void OPPROTO op_fdtoi(void)
1731 e8af50a3 bellard
{
1732 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1733 bd59780c ths
    *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
1734 417454b0 blueswir1
    check_ieee_exceptions();
1735 e8af50a3 bellard
}
1736 e8af50a3 bellard
1737 3475187d bellard
#ifdef TARGET_SPARC64
1738 3475187d bellard
void OPPROTO op_fstox(void)
1739 3475187d bellard
{
1740 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1741 bd59780c ths
    *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
1742 417454b0 blueswir1
    check_ieee_exceptions();
1743 3475187d bellard
}
1744 3475187d bellard
1745 3475187d bellard
void OPPROTO op_fdtox(void)
1746 3475187d bellard
{
1747 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1748 bd59780c ths
    *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
1749 417454b0 blueswir1
    check_ieee_exceptions();
1750 3475187d bellard
}
1751 3475187d bellard
1752 3475187d bellard
void OPPROTO op_fmovs_cc(void)
1753 3475187d bellard
{
1754 3475187d bellard
    if (T2)
1755 3475187d bellard
        FT0 = FT1;
1756 3475187d bellard
}
1757 3475187d bellard
1758 3475187d bellard
void OPPROTO op_fmovd_cc(void)
1759 3475187d bellard
{
1760 3475187d bellard
    if (T2)
1761 3475187d bellard
        DT0 = DT1;
1762 3475187d bellard
}
1763 3475187d bellard
1764 3475187d bellard
void OPPROTO op_mov_cc(void)
1765 3475187d bellard
{
1766 3475187d bellard
    if (T2)
1767 3475187d bellard
        T0 = T1;
1768 3475187d bellard
}
1769 3475187d bellard
1770 3475187d bellard
void OPPROTO op_flushw(void)
1771 3475187d bellard
{
1772 3475187d bellard
    if (env->cansave != NWINDOWS - 2) {
1773 3475187d bellard
        raise_exception(TT_SPILL | (env->otherwin != 0 ? 
1774 3475187d bellard
                                    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1775 3475187d bellard
                                    ((env->wstate & 0x7) << 2)));
1776 3475187d bellard
    }
1777 3475187d bellard
}
1778 3475187d bellard
1779 3475187d bellard
void OPPROTO op_saved(void)
1780 3475187d bellard
{
1781 3475187d bellard
    env->cansave++;
1782 3475187d bellard
    if (env->otherwin == 0)
1783 3475187d bellard
        env->canrestore--;
1784 725cb90b bellard
    else
1785 725cb90b bellard
        env->otherwin--;
1786 725cb90b bellard
    FORCE_RET();
1787 3475187d bellard
}
1788 3475187d bellard
1789 3475187d bellard
void OPPROTO op_restored(void)
1790 3475187d bellard
{
1791 3475187d bellard
    env->canrestore++;
1792 3475187d bellard
    if (env->cleanwin < NWINDOWS - 1)
1793 3475187d bellard
        env->cleanwin++;
1794 3475187d bellard
    if (env->otherwin == 0)
1795 3475187d bellard
        env->cansave--;
1796 3475187d bellard
    else
1797 3475187d bellard
        env->otherwin--;
1798 725cb90b bellard
    FORCE_RET();
1799 3475187d bellard
}
1800 3475187d bellard
1801 3475187d bellard
void OPPROTO op_popc(void)
1802 3475187d bellard
{
1803 3475187d bellard
    do_popc();
1804 3475187d bellard
}
1805 3475187d bellard
1806 3475187d bellard
void OPPROTO op_done(void)
1807 3475187d bellard
{
1808 83469015 bellard
    do_done();
1809 3475187d bellard
}
1810 3475187d bellard
1811 3475187d bellard
void OPPROTO op_retry(void)
1812 3475187d bellard
{
1813 83469015 bellard
    do_retry();
1814 3475187d bellard
}
1815 3475187d bellard
1816 3475187d bellard
void OPPROTO op_sir(void)
1817 3475187d bellard
{
1818 3475187d bellard
    // XXX
1819 3475187d bellard
1820 3475187d bellard
}
1821 3475187d bellard
1822 3475187d bellard
void OPPROTO op_ld_asi_reg()
1823 3475187d bellard
{
1824 3475187d bellard
    T0 += PARAM1;
1825 3475187d bellard
    helper_ld_asi(env->asi, PARAM2, PARAM3);
1826 3475187d bellard
}
1827 3475187d bellard
1828 3475187d bellard
void OPPROTO op_st_asi_reg()
1829 3475187d bellard
{
1830 3475187d bellard
    T0 += PARAM1;
1831 3475187d bellard
    helper_st_asi(env->asi, PARAM2, PARAM3);
1832 3475187d bellard
}
1833 3475187d bellard
#endif
1834 3475187d bellard
1835 e8af50a3 bellard
void OPPROTO op_ld_asi()
1836 e8af50a3 bellard
{
1837 e8af50a3 bellard
    helper_ld_asi(PARAM1, PARAM2, PARAM3);
1838 e8af50a3 bellard
}
1839 e8af50a3 bellard
1840 e8af50a3 bellard
void OPPROTO op_st_asi()
1841 e8af50a3 bellard
{
1842 e8af50a3 bellard
    helper_st_asi(PARAM1, PARAM2, PARAM3);
1843 e8af50a3 bellard
}
1844 e8af50a3 bellard
1845 725cb90b bellard
#ifdef TARGET_SPARC64
1846 725cb90b bellard
void OPPROTO op_alignaddr()
1847 725cb90b bellard
{
1848 725cb90b bellard
    uint64_t tmp;
1849 725cb90b bellard
1850 725cb90b bellard
    tmp = T0 + T1;
1851 725cb90b bellard
    env->gsr &= ~7ULL;
1852 725cb90b bellard
    env->gsr |= tmp & 7ULL;
1853 725cb90b bellard
    T0 = tmp & ~7ULL;
1854 725cb90b bellard
}
1855 725cb90b bellard
1856 725cb90b bellard
void OPPROTO op_faligndata()
1857 725cb90b bellard
{
1858 725cb90b bellard
    uint64_t tmp;
1859 725cb90b bellard
1860 725cb90b bellard
    tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
1861 725cb90b bellard
    tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
1862 725cb90b bellard
    (*((uint64_t *)&DT0)) = tmp;
1863 725cb90b bellard
}
1864 725cb90b bellard
#endif