Statistics
| Branch: | Revision:

root / target-ppc / translate_init.c @ 417bf010

History | View | Annotate | Download (246.8 kB)

1
/*
2
 *  PowerPC CPU initialization for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20

    
21
/* A lot of PowerPC definition have been included here.
22
 * Most of them are not usable for now but have been kept
23
 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24
 */
25

    
26
#include "dis-asm.h"
27

    
28
//#define PPC_DUMP_CPU
29
//#define PPC_DEBUG_SPR
30
//#define PPC_DEBUG_IRQ
31

    
32
struct ppc_def_t {
33
    const unsigned char *name;
34
    uint32_t pvr;
35
    uint32_t pvr_mask;
36
    uint64_t insns_flags;
37
    uint64_t msr_mask;
38
    uint8_t mmu_model;
39
    uint8_t excp_model;
40
    uint8_t bus_model;
41
    uint8_t pad;
42
    uint32_t flags;
43
    int bfd_mach;
44
    void (*init_proc)(CPUPPCState *env);
45
};
46

    
47
/* For user-mode emulation, we don't emulate any IRQ controller */
48
#if defined(CONFIG_USER_ONLY)
49
#define PPC_IRQ_INIT_FN(name)                                                 \
50
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
51
{                                                                             \
52
}
53
#else
54
#define PPC_IRQ_INIT_FN(name)                                                 \
55
void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
56
#endif
57

    
58
PPC_IRQ_INIT_FN(40x);
59
PPC_IRQ_INIT_FN(6xx);
60
PPC_IRQ_INIT_FN(970);
61

    
62
/* Generic callbacks:
63
 * do nothing but store/retrieve spr value
64
 */
65
#ifdef PPC_DUMP_SPR_ACCESSES
66
static void spr_read_generic (void *opaque, int sprn)
67
{
68
    gen_op_load_dump_spr(sprn);
69
}
70

    
71
static void spr_write_generic (void *opaque, int sprn)
72
{
73
    gen_op_store_dump_spr(sprn);
74
}
75
#else
76
static void spr_read_generic (void *opaque, int sprn)
77
{
78
    gen_op_load_spr(sprn);
79
}
80

    
81
static void spr_write_generic (void *opaque, int sprn)
82
{
83
    gen_op_store_spr(sprn);
84
}
85
#endif
86

    
87
#if !defined(CONFIG_USER_ONLY)
88
static void spr_write_clear (void *opaque, int sprn)
89
{
90
    gen_op_mask_spr(sprn);
91
}
92
#endif
93

    
94
/* SPR common to all PowerPC */
95
/* XER */
96
static void spr_read_xer (void *opaque, int sprn)
97
{
98
    gen_op_load_xer();
99
}
100

    
101
static void spr_write_xer (void *opaque, int sprn)
102
{
103
    gen_op_store_xer();
104
}
105

    
106
/* LR */
107
static void spr_read_lr (void *opaque, int sprn)
108
{
109
    gen_op_load_lr();
110
}
111

    
112
static void spr_write_lr (void *opaque, int sprn)
113
{
114
    gen_op_store_lr();
115
}
116

    
117
/* CTR */
118
static void spr_read_ctr (void *opaque, int sprn)
119
{
120
    gen_op_load_ctr();
121
}
122

    
123
static void spr_write_ctr (void *opaque, int sprn)
124
{
125
    gen_op_store_ctr();
126
}
127

    
128
/* User read access to SPR */
129
/* USPRx */
130
/* UMMCRx */
131
/* UPMCx */
132
/* USIA */
133
/* UDECR */
134
static void spr_read_ureg (void *opaque, int sprn)
135
{
136
    gen_op_load_spr(sprn + 0x10);
137
}
138

    
139
/* SPR common to all non-embedded PowerPC */
140
/* DECR */
141
#if !defined(CONFIG_USER_ONLY)
142
static void spr_read_decr (void *opaque, int sprn)
143
{
144
    gen_op_load_decr();
145
}
146

    
147
static void spr_write_decr (void *opaque, int sprn)
148
{
149
    gen_op_store_decr();
150
}
151
#endif
152

    
153
/* SPR common to all non-embedded PowerPC, except 601 */
154
/* Time base */
155
static void spr_read_tbl (void *opaque, int sprn)
156
{
157
    gen_op_load_tbl();
158
}
159

    
160
static void spr_read_tbu (void *opaque, int sprn)
161
{
162
    gen_op_load_tbu();
163
}
164

    
165
__attribute__ (( unused ))
166
static void spr_read_atbl (void *opaque, int sprn)
167
{
168
    gen_op_load_atbl();
169
}
170

    
171
__attribute__ (( unused ))
172
static void spr_read_atbu (void *opaque, int sprn)
173
{
174
    gen_op_load_atbu();
175
}
176

    
177
#if !defined(CONFIG_USER_ONLY)
178
static void spr_write_tbl (void *opaque, int sprn)
179
{
180
    gen_op_store_tbl();
181
}
182

    
183
static void spr_write_tbu (void *opaque, int sprn)
184
{
185
    gen_op_store_tbu();
186
}
187

    
188
__attribute__ (( unused ))
189
static void spr_write_atbl (void *opaque, int sprn)
190
{
191
    gen_op_store_atbl();
192
}
193

    
194
__attribute__ (( unused ))
195
static void spr_write_atbu (void *opaque, int sprn)
196
{
197
    gen_op_store_atbu();
198
}
199
#endif
200

    
201
#if !defined(CONFIG_USER_ONLY)
202
/* IBAT0U...IBAT0U */
203
/* IBAT0L...IBAT7L */
204
static void spr_read_ibat (void *opaque, int sprn)
205
{
206
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
207
}
208

    
209
static void spr_read_ibat_h (void *opaque, int sprn)
210
{
211
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
212
}
213

    
214
static void spr_write_ibatu (void *opaque, int sprn)
215
{
216
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
217
}
218

    
219
static void spr_write_ibatu_h (void *opaque, int sprn)
220
{
221
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
222
}
223

    
224
static void spr_write_ibatl (void *opaque, int sprn)
225
{
226
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
227
}
228

    
229
static void spr_write_ibatl_h (void *opaque, int sprn)
230
{
231
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
232
}
233

    
234
/* DBAT0U...DBAT7U */
235
/* DBAT0L...DBAT7L */
236
static void spr_read_dbat (void *opaque, int sprn)
237
{
238
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
239
}
240

    
241
static void spr_read_dbat_h (void *opaque, int sprn)
242
{
243
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
244
}
245

    
246
static void spr_write_dbatu (void *opaque, int sprn)
247
{
248
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
249
}
250

    
251
static void spr_write_dbatu_h (void *opaque, int sprn)
252
{
253
    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
254
}
255

    
256
static void spr_write_dbatl (void *opaque, int sprn)
257
{
258
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
259
}
260

    
261
static void spr_write_dbatl_h (void *opaque, int sprn)
262
{
263
    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
264
}
265

    
266
/* SDR1 */
267
static void spr_read_sdr1 (void *opaque, int sprn)
268
{
269
    gen_op_load_sdr1();
270
}
271

    
272
static void spr_write_sdr1 (void *opaque, int sprn)
273
{
274
    gen_op_store_sdr1();
275
}
276

    
277
/* 64 bits PowerPC specific SPRs */
278
/* ASR */
279
#if defined(TARGET_PPC64)
280
__attribute__ (( unused ))
281
static void spr_read_asr (void *opaque, int sprn)
282
{
283
    gen_op_load_asr();
284
}
285

    
286
__attribute__ (( unused ))
287
static void spr_write_asr (void *opaque, int sprn)
288
{
289
    gen_op_store_asr();
290
}
291
#endif
292
#endif
293

    
294
/* PowerPC 601 specific registers */
295
/* RTC */
296
static void spr_read_601_rtcl (void *opaque, int sprn)
297
{
298
    gen_op_load_601_rtcl();
299
}
300

    
301
static void spr_read_601_rtcu (void *opaque, int sprn)
302
{
303
    gen_op_load_601_rtcu();
304
}
305

    
306
#if !defined(CONFIG_USER_ONLY)
307
static void spr_write_601_rtcu (void *opaque, int sprn)
308
{
309
    gen_op_store_601_rtcu();
310
}
311

    
312
static void spr_write_601_rtcl (void *opaque, int sprn)
313
{
314
    gen_op_store_601_rtcl();
315
}
316
#endif
317

    
318
/* Unified bats */
319
#if !defined(CONFIG_USER_ONLY)
320
static void spr_read_601_ubat (void *opaque, int sprn)
321
{
322
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
323
}
324

    
325
static void spr_write_601_ubatu (void *opaque, int sprn)
326
{
327
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
328
}
329

    
330
static void spr_write_601_ubatl (void *opaque, int sprn)
331
{
332
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
333
}
334
#endif
335

    
336
/* PowerPC 40x specific registers */
337
#if !defined(CONFIG_USER_ONLY)
338
static void spr_read_40x_pit (void *opaque, int sprn)
339
{
340
    gen_op_load_40x_pit();
341
}
342

    
343
static void spr_write_40x_pit (void *opaque, int sprn)
344
{
345
    gen_op_store_40x_pit();
346
}
347

    
348
static void spr_write_40x_dbcr0 (void *opaque, int sprn)
349
{
350
    DisasContext *ctx = opaque;
351

    
352
    gen_op_store_40x_dbcr0();
353
    /* We must stop translation as we may have rebooted */
354
    GEN_STOP(ctx);
355
}
356

    
357
static void spr_write_40x_sler (void *opaque, int sprn)
358
{
359
    gen_op_store_40x_sler();
360
}
361

    
362
static void spr_write_booke_tcr (void *opaque, int sprn)
363
{
364
    gen_op_store_booke_tcr();
365
}
366

    
367
static void spr_write_booke_tsr (void *opaque, int sprn)
368
{
369
    gen_op_store_booke_tsr();
370
}
371
#endif
372

    
373
/* PowerPC 403 specific registers */
374
/* PBL1 / PBU1 / PBL2 / PBU2 */
375
#if !defined(CONFIG_USER_ONLY)
376
static void spr_read_403_pbr (void *opaque, int sprn)
377
{
378
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
379
}
380

    
381
static void spr_write_403_pbr (void *opaque, int sprn)
382
{
383
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
384
}
385

    
386
static void spr_write_pir (void *opaque, int sprn)
387
{
388
    gen_op_store_pir();
389
}
390
#endif
391

    
392
#if !defined(CONFIG_USER_ONLY)
393
/* Callback used to write the exception vector base */
394
static void spr_write_excp_prefix (void *opaque, int sprn)
395
{
396
    gen_op_store_excp_prefix();
397
    gen_op_store_spr(sprn);
398
}
399

    
400
static void spr_write_excp_vector (void *opaque, int sprn)
401
{
402
    DisasContext *ctx = opaque;
403

    
404
    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
405
        gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
406
        gen_op_store_spr(sprn);
407
    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
408
        gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
409
        gen_op_store_spr(sprn);
410
    } else {
411
        printf("Trying to write an unknown exception vector %d %03x\n",
412
               sprn, sprn);
413
        GEN_EXCP_PRIVREG(ctx);
414
    }
415
}
416
#endif
417

    
418
#if defined(CONFIG_USER_ONLY)
419
#define spr_register(env, num, name, uea_read, uea_write,                     \
420
                     oea_read, oea_write, initial_value)                      \
421
do {                                                                          \
422
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
423
} while (0)
424
static inline void _spr_register (CPUPPCState *env, int num,
425
                                  const unsigned char *name,
426
                                  void (*uea_read)(void *opaque, int sprn),
427
                                  void (*uea_write)(void *opaque, int sprn),
428
                                  target_ulong initial_value)
429
#else
430
static inline void spr_register (CPUPPCState *env, int num,
431
                                 const unsigned char *name,
432
                                 void (*uea_read)(void *opaque, int sprn),
433
                                 void (*uea_write)(void *opaque, int sprn),
434
                                 void (*oea_read)(void *opaque, int sprn),
435
                                 void (*oea_write)(void *opaque, int sprn),
436
                                 target_ulong initial_value)
437
#endif
438
{
439
    ppc_spr_t *spr;
440

    
441
    spr = &env->spr_cb[num];
442
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
443
#if !defined(CONFIG_USER_ONLY)
444
        spr->oea_read != NULL || spr->oea_write != NULL ||
445
#endif
446
        spr->uea_read != NULL || spr->uea_write != NULL) {
447
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
448
        exit(1);
449
    }
450
#if defined(PPC_DEBUG_SPR)
451
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
452
           initial_value);
453
#endif
454
    spr->name = name;
455
    spr->uea_read = uea_read;
456
    spr->uea_write = uea_write;
457
#if !defined(CONFIG_USER_ONLY)
458
    spr->oea_read = oea_read;
459
    spr->oea_write = oea_write;
460
#endif
461
    env->spr[num] = initial_value;
462
}
463

    
464
/* Generic PowerPC SPRs */
465
static void gen_spr_generic (CPUPPCState *env)
466
{
467
    /* Integer processing */
468
    spr_register(env, SPR_XER, "XER",
469
                 &spr_read_xer, &spr_write_xer,
470
                 &spr_read_xer, &spr_write_xer,
471
                 0x00000000);
472
    /* Branch contol */
473
    spr_register(env, SPR_LR, "LR",
474
                 &spr_read_lr, &spr_write_lr,
475
                 &spr_read_lr, &spr_write_lr,
476
                 0x00000000);
477
    spr_register(env, SPR_CTR, "CTR",
478
                 &spr_read_ctr, &spr_write_ctr,
479
                 &spr_read_ctr, &spr_write_ctr,
480
                 0x00000000);
481
    /* Interrupt processing */
482
    spr_register(env, SPR_SRR0, "SRR0",
483
                 SPR_NOACCESS, SPR_NOACCESS,
484
                 &spr_read_generic, &spr_write_generic,
485
                 0x00000000);
486
    spr_register(env, SPR_SRR1, "SRR1",
487
                 SPR_NOACCESS, SPR_NOACCESS,
488
                 &spr_read_generic, &spr_write_generic,
489
                 0x00000000);
490
    /* Processor control */
491
    spr_register(env, SPR_SPRG0, "SPRG0",
492
                 SPR_NOACCESS, SPR_NOACCESS,
493
                 &spr_read_generic, &spr_write_generic,
494
                 0x00000000);
495
    spr_register(env, SPR_SPRG1, "SPRG1",
496
                 SPR_NOACCESS, SPR_NOACCESS,
497
                 &spr_read_generic, &spr_write_generic,
498
                 0x00000000);
499
    spr_register(env, SPR_SPRG2, "SPRG2",
500
                 SPR_NOACCESS, SPR_NOACCESS,
501
                 &spr_read_generic, &spr_write_generic,
502
                 0x00000000);
503
    spr_register(env, SPR_SPRG3, "SPRG3",
504
                 SPR_NOACCESS, SPR_NOACCESS,
505
                 &spr_read_generic, &spr_write_generic,
506
                 0x00000000);
507
}
508

    
509
/* SPR common to all non-embedded PowerPC, including 601 */
510
static void gen_spr_ne_601 (CPUPPCState *env)
511
{
512
    /* Exception processing */
513
    spr_register(env, SPR_DSISR, "DSISR",
514
                 SPR_NOACCESS, SPR_NOACCESS,
515
                 &spr_read_generic, &spr_write_generic,
516
                 0x00000000);
517
    spr_register(env, SPR_DAR, "DAR",
518
                 SPR_NOACCESS, SPR_NOACCESS,
519
                 &spr_read_generic, &spr_write_generic,
520
                 0x00000000);
521
    /* Timer */
522
    spr_register(env, SPR_DECR, "DECR",
523
                 SPR_NOACCESS, SPR_NOACCESS,
524
                 &spr_read_decr, &spr_write_decr,
525
                 0x00000000);
526
    /* Memory management */
527
    spr_register(env, SPR_SDR1, "SDR1",
528
                 SPR_NOACCESS, SPR_NOACCESS,
529
                 &spr_read_sdr1, &spr_write_sdr1,
530
                 0x00000000);
531
}
532

    
533
/* BATs 0-3 */
534
static void gen_low_BATs (CPUPPCState *env)
535
{
536
#if !defined(CONFIG_USER_ONLY)
537
    spr_register(env, SPR_IBAT0U, "IBAT0U",
538
                 SPR_NOACCESS, SPR_NOACCESS,
539
                 &spr_read_ibat, &spr_write_ibatu,
540
                 0x00000000);
541
    spr_register(env, SPR_IBAT0L, "IBAT0L",
542
                 SPR_NOACCESS, SPR_NOACCESS,
543
                 &spr_read_ibat, &spr_write_ibatl,
544
                 0x00000000);
545
    spr_register(env, SPR_IBAT1U, "IBAT1U",
546
                 SPR_NOACCESS, SPR_NOACCESS,
547
                 &spr_read_ibat, &spr_write_ibatu,
548
                 0x00000000);
549
    spr_register(env, SPR_IBAT1L, "IBAT1L",
550
                 SPR_NOACCESS, SPR_NOACCESS,
551
                 &spr_read_ibat, &spr_write_ibatl,
552
                 0x00000000);
553
    spr_register(env, SPR_IBAT2U, "IBAT2U",
554
                 SPR_NOACCESS, SPR_NOACCESS,
555
                 &spr_read_ibat, &spr_write_ibatu,
556
                 0x00000000);
557
    spr_register(env, SPR_IBAT2L, "IBAT2L",
558
                 SPR_NOACCESS, SPR_NOACCESS,
559
                 &spr_read_ibat, &spr_write_ibatl,
560
                 0x00000000);
561
    spr_register(env, SPR_IBAT3U, "IBAT3U",
562
                 SPR_NOACCESS, SPR_NOACCESS,
563
                 &spr_read_ibat, &spr_write_ibatu,
564
                 0x00000000);
565
    spr_register(env, SPR_IBAT3L, "IBAT3L",
566
                 SPR_NOACCESS, SPR_NOACCESS,
567
                 &spr_read_ibat, &spr_write_ibatl,
568
                 0x00000000);
569
    spr_register(env, SPR_DBAT0U, "DBAT0U",
570
                 SPR_NOACCESS, SPR_NOACCESS,
571
                 &spr_read_dbat, &spr_write_dbatu,
572
                 0x00000000);
573
    spr_register(env, SPR_DBAT0L, "DBAT0L",
574
                 SPR_NOACCESS, SPR_NOACCESS,
575
                 &spr_read_dbat, &spr_write_dbatl,
576
                 0x00000000);
577
    spr_register(env, SPR_DBAT1U, "DBAT1U",
578
                 SPR_NOACCESS, SPR_NOACCESS,
579
                 &spr_read_dbat, &spr_write_dbatu,
580
                 0x00000000);
581
    spr_register(env, SPR_DBAT1L, "DBAT1L",
582
                 SPR_NOACCESS, SPR_NOACCESS,
583
                 &spr_read_dbat, &spr_write_dbatl,
584
                 0x00000000);
585
    spr_register(env, SPR_DBAT2U, "DBAT2U",
586
                 SPR_NOACCESS, SPR_NOACCESS,
587
                 &spr_read_dbat, &spr_write_dbatu,
588
                 0x00000000);
589
    spr_register(env, SPR_DBAT2L, "DBAT2L",
590
                 SPR_NOACCESS, SPR_NOACCESS,
591
                 &spr_read_dbat, &spr_write_dbatl,
592
                 0x00000000);
593
    spr_register(env, SPR_DBAT3U, "DBAT3U",
594
                 SPR_NOACCESS, SPR_NOACCESS,
595
                 &spr_read_dbat, &spr_write_dbatu,
596
                 0x00000000);
597
    spr_register(env, SPR_DBAT3L, "DBAT3L",
598
                 SPR_NOACCESS, SPR_NOACCESS,
599
                 &spr_read_dbat, &spr_write_dbatl,
600
                 0x00000000);
601
    env->nb_BATs += 4;
602
#endif
603
}
604

    
605
/* BATs 4-7 */
606
static void gen_high_BATs (CPUPPCState *env)
607
{
608
#if !defined(CONFIG_USER_ONLY)
609
    spr_register(env, SPR_IBAT4U, "IBAT4U",
610
                 SPR_NOACCESS, SPR_NOACCESS,
611
                 &spr_read_ibat_h, &spr_write_ibatu_h,
612
                 0x00000000);
613
    spr_register(env, SPR_IBAT4L, "IBAT4L",
614
                 SPR_NOACCESS, SPR_NOACCESS,
615
                 &spr_read_ibat_h, &spr_write_ibatl_h,
616
                 0x00000000);
617
    spr_register(env, SPR_IBAT5U, "IBAT5U",
618
                 SPR_NOACCESS, SPR_NOACCESS,
619
                 &spr_read_ibat_h, &spr_write_ibatu_h,
620
                 0x00000000);
621
    spr_register(env, SPR_IBAT5L, "IBAT5L",
622
                 SPR_NOACCESS, SPR_NOACCESS,
623
                 &spr_read_ibat_h, &spr_write_ibatl_h,
624
                 0x00000000);
625
    spr_register(env, SPR_IBAT6U, "IBAT6U",
626
                 SPR_NOACCESS, SPR_NOACCESS,
627
                 &spr_read_ibat_h, &spr_write_ibatu_h,
628
                 0x00000000);
629
    spr_register(env, SPR_IBAT6L, "IBAT6L",
630
                 SPR_NOACCESS, SPR_NOACCESS,
631
                 &spr_read_ibat_h, &spr_write_ibatl_h,
632
                 0x00000000);
633
    spr_register(env, SPR_IBAT7U, "IBAT7U",
634
                 SPR_NOACCESS, SPR_NOACCESS,
635
                 &spr_read_ibat_h, &spr_write_ibatu_h,
636
                 0x00000000);
637
    spr_register(env, SPR_IBAT7L, "IBAT7L",
638
                 SPR_NOACCESS, SPR_NOACCESS,
639
                 &spr_read_ibat_h, &spr_write_ibatl_h,
640
                 0x00000000);
641
    spr_register(env, SPR_DBAT4U, "DBAT4U",
642
                 SPR_NOACCESS, SPR_NOACCESS,
643
                 &spr_read_dbat_h, &spr_write_dbatu_h,
644
                 0x00000000);
645
    spr_register(env, SPR_DBAT4L, "DBAT4L",
646
                 SPR_NOACCESS, SPR_NOACCESS,
647
                 &spr_read_dbat_h, &spr_write_dbatl_h,
648
                 0x00000000);
649
    spr_register(env, SPR_DBAT5U, "DBAT5U",
650
                 SPR_NOACCESS, SPR_NOACCESS,
651
                 &spr_read_dbat_h, &spr_write_dbatu_h,
652
                 0x00000000);
653
    spr_register(env, SPR_DBAT5L, "DBAT5L",
654
                 SPR_NOACCESS, SPR_NOACCESS,
655
                 &spr_read_dbat_h, &spr_write_dbatl_h,
656
                 0x00000000);
657
    spr_register(env, SPR_DBAT6U, "DBAT6U",
658
                 SPR_NOACCESS, SPR_NOACCESS,
659
                 &spr_read_dbat_h, &spr_write_dbatu_h,
660
                 0x00000000);
661
    spr_register(env, SPR_DBAT6L, "DBAT6L",
662
                 SPR_NOACCESS, SPR_NOACCESS,
663
                 &spr_read_dbat_h, &spr_write_dbatl_h,
664
                 0x00000000);
665
    spr_register(env, SPR_DBAT7U, "DBAT7U",
666
                 SPR_NOACCESS, SPR_NOACCESS,
667
                 &spr_read_dbat_h, &spr_write_dbatu_h,
668
                 0x00000000);
669
    spr_register(env, SPR_DBAT7L, "DBAT7L",
670
                 SPR_NOACCESS, SPR_NOACCESS,
671
                 &spr_read_dbat_h, &spr_write_dbatl_h,
672
                 0x00000000);
673
    env->nb_BATs += 4;
674
#endif
675
}
676

    
677
/* Generic PowerPC time base */
678
static void gen_tbl (CPUPPCState *env)
679
{
680
    spr_register(env, SPR_VTBL,  "TBL",
681
                 &spr_read_tbl, SPR_NOACCESS,
682
                 &spr_read_tbl, SPR_NOACCESS,
683
                 0x00000000);
684
    spr_register(env, SPR_TBL,   "TBL",
685
                 SPR_NOACCESS, SPR_NOACCESS,
686
                 SPR_NOACCESS, &spr_write_tbl,
687
                 0x00000000);
688
    spr_register(env, SPR_VTBU,  "TBU",
689
                 &spr_read_tbu, SPR_NOACCESS,
690
                 &spr_read_tbu, SPR_NOACCESS,
691
                 0x00000000);
692
    spr_register(env, SPR_TBU,   "TBU",
693
                 SPR_NOACCESS, SPR_NOACCESS,
694
                 SPR_NOACCESS, &spr_write_tbu,
695
                 0x00000000);
696
}
697

    
698
/* Softare table search registers */
699
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
700
{
701
#if !defined(CONFIG_USER_ONLY)
702
    env->nb_tlb = nb_tlbs;
703
    env->nb_ways = nb_ways;
704
    env->id_tlbs = 1;
705
    spr_register(env, SPR_DMISS, "DMISS",
706
                 SPR_NOACCESS, SPR_NOACCESS,
707
                 &spr_read_generic, SPR_NOACCESS,
708
                 0x00000000);
709
    spr_register(env, SPR_DCMP, "DCMP",
710
                 SPR_NOACCESS, SPR_NOACCESS,
711
                 &spr_read_generic, SPR_NOACCESS,
712
                 0x00000000);
713
    spr_register(env, SPR_HASH1, "HASH1",
714
                 SPR_NOACCESS, SPR_NOACCESS,
715
                 &spr_read_generic, SPR_NOACCESS,
716
                 0x00000000);
717
    spr_register(env, SPR_HASH2, "HASH2",
718
                 SPR_NOACCESS, SPR_NOACCESS,
719
                 &spr_read_generic, SPR_NOACCESS,
720
                 0x00000000);
721
    spr_register(env, SPR_IMISS, "IMISS",
722
                 SPR_NOACCESS, SPR_NOACCESS,
723
                 &spr_read_generic, SPR_NOACCESS,
724
                 0x00000000);
725
    spr_register(env, SPR_ICMP, "ICMP",
726
                 SPR_NOACCESS, SPR_NOACCESS,
727
                 &spr_read_generic, SPR_NOACCESS,
728
                 0x00000000);
729
    spr_register(env, SPR_RPA, "RPA",
730
                 SPR_NOACCESS, SPR_NOACCESS,
731
                 &spr_read_generic, &spr_write_generic,
732
                 0x00000000);
733
#endif
734
}
735

    
736
/* SPR common to MPC755 and G2 */
737
static void gen_spr_G2_755 (CPUPPCState *env)
738
{
739
    /* SGPRs */
740
    spr_register(env, SPR_SPRG4, "SPRG4",
741
                 SPR_NOACCESS, SPR_NOACCESS,
742
                 &spr_read_generic, &spr_write_generic,
743
                 0x00000000);
744
    spr_register(env, SPR_SPRG5, "SPRG5",
745
                 SPR_NOACCESS, SPR_NOACCESS,
746
                 &spr_read_generic, &spr_write_generic,
747
                 0x00000000);
748
    spr_register(env, SPR_SPRG6, "SPRG6",
749
                 SPR_NOACCESS, SPR_NOACCESS,
750
                 &spr_read_generic, &spr_write_generic,
751
                 0x00000000);
752
    spr_register(env, SPR_SPRG7, "SPRG7",
753
                 SPR_NOACCESS, SPR_NOACCESS,
754
                 &spr_read_generic, &spr_write_generic,
755
                 0x00000000);
756
    /* External access control */
757
    /* XXX : not implemented */
758
    spr_register(env, SPR_EAR, "EAR",
759
                 SPR_NOACCESS, SPR_NOACCESS,
760
                 &spr_read_generic, &spr_write_generic,
761
                 0x00000000);
762
}
763

    
764
/* SPR common to all 7xx PowerPC implementations */
765
static void gen_spr_7xx (CPUPPCState *env)
766
{
767
    /* Breakpoints */
768
    /* XXX : not implemented */
769
    spr_register(env, SPR_DABR, "DABR",
770
                 SPR_NOACCESS, SPR_NOACCESS,
771
                 &spr_read_generic, &spr_write_generic,
772
                 0x00000000);
773
    /* XXX : not implemented */
774
    spr_register(env, SPR_IABR, "IABR",
775
                 SPR_NOACCESS, SPR_NOACCESS,
776
                 &spr_read_generic, &spr_write_generic,
777
                 0x00000000);
778
    /* Cache management */
779
    /* XXX : not implemented */
780
    spr_register(env, SPR_ICTC, "ICTC",
781
                 SPR_NOACCESS, SPR_NOACCESS,
782
                 &spr_read_generic, &spr_write_generic,
783
                 0x00000000);
784
    /* XXX : not implemented */
785
    spr_register(env, SPR_L2CR, "L2CR",
786
                 SPR_NOACCESS, SPR_NOACCESS,
787
                 &spr_read_generic, &spr_write_generic,
788
                 0x00000000);
789
    /* Performance monitors */
790
    /* XXX : not implemented */
791
    spr_register(env, SPR_MMCR0, "MMCR0",
792
                 SPR_NOACCESS, SPR_NOACCESS,
793
                 &spr_read_generic, &spr_write_generic,
794
                 0x00000000);
795
    /* XXX : not implemented */
796
    spr_register(env, SPR_MMCR1, "MMCR1",
797
                 SPR_NOACCESS, SPR_NOACCESS,
798
                 &spr_read_generic, &spr_write_generic,
799
                 0x00000000);
800
    /* XXX : not implemented */
801
    spr_register(env, SPR_PMC1, "PMC1",
802
                 SPR_NOACCESS, SPR_NOACCESS,
803
                 &spr_read_generic, &spr_write_generic,
804
                 0x00000000);
805
    /* XXX : not implemented */
806
    spr_register(env, SPR_PMC2, "PMC2",
807
                 SPR_NOACCESS, SPR_NOACCESS,
808
                 &spr_read_generic, &spr_write_generic,
809
                 0x00000000);
810
    /* XXX : not implemented */
811
    spr_register(env, SPR_PMC3, "PMC3",
812
                 SPR_NOACCESS, SPR_NOACCESS,
813
                 &spr_read_generic, &spr_write_generic,
814
                 0x00000000);
815
    /* XXX : not implemented */
816
    spr_register(env, SPR_PMC4, "PMC4",
817
                 SPR_NOACCESS, SPR_NOACCESS,
818
                 &spr_read_generic, &spr_write_generic,
819
                 0x00000000);
820
    /* XXX : not implemented */
821
    spr_register(env, SPR_SIAR, "SIAR",
822
                 SPR_NOACCESS, SPR_NOACCESS,
823
                 &spr_read_generic, SPR_NOACCESS,
824
                 0x00000000);
825
    /* XXX : not implemented */
826
    spr_register(env, SPR_UMMCR0, "UMMCR0",
827
                 &spr_read_ureg, SPR_NOACCESS,
828
                 &spr_read_ureg, SPR_NOACCESS,
829
                 0x00000000);
830
    /* XXX : not implemented */
831
    spr_register(env, SPR_UMMCR1, "UMMCR1",
832
                 &spr_read_ureg, SPR_NOACCESS,
833
                 &spr_read_ureg, SPR_NOACCESS,
834
                 0x00000000);
835
    /* XXX : not implemented */
836
    spr_register(env, SPR_UPMC1, "UPMC1",
837
                 &spr_read_ureg, SPR_NOACCESS,
838
                 &spr_read_ureg, SPR_NOACCESS,
839
                 0x00000000);
840
    /* XXX : not implemented */
841
    spr_register(env, SPR_UPMC2, "UPMC2",
842
                 &spr_read_ureg, SPR_NOACCESS,
843
                 &spr_read_ureg, SPR_NOACCESS,
844
                 0x00000000);
845
    /* XXX : not implemented */
846
    spr_register(env, SPR_UPMC3, "UPMC3",
847
                 &spr_read_ureg, SPR_NOACCESS,
848
                 &spr_read_ureg, SPR_NOACCESS,
849
                 0x00000000);
850
    /* XXX : not implemented */
851
    spr_register(env, SPR_UPMC4, "UPMC4",
852
                 &spr_read_ureg, SPR_NOACCESS,
853
                 &spr_read_ureg, SPR_NOACCESS,
854
                 0x00000000);
855
    /* XXX : not implemented */
856
    spr_register(env, SPR_USIAR, "USIAR",
857
                 &spr_read_ureg, SPR_NOACCESS,
858
                 &spr_read_ureg, SPR_NOACCESS,
859
                 0x00000000);
860
    /* External access control */
861
    /* XXX : not implemented */
862
    spr_register(env, SPR_EAR, "EAR",
863
                 SPR_NOACCESS, SPR_NOACCESS,
864
                 &spr_read_generic, &spr_write_generic,
865
                 0x00000000);
866
}
867

    
868
static void gen_spr_thrm (CPUPPCState *env)
869
{
870
    /* Thermal management */
871
    /* XXX : not implemented */
872
    spr_register(env, SPR_THRM1, "THRM1",
873
                 SPR_NOACCESS, SPR_NOACCESS,
874
                 &spr_read_generic, &spr_write_generic,
875
                 0x00000000);
876
    /* XXX : not implemented */
877
    spr_register(env, SPR_THRM2, "THRM2",
878
                 SPR_NOACCESS, SPR_NOACCESS,
879
                 &spr_read_generic, &spr_write_generic,
880
                 0x00000000);
881
    /* XXX : not implemented */
882
    spr_register(env, SPR_THRM3, "THRM3",
883
                 SPR_NOACCESS, SPR_NOACCESS,
884
                 &spr_read_generic, &spr_write_generic,
885
                 0x00000000);
886
}
887

    
888
/* SPR specific to PowerPC 604 implementation */
889
static void gen_spr_604 (CPUPPCState *env)
890
{
891
    /* Processor identification */
892
    spr_register(env, SPR_PIR, "PIR",
893
                 SPR_NOACCESS, SPR_NOACCESS,
894
                 &spr_read_generic, &spr_write_pir,
895
                 0x00000000);
896
    /* Breakpoints */
897
    /* XXX : not implemented */
898
    spr_register(env, SPR_IABR, "IABR",
899
                 SPR_NOACCESS, SPR_NOACCESS,
900
                 &spr_read_generic, &spr_write_generic,
901
                 0x00000000);
902
    /* XXX : not implemented */
903
    spr_register(env, SPR_DABR, "DABR",
904
                 SPR_NOACCESS, SPR_NOACCESS,
905
                 &spr_read_generic, &spr_write_generic,
906
                 0x00000000);
907
    /* Performance counters */
908
    /* XXX : not implemented */
909
    spr_register(env, SPR_MMCR0, "MMCR0",
910
                 SPR_NOACCESS, SPR_NOACCESS,
911
                 &spr_read_generic, &spr_write_generic,
912
                 0x00000000);
913
    /* XXX : not implemented */
914
    spr_register(env, SPR_MMCR1, "MMCR1",
915
                 SPR_NOACCESS, SPR_NOACCESS,
916
                 &spr_read_generic, &spr_write_generic,
917
                 0x00000000);
918
    /* XXX : not implemented */
919
    spr_register(env, SPR_PMC1, "PMC1",
920
                 SPR_NOACCESS, SPR_NOACCESS,
921
                 &spr_read_generic, &spr_write_generic,
922
                 0x00000000);
923
    /* XXX : not implemented */
924
    spr_register(env, SPR_PMC2, "PMC2",
925
                 SPR_NOACCESS, SPR_NOACCESS,
926
                 &spr_read_generic, &spr_write_generic,
927
                 0x00000000);
928
    /* XXX : not implemented */
929
    spr_register(env, SPR_PMC3, "PMC3",
930
                 SPR_NOACCESS, SPR_NOACCESS,
931
                 &spr_read_generic, &spr_write_generic,
932
                 0x00000000);
933
    /* XXX : not implemented */
934
    spr_register(env, SPR_PMC4, "PMC4",
935
                 SPR_NOACCESS, SPR_NOACCESS,
936
                 &spr_read_generic, &spr_write_generic,
937
                 0x00000000);
938
    /* XXX : not implemented */
939
    spr_register(env, SPR_SIAR, "SIAR",
940
                 SPR_NOACCESS, SPR_NOACCESS,
941
                 &spr_read_generic, SPR_NOACCESS,
942
                 0x00000000);
943
    /* XXX : not implemented */
944
    spr_register(env, SPR_SDA, "SDA",
945
                 SPR_NOACCESS, SPR_NOACCESS,
946
                 &spr_read_generic, SPR_NOACCESS,
947
                 0x00000000);
948
    /* External access control */
949
    /* XXX : not implemented */
950
    spr_register(env, SPR_EAR, "EAR",
951
                 SPR_NOACCESS, SPR_NOACCESS,
952
                 &spr_read_generic, &spr_write_generic,
953
                 0x00000000);
954
}
955

    
956
/* SPR specific to PowerPC 603 implementation */
957
static void gen_spr_603 (CPUPPCState *env)
958
{
959
    /* External access control */
960
    /* XXX : not implemented */
961
    spr_register(env, SPR_EAR, "EAR",
962
                 SPR_NOACCESS, SPR_NOACCESS,
963
                 &spr_read_generic, &spr_write_generic,
964
                 0x00000000);
965
}
966

    
967
/* SPR specific to PowerPC G2 implementation */
968
static void gen_spr_G2 (CPUPPCState *env)
969
{
970
    /* Memory base address */
971
    /* MBAR */
972
    /* XXX : not implemented */
973
    spr_register(env, SPR_MBAR, "MBAR",
974
                 SPR_NOACCESS, SPR_NOACCESS,
975
                 &spr_read_generic, &spr_write_generic,
976
                 0x00000000);
977
    /* System version register */
978
    /* SVR */
979
    /* XXX : TODO: initialize it to an appropriate value */
980
    spr_register(env, SPR_SVR, "SVR",
981
                 SPR_NOACCESS, SPR_NOACCESS,
982
                 &spr_read_generic, SPR_NOACCESS,
983
                 0x00000000);
984
    /* Exception processing */
985
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
986
                 SPR_NOACCESS, SPR_NOACCESS,
987
                 &spr_read_generic, &spr_write_generic,
988
                 0x00000000);
989
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
990
                 SPR_NOACCESS, SPR_NOACCESS,
991
                 &spr_read_generic, &spr_write_generic,
992
                 0x00000000);
993
    /* Breakpoints */
994
    /* XXX : not implemented */
995
    spr_register(env, SPR_DABR, "DABR",
996
                 SPR_NOACCESS, SPR_NOACCESS,
997
                 &spr_read_generic, &spr_write_generic,
998
                 0x00000000);
999
    /* XXX : not implemented */
1000
    spr_register(env, SPR_DABR2, "DABR2",
1001
                 SPR_NOACCESS, SPR_NOACCESS,
1002
                 &spr_read_generic, &spr_write_generic,
1003
                 0x00000000);
1004
    /* XXX : not implemented */
1005
    spr_register(env, SPR_IABR, "IABR",
1006
                 SPR_NOACCESS, SPR_NOACCESS,
1007
                 &spr_read_generic, &spr_write_generic,
1008
                 0x00000000);
1009
    /* XXX : not implemented */
1010
    spr_register(env, SPR_IABR2, "IABR2",
1011
                 SPR_NOACCESS, SPR_NOACCESS,
1012
                 &spr_read_generic, &spr_write_generic,
1013
                 0x00000000);
1014
    /* XXX : not implemented */
1015
    spr_register(env, SPR_IBCR, "IBCR",
1016
                 SPR_NOACCESS, SPR_NOACCESS,
1017
                 &spr_read_generic, &spr_write_generic,
1018
                 0x00000000);
1019
    /* XXX : not implemented */
1020
    spr_register(env, SPR_DBCR, "DBCR",
1021
                 SPR_NOACCESS, SPR_NOACCESS,
1022
                 &spr_read_generic, &spr_write_generic,
1023
                 0x00000000);
1024
}
1025

    
1026
/* SPR specific to PowerPC 602 implementation */
1027
static void gen_spr_602 (CPUPPCState *env)
1028
{
1029
    /* ESA registers */
1030
    /* XXX : not implemented */
1031
    spr_register(env, SPR_SER, "SER",
1032
                 SPR_NOACCESS, SPR_NOACCESS,
1033
                 &spr_read_generic, &spr_write_generic,
1034
                 0x00000000);
1035
    /* XXX : not implemented */
1036
    spr_register(env, SPR_SEBR, "SEBR",
1037
                 SPR_NOACCESS, SPR_NOACCESS,
1038
                 &spr_read_generic, &spr_write_generic,
1039
                 0x00000000);
1040
    /* XXX : not implemented */
1041
    spr_register(env, SPR_ESASRR, "ESASRR",
1042
                 SPR_NOACCESS, SPR_NOACCESS,
1043
                 &spr_read_generic, &spr_write_generic,
1044
                 0x00000000);
1045
    /* Floating point status */
1046
    /* XXX : not implemented */
1047
    spr_register(env, SPR_SP, "SP",
1048
                 SPR_NOACCESS, SPR_NOACCESS,
1049
                 &spr_read_generic, &spr_write_generic,
1050
                 0x00000000);
1051
    /* XXX : not implemented */
1052
    spr_register(env, SPR_LT, "LT",
1053
                 SPR_NOACCESS, SPR_NOACCESS,
1054
                 &spr_read_generic, &spr_write_generic,
1055
                 0x00000000);
1056
    /* Watchdog timer */
1057
    /* XXX : not implemented */
1058
    spr_register(env, SPR_TCR, "TCR",
1059
                 SPR_NOACCESS, SPR_NOACCESS,
1060
                 &spr_read_generic, &spr_write_generic,
1061
                 0x00000000);
1062
    /* Interrupt base */
1063
    spr_register(env, SPR_IBR, "IBR",
1064
                 SPR_NOACCESS, SPR_NOACCESS,
1065
                 &spr_read_generic, &spr_write_generic,
1066
                 0x00000000);
1067
    /* XXX : not implemented */
1068
    spr_register(env, SPR_IABR, "IABR",
1069
                 SPR_NOACCESS, SPR_NOACCESS,
1070
                 &spr_read_generic, &spr_write_generic,
1071
                 0x00000000);
1072
}
1073

    
1074
/* SPR specific to PowerPC 601 implementation */
1075
static void gen_spr_601 (CPUPPCState *env)
1076
{
1077
    /* Multiplication/division register */
1078
    /* MQ */
1079
    spr_register(env, SPR_MQ, "MQ",
1080
                 &spr_read_generic, &spr_write_generic,
1081
                 &spr_read_generic, &spr_write_generic,
1082
                 0x00000000);
1083
    /* RTC registers */
1084
    spr_register(env, SPR_601_RTCU, "RTCU",
1085
                 SPR_NOACCESS, SPR_NOACCESS,
1086
                 SPR_NOACCESS, &spr_write_601_rtcu,
1087
                 0x00000000);
1088
    spr_register(env, SPR_601_VRTCU, "RTCU",
1089
                 &spr_read_601_rtcu, SPR_NOACCESS,
1090
                 &spr_read_601_rtcu, SPR_NOACCESS,
1091
                 0x00000000);
1092
    spr_register(env, SPR_601_RTCL, "RTCL",
1093
                 SPR_NOACCESS, SPR_NOACCESS,
1094
                 SPR_NOACCESS, &spr_write_601_rtcl,
1095
                 0x00000000);
1096
    spr_register(env, SPR_601_VRTCL, "RTCL",
1097
                 &spr_read_601_rtcl, SPR_NOACCESS,
1098
                 &spr_read_601_rtcl, SPR_NOACCESS,
1099
                 0x00000000);
1100
    /* Timer */
1101
#if 0 /* ? */
1102
    spr_register(env, SPR_601_UDECR, "UDECR",
1103
                 &spr_read_decr, SPR_NOACCESS,
1104
                 &spr_read_decr, SPR_NOACCESS,
1105
                 0x00000000);
1106
#endif
1107
    /* External access control */
1108
    /* XXX : not implemented */
1109
    spr_register(env, SPR_EAR, "EAR",
1110
                 SPR_NOACCESS, SPR_NOACCESS,
1111
                 &spr_read_generic, &spr_write_generic,
1112
                 0x00000000);
1113
    /* Memory management */
1114
#if !defined(CONFIG_USER_ONLY)
1115
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1116
                 SPR_NOACCESS, SPR_NOACCESS,
1117
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1118
                 0x00000000);
1119
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1120
                 SPR_NOACCESS, SPR_NOACCESS,
1121
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1122
                 0x00000000);
1123
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1124
                 SPR_NOACCESS, SPR_NOACCESS,
1125
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1126
                 0x00000000);
1127
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1128
                 SPR_NOACCESS, SPR_NOACCESS,
1129
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1130
                 0x00000000);
1131
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1132
                 SPR_NOACCESS, SPR_NOACCESS,
1133
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1134
                 0x00000000);
1135
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1136
                 SPR_NOACCESS, SPR_NOACCESS,
1137
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1138
                 0x00000000);
1139
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1140
                 SPR_NOACCESS, SPR_NOACCESS,
1141
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1142
                 0x00000000);
1143
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1144
                 SPR_NOACCESS, SPR_NOACCESS,
1145
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1146
                 0x00000000);
1147
    env->nb_BATs = 4;
1148
#endif
1149
}
1150

    
1151
static void gen_spr_74xx (CPUPPCState *env)
1152
{
1153
    /* Processor identification */
1154
    spr_register(env, SPR_PIR, "PIR",
1155
                 SPR_NOACCESS, SPR_NOACCESS,
1156
                 &spr_read_generic, &spr_write_pir,
1157
                 0x00000000);
1158
    /* XXX : not implemented */
1159
    spr_register(env, SPR_MMCR2, "MMCR2",
1160
                 SPR_NOACCESS, SPR_NOACCESS,
1161
                 &spr_read_generic, &spr_write_generic,
1162
                 0x00000000);
1163
    /* XXX : not implemented */
1164
    spr_register(env, SPR_UMMCR2, "UMMCR2",
1165
                 &spr_read_ureg, SPR_NOACCESS,
1166
                 &spr_read_ureg, SPR_NOACCESS,
1167
                 0x00000000);
1168
    /* XXX: not implemented */
1169
    spr_register(env, SPR_BAMR, "BAMR",
1170
                 SPR_NOACCESS, SPR_NOACCESS,
1171
                 &spr_read_generic, &spr_write_generic,
1172
                 0x00000000);
1173
    /* XXX : not implemented */
1174
    spr_register(env, SPR_UBAMR, "UBAMR",
1175
                 &spr_read_ureg, SPR_NOACCESS,
1176
                 &spr_read_ureg, SPR_NOACCESS,
1177
                 0x00000000);
1178
    /* XXX : not implemented */
1179
    spr_register(env, SPR_MSSCR0, "MSSCR0",
1180
                 SPR_NOACCESS, SPR_NOACCESS,
1181
                 &spr_read_generic, &spr_write_generic,
1182
                 0x00000000);
1183
    /* Hardware implementation registers */
1184
    /* XXX : not implemented */
1185
    spr_register(env, SPR_HID0, "HID0",
1186
                 SPR_NOACCESS, SPR_NOACCESS,
1187
                 &spr_read_generic, &spr_write_generic,
1188
                 0x00000000);
1189
    /* XXX : not implemented */
1190
    spr_register(env, SPR_HID1, "HID1",
1191
                 SPR_NOACCESS, SPR_NOACCESS,
1192
                 &spr_read_generic, &spr_write_generic,
1193
                 0x00000000);
1194
    /* Altivec */
1195
    spr_register(env, SPR_VRSAVE, "VRSAVE",
1196
                 &spr_read_generic, &spr_write_generic,
1197
                 &spr_read_generic, &spr_write_generic,
1198
                 0x00000000);
1199
}
1200

    
1201
static void gen_l3_ctrl (CPUPPCState *env)
1202
{
1203
    /* L3CR */
1204
    /* XXX : not implemented */
1205
    spr_register(env, SPR_L3CR, "L3CR",
1206
                 SPR_NOACCESS, SPR_NOACCESS,
1207
                 &spr_read_generic, &spr_write_generic,
1208
                 0x00000000);
1209
    /* L3ITCR0 */
1210
    /* XXX : not implemented */
1211
    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1212
                 SPR_NOACCESS, SPR_NOACCESS,
1213
                 &spr_read_generic, &spr_write_generic,
1214
                 0x00000000);
1215
    /* L3ITCR1 */
1216
    /* XXX : not implemented */
1217
    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1218
                 SPR_NOACCESS, SPR_NOACCESS,
1219
                 &spr_read_generic, &spr_write_generic,
1220
                 0x00000000);
1221
    /* L3ITCR2 */
1222
    /* XXX : not implemented */
1223
    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1224
                 SPR_NOACCESS, SPR_NOACCESS,
1225
                 &spr_read_generic, &spr_write_generic,
1226
                 0x00000000);
1227
    /* L3ITCR3 */
1228
    /* XXX : not implemented */
1229
    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1230
                 SPR_NOACCESS, SPR_NOACCESS,
1231
                 &spr_read_generic, &spr_write_generic,
1232
                 0x00000000);
1233
    /* L3OHCR */
1234
    /* XXX : not implemented */
1235
    spr_register(env, SPR_L3OHCR, "L3OHCR",
1236
                 SPR_NOACCESS, SPR_NOACCESS,
1237
                 &spr_read_generic, &spr_write_generic,
1238
                 0x00000000);
1239
    /* L3PM */
1240
    /* XXX : not implemented */
1241
    spr_register(env, SPR_L3PM, "L3PM",
1242
                 SPR_NOACCESS, SPR_NOACCESS,
1243
                 &spr_read_generic, &spr_write_generic,
1244
                 0x00000000);
1245
}
1246

    
1247
static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1248
{
1249
#if !defined(CONFIG_USER_ONLY)
1250
    env->nb_tlb = nb_tlbs;
1251
    env->nb_ways = nb_ways;
1252
    env->id_tlbs = 1;
1253
    /* XXX : not implemented */
1254
    spr_register(env, SPR_PTEHI, "PTEHI",
1255
                 SPR_NOACCESS, SPR_NOACCESS,
1256
                 &spr_read_generic, &spr_write_generic,
1257
                 0x00000000);
1258
    /* XXX : not implemented */
1259
    spr_register(env, SPR_PTELO, "PTELO",
1260
                 SPR_NOACCESS, SPR_NOACCESS,
1261
                 &spr_read_generic, &spr_write_generic,
1262
                 0x00000000);
1263
    /* XXX : not implemented */
1264
    spr_register(env, SPR_TLBMISS, "TLBMISS",
1265
                 SPR_NOACCESS, SPR_NOACCESS,
1266
                 &spr_read_generic, &spr_write_generic,
1267
                 0x00000000);
1268
#endif
1269
}
1270

    
1271
/* PowerPC BookE SPR */
1272
static void gen_spr_BookE (CPUPPCState *env)
1273
{
1274
    /* Processor identification */
1275
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1276
                 SPR_NOACCESS, SPR_NOACCESS,
1277
                 &spr_read_generic, &spr_write_pir,
1278
                 0x00000000);
1279
    /* Interrupt processing */
1280
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1281
                 SPR_NOACCESS, SPR_NOACCESS,
1282
                 &spr_read_generic, &spr_write_generic,
1283
                 0x00000000);
1284
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1285
                 SPR_NOACCESS, SPR_NOACCESS,
1286
                 &spr_read_generic, &spr_write_generic,
1287
                 0x00000000);
1288
#if 0
1289
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1290
                 SPR_NOACCESS, SPR_NOACCESS,
1291
                 &spr_read_generic, &spr_write_generic,
1292
                 0x00000000);
1293
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1294
                 SPR_NOACCESS, SPR_NOACCESS,
1295
                 &spr_read_generic, &spr_write_generic,
1296
                 0x00000000);
1297
#endif
1298
    /* Debug */
1299
    /* XXX : not implemented */
1300
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1301
                 SPR_NOACCESS, SPR_NOACCESS,
1302
                 &spr_read_generic, &spr_write_generic,
1303
                 0x00000000);
1304
    /* XXX : not implemented */
1305
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1306
                 SPR_NOACCESS, SPR_NOACCESS,
1307
                 &spr_read_generic, &spr_write_generic,
1308
                 0x00000000);
1309
    /* XXX : not implemented */
1310
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1311
                 SPR_NOACCESS, SPR_NOACCESS,
1312
                 &spr_read_generic, &spr_write_generic,
1313
                 0x00000000);
1314
    /* XXX : not implemented */
1315
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1316
                 SPR_NOACCESS, SPR_NOACCESS,
1317
                 &spr_read_generic, &spr_write_generic,
1318
                 0x00000000);
1319
    /* XXX : not implemented */
1320
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1321
                 SPR_NOACCESS, SPR_NOACCESS,
1322
                 &spr_read_generic, &spr_write_generic,
1323
                 0x00000000);
1324
    /* XXX : not implemented */
1325
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1326
                 SPR_NOACCESS, SPR_NOACCESS,
1327
                 &spr_read_generic, &spr_write_generic,
1328
                 0x00000000);
1329
    /* XXX : not implemented */
1330
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1331
                 SPR_NOACCESS, SPR_NOACCESS,
1332
                 &spr_read_generic, &spr_write_generic,
1333
                 0x00000000);
1334
    /* XXX : not implemented */
1335
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1336
                 SPR_NOACCESS, SPR_NOACCESS,
1337
                 &spr_read_generic, &spr_write_generic,
1338
                 0x00000000);
1339
    /* XXX : not implemented */
1340
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1341
                 SPR_NOACCESS, SPR_NOACCESS,
1342
                 &spr_read_generic, &spr_write_generic,
1343
                 0x00000000);
1344
    /* XXX : not implemented */
1345
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1346
                 SPR_NOACCESS, SPR_NOACCESS,
1347
                 &spr_read_generic, &spr_write_generic,
1348
                 0x00000000);
1349
    /* XXX : not implemented */
1350
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1351
                 SPR_NOACCESS, SPR_NOACCESS,
1352
                 &spr_read_generic, &spr_write_generic,
1353
                 0x00000000);
1354
    /* XXX : not implemented */
1355
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1356
                 SPR_NOACCESS, SPR_NOACCESS,
1357
                 &spr_read_generic, &spr_write_clear,
1358
                 0x00000000);
1359
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1360
                 SPR_NOACCESS, SPR_NOACCESS,
1361
                 &spr_read_generic, &spr_write_generic,
1362
                 0x00000000);
1363
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1364
                 SPR_NOACCESS, SPR_NOACCESS,
1365
                 &spr_read_generic, &spr_write_generic,
1366
                 0x00000000);
1367
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1368
                 SPR_NOACCESS, SPR_NOACCESS,
1369
                 &spr_read_generic, &spr_write_excp_prefix,
1370
                 0x00000000);
1371
    /* Exception vectors */
1372
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1373
                 SPR_NOACCESS, SPR_NOACCESS,
1374
                 &spr_read_generic, &spr_write_excp_vector,
1375
                 0x00000000);
1376
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1377
                 SPR_NOACCESS, SPR_NOACCESS,
1378
                 &spr_read_generic, &spr_write_excp_vector,
1379
                 0x00000000);
1380
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1381
                 SPR_NOACCESS, SPR_NOACCESS,
1382
                 &spr_read_generic, &spr_write_excp_vector,
1383
                 0x00000000);
1384
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1385
                 SPR_NOACCESS, SPR_NOACCESS,
1386
                 &spr_read_generic, &spr_write_excp_vector,
1387
                 0x00000000);
1388
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1389
                 SPR_NOACCESS, SPR_NOACCESS,
1390
                 &spr_read_generic, &spr_write_excp_vector,
1391
                 0x00000000);
1392
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1393
                 SPR_NOACCESS, SPR_NOACCESS,
1394
                 &spr_read_generic, &spr_write_excp_vector,
1395
                 0x00000000);
1396
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1397
                 SPR_NOACCESS, SPR_NOACCESS,
1398
                 &spr_read_generic, &spr_write_excp_vector,
1399
                 0x00000000);
1400
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1401
                 SPR_NOACCESS, SPR_NOACCESS,
1402
                 &spr_read_generic, &spr_write_excp_vector,
1403
                 0x00000000);
1404
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1405
                 SPR_NOACCESS, SPR_NOACCESS,
1406
                 &spr_read_generic, &spr_write_excp_vector,
1407
                 0x00000000);
1408
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1409
                 SPR_NOACCESS, SPR_NOACCESS,
1410
                 &spr_read_generic, &spr_write_excp_vector,
1411
                 0x00000000);
1412
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1413
                 SPR_NOACCESS, SPR_NOACCESS,
1414
                 &spr_read_generic, &spr_write_excp_vector,
1415
                 0x00000000);
1416
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1417
                 SPR_NOACCESS, SPR_NOACCESS,
1418
                 &spr_read_generic, &spr_write_excp_vector,
1419
                 0x00000000);
1420
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1421
                 SPR_NOACCESS, SPR_NOACCESS,
1422
                 &spr_read_generic, &spr_write_excp_vector,
1423
                 0x00000000);
1424
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1425
                 SPR_NOACCESS, SPR_NOACCESS,
1426
                 &spr_read_generic, &spr_write_excp_vector,
1427
                 0x00000000);
1428
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1429
                 SPR_NOACCESS, SPR_NOACCESS,
1430
                 &spr_read_generic, &spr_write_excp_vector,
1431
                 0x00000000);
1432
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1433
                 SPR_NOACCESS, SPR_NOACCESS,
1434
                 &spr_read_generic, &spr_write_excp_vector,
1435
                 0x00000000);
1436
#if 0
1437
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1438
                 SPR_NOACCESS, SPR_NOACCESS,
1439
                 &spr_read_generic, &spr_write_excp_vector,
1440
                 0x00000000);
1441
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1442
                 SPR_NOACCESS, SPR_NOACCESS,
1443
                 &spr_read_generic, &spr_write_excp_vector,
1444
                 0x00000000);
1445
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1446
                 SPR_NOACCESS, SPR_NOACCESS,
1447
                 &spr_read_generic, &spr_write_excp_vector,
1448
                 0x00000000);
1449
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1450
                 SPR_NOACCESS, SPR_NOACCESS,
1451
                 &spr_read_generic, &spr_write_excp_vector,
1452
                 0x00000000);
1453
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1454
                 SPR_NOACCESS, SPR_NOACCESS,
1455
                 &spr_read_generic, &spr_write_excp_vector,
1456
                 0x00000000);
1457
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1458
                 SPR_NOACCESS, SPR_NOACCESS,
1459
                 &spr_read_generic, &spr_write_excp_vector,
1460
                 0x00000000);
1461
#endif
1462
    spr_register(env, SPR_BOOKE_PID, "PID",
1463
                 SPR_NOACCESS, SPR_NOACCESS,
1464
                 &spr_read_generic, &spr_write_generic,
1465
                 0x00000000);
1466
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1467
                 SPR_NOACCESS, SPR_NOACCESS,
1468
                 &spr_read_generic, &spr_write_booke_tcr,
1469
                 0x00000000);
1470
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1471
                 SPR_NOACCESS, SPR_NOACCESS,
1472
                 &spr_read_generic, &spr_write_booke_tsr,
1473
                 0x00000000);
1474
    /* Timer */
1475
    spr_register(env, SPR_DECR, "DECR",
1476
                 SPR_NOACCESS, SPR_NOACCESS,
1477
                 &spr_read_decr, &spr_write_decr,
1478
                 0x00000000);
1479
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1480
                 SPR_NOACCESS, SPR_NOACCESS,
1481
                 SPR_NOACCESS, &spr_write_generic,
1482
                 0x00000000);
1483
    /* SPRGs */
1484
    spr_register(env, SPR_USPRG0, "USPRG0",
1485
                 &spr_read_generic, &spr_write_generic,
1486
                 &spr_read_generic, &spr_write_generic,
1487
                 0x00000000);
1488
    spr_register(env, SPR_SPRG4, "SPRG4",
1489
                 SPR_NOACCESS, SPR_NOACCESS,
1490
                 &spr_read_generic, &spr_write_generic,
1491
                 0x00000000);
1492
    spr_register(env, SPR_USPRG4, "USPRG4",
1493
                 &spr_read_ureg, SPR_NOACCESS,
1494
                 &spr_read_ureg, SPR_NOACCESS,
1495
                 0x00000000);
1496
    spr_register(env, SPR_SPRG5, "SPRG5",
1497
                 SPR_NOACCESS, SPR_NOACCESS,
1498
                 &spr_read_generic, &spr_write_generic,
1499
                 0x00000000);
1500
    spr_register(env, SPR_USPRG5, "USPRG5",
1501
                 &spr_read_ureg, SPR_NOACCESS,
1502
                 &spr_read_ureg, SPR_NOACCESS,
1503
                 0x00000000);
1504
    spr_register(env, SPR_SPRG6, "SPRG6",
1505
                 SPR_NOACCESS, SPR_NOACCESS,
1506
                 &spr_read_generic, &spr_write_generic,
1507
                 0x00000000);
1508
    spr_register(env, SPR_USPRG6, "USPRG6",
1509
                 &spr_read_ureg, SPR_NOACCESS,
1510
                 &spr_read_ureg, SPR_NOACCESS,
1511
                 0x00000000);
1512
    spr_register(env, SPR_SPRG7, "SPRG7",
1513
                 SPR_NOACCESS, SPR_NOACCESS,
1514
                 &spr_read_generic, &spr_write_generic,
1515
                 0x00000000);
1516
    spr_register(env, SPR_USPRG7, "USPRG7",
1517
                 &spr_read_ureg, SPR_NOACCESS,
1518
                 &spr_read_ureg, SPR_NOACCESS,
1519
                 0x00000000);
1520
}
1521

    
1522
/* FSL storage control registers */
1523
static void gen_spr_BookE_FSL (CPUPPCState *env)
1524
{
1525
#if !defined(CONFIG_USER_ONLY)
1526
    /* TLB assist registers */
1527
    /* XXX : not implemented */
1528
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1529
                 SPR_NOACCESS, SPR_NOACCESS,
1530
                 &spr_read_generic, &spr_write_generic,
1531
                 0x00000000);
1532
    /* XXX : not implemented */
1533
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1534
                 SPR_NOACCESS, SPR_NOACCESS,
1535
                 &spr_read_generic, &spr_write_generic,
1536
                 0x00000000);
1537
    /* XXX : not implemented */
1538
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1539
                 SPR_NOACCESS, SPR_NOACCESS,
1540
                 &spr_read_generic, &spr_write_generic,
1541
                 0x00000000);
1542
    /* XXX : not implemented */
1543
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1544
                 SPR_NOACCESS, SPR_NOACCESS,
1545
                 &spr_read_generic, &spr_write_generic,
1546
                 0x00000000);
1547
    /* XXX : not implemented */
1548
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1549
                 SPR_NOACCESS, SPR_NOACCESS,
1550
                 &spr_read_generic, &spr_write_generic,
1551
                 0x00000000);
1552
    /* XXX : not implemented */
1553
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1554
                 SPR_NOACCESS, SPR_NOACCESS,
1555
                 &spr_read_generic, &spr_write_generic,
1556
                 0x00000000);
1557
    /* XXX : not implemented */
1558
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1559
                 SPR_NOACCESS, SPR_NOACCESS,
1560
                 &spr_read_generic, &spr_write_generic,
1561
                 0x00000000);
1562
    if (env->nb_pids > 1) {
1563
        /* XXX : not implemented */
1564
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1565
                     SPR_NOACCESS, SPR_NOACCESS,
1566
                     &spr_read_generic, &spr_write_generic,
1567
                     0x00000000);
1568
    }
1569
    if (env->nb_pids > 2) {
1570
        /* XXX : not implemented */
1571
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1572
                     SPR_NOACCESS, SPR_NOACCESS,
1573
                     &spr_read_generic, &spr_write_generic,
1574
                     0x00000000);
1575
    }
1576
    /* XXX : not implemented */
1577
    spr_register(env, SPR_MMUCFG, "MMUCFG",
1578
                 SPR_NOACCESS, SPR_NOACCESS,
1579
                 &spr_read_generic, SPR_NOACCESS,
1580
                 0x00000000); /* TOFIX */
1581
    /* XXX : not implemented */
1582
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1583
                 SPR_NOACCESS, SPR_NOACCESS,
1584
                 &spr_read_generic, &spr_write_generic,
1585
                 0x00000000); /* TOFIX */
1586
    switch (env->nb_ways) {
1587
    case 4:
1588
        /* XXX : not implemented */
1589
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1590
                     SPR_NOACCESS, SPR_NOACCESS,
1591
                     &spr_read_generic, SPR_NOACCESS,
1592
                     0x00000000); /* TOFIX */
1593
        /* Fallthru */
1594
    case 3:
1595
        /* XXX : not implemented */
1596
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1597
                     SPR_NOACCESS, SPR_NOACCESS,
1598
                     &spr_read_generic, SPR_NOACCESS,
1599
                     0x00000000); /* TOFIX */
1600
        /* Fallthru */
1601
    case 2:
1602
        /* XXX : not implemented */
1603
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1604
                     SPR_NOACCESS, SPR_NOACCESS,
1605
                     &spr_read_generic, SPR_NOACCESS,
1606
                     0x00000000); /* TOFIX */
1607
        /* Fallthru */
1608
    case 1:
1609
        /* XXX : not implemented */
1610
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1611
                     SPR_NOACCESS, SPR_NOACCESS,
1612
                     &spr_read_generic, SPR_NOACCESS,
1613
                     0x00000000); /* TOFIX */
1614
        /* Fallthru */
1615
    case 0:
1616
    default:
1617
        break;
1618
    }
1619
#endif
1620
}
1621

    
1622
/* SPR specific to PowerPC 440 implementation */
1623
static void gen_spr_440 (CPUPPCState *env)
1624
{
1625
    /* Cache control */
1626
    /* XXX : not implemented */
1627
    spr_register(env, SPR_440_DNV0, "DNV0",
1628
                 SPR_NOACCESS, SPR_NOACCESS,
1629
                 &spr_read_generic, &spr_write_generic,
1630
                 0x00000000);
1631
    /* XXX : not implemented */
1632
    spr_register(env, SPR_440_DNV1, "DNV1",
1633
                 SPR_NOACCESS, SPR_NOACCESS,
1634
                 &spr_read_generic, &spr_write_generic,
1635
                 0x00000000);
1636
    /* XXX : not implemented */
1637
    spr_register(env, SPR_440_DNV2, "DNV2",
1638
                 SPR_NOACCESS, SPR_NOACCESS,
1639
                 &spr_read_generic, &spr_write_generic,
1640
                 0x00000000);
1641
    /* XXX : not implemented */
1642
    spr_register(env, SPR_440_DNV3, "DNV3",
1643
                 SPR_NOACCESS, SPR_NOACCESS,
1644
                 &spr_read_generic, &spr_write_generic,
1645
                 0x00000000);
1646
    /* XXX : not implemented */
1647
    spr_register(env, SPR_440_DTV0, "DTV0",
1648
                 SPR_NOACCESS, SPR_NOACCESS,
1649
                 &spr_read_generic, &spr_write_generic,
1650
                 0x00000000);
1651
    /* XXX : not implemented */
1652
    spr_register(env, SPR_440_DTV1, "DTV1",
1653
                 SPR_NOACCESS, SPR_NOACCESS,
1654
                 &spr_read_generic, &spr_write_generic,
1655
                 0x00000000);
1656
    /* XXX : not implemented */
1657
    spr_register(env, SPR_440_DTV2, "DTV2",
1658
                 SPR_NOACCESS, SPR_NOACCESS,
1659
                 &spr_read_generic, &spr_write_generic,
1660
                 0x00000000);
1661
    /* XXX : not implemented */
1662
    spr_register(env, SPR_440_DTV3, "DTV3",
1663
                 SPR_NOACCESS, SPR_NOACCESS,
1664
                 &spr_read_generic, &spr_write_generic,
1665
                 0x00000000);
1666
    /* XXX : not implemented */
1667
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1668
                 SPR_NOACCESS, SPR_NOACCESS,
1669
                 &spr_read_generic, &spr_write_generic,
1670
                 0x00000000);
1671
    /* XXX : not implemented */
1672
    spr_register(env, SPR_440_INV0, "INV0",
1673
                 SPR_NOACCESS, SPR_NOACCESS,
1674
                 &spr_read_generic, &spr_write_generic,
1675
                 0x00000000);
1676
    /* XXX : not implemented */
1677
    spr_register(env, SPR_440_INV1, "INV1",
1678
                 SPR_NOACCESS, SPR_NOACCESS,
1679
                 &spr_read_generic, &spr_write_generic,
1680
                 0x00000000);
1681
    /* XXX : not implemented */
1682
    spr_register(env, SPR_440_INV2, "INV2",
1683
                 SPR_NOACCESS, SPR_NOACCESS,
1684
                 &spr_read_generic, &spr_write_generic,
1685
                 0x00000000);
1686
    /* XXX : not implemented */
1687
    spr_register(env, SPR_440_INV3, "INV3",
1688
                 SPR_NOACCESS, SPR_NOACCESS,
1689
                 &spr_read_generic, &spr_write_generic,
1690
                 0x00000000);
1691
    /* XXX : not implemented */
1692
    spr_register(env, SPR_440_ITV0, "ITV0",
1693
                 SPR_NOACCESS, SPR_NOACCESS,
1694
                 &spr_read_generic, &spr_write_generic,
1695
                 0x00000000);
1696
    /* XXX : not implemented */
1697
    spr_register(env, SPR_440_ITV1, "ITV1",
1698
                 SPR_NOACCESS, SPR_NOACCESS,
1699
                 &spr_read_generic, &spr_write_generic,
1700
                 0x00000000);
1701
    /* XXX : not implemented */
1702
    spr_register(env, SPR_440_ITV2, "ITV2",
1703
                 SPR_NOACCESS, SPR_NOACCESS,
1704
                 &spr_read_generic, &spr_write_generic,
1705
                 0x00000000);
1706
    /* XXX : not implemented */
1707
    spr_register(env, SPR_440_ITV3, "ITV3",
1708
                 SPR_NOACCESS, SPR_NOACCESS,
1709
                 &spr_read_generic, &spr_write_generic,
1710
                 0x00000000);
1711
    /* XXX : not implemented */
1712
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1713
                 SPR_NOACCESS, SPR_NOACCESS,
1714
                 &spr_read_generic, &spr_write_generic,
1715
                 0x00000000);
1716
    /* Cache debug */
1717
    /* XXX : not implemented */
1718
    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1719
                 SPR_NOACCESS, SPR_NOACCESS,
1720
                 &spr_read_generic, SPR_NOACCESS,
1721
                 0x00000000);
1722
    /* XXX : not implemented */
1723
    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1724
                 SPR_NOACCESS, SPR_NOACCESS,
1725
                 &spr_read_generic, SPR_NOACCESS,
1726
                 0x00000000);
1727
    /* XXX : not implemented */
1728
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1729
                 SPR_NOACCESS, SPR_NOACCESS,
1730
                 &spr_read_generic, SPR_NOACCESS,
1731
                 0x00000000);
1732
    /* XXX : not implemented */
1733
    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1734
                 SPR_NOACCESS, SPR_NOACCESS,
1735
                 &spr_read_generic, SPR_NOACCESS,
1736
                 0x00000000);
1737
    /* XXX : not implemented */
1738
    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1739
                 SPR_NOACCESS, SPR_NOACCESS,
1740
                 &spr_read_generic, SPR_NOACCESS,
1741
                 0x00000000);
1742
    /* XXX : not implemented */
1743
    spr_register(env, SPR_440_DBDR, "DBDR",
1744
                 SPR_NOACCESS, SPR_NOACCESS,
1745
                 &spr_read_generic, &spr_write_generic,
1746
                 0x00000000);
1747
    /* Processor control */
1748
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1749
                 SPR_NOACCESS, SPR_NOACCESS,
1750
                 &spr_read_generic, &spr_write_generic,
1751
                 0x00000000);
1752
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1753
                 SPR_NOACCESS, SPR_NOACCESS,
1754
                 &spr_read_generic, SPR_NOACCESS,
1755
                 0x00000000);
1756
    /* Storage control */
1757
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1758
                 SPR_NOACCESS, SPR_NOACCESS,
1759
                 &spr_read_generic, &spr_write_generic,
1760
                 0x00000000);
1761
}
1762

    
1763
/* SPR shared between PowerPC 40x implementations */
1764
static void gen_spr_40x (CPUPPCState *env)
1765
{
1766
    /* Cache */
1767
    /* not emulated, as Qemu do not emulate caches */
1768
    spr_register(env, SPR_40x_DCCR, "DCCR",
1769
                 SPR_NOACCESS, SPR_NOACCESS,
1770
                 &spr_read_generic, &spr_write_generic,
1771
                 0x00000000);
1772
    /* not emulated, as Qemu do not emulate caches */
1773
    spr_register(env, SPR_40x_ICCR, "ICCR",
1774
                 SPR_NOACCESS, SPR_NOACCESS,
1775
                 &spr_read_generic, &spr_write_generic,
1776
                 0x00000000);
1777
    /* not emulated, as Qemu do not emulate caches */
1778
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1779
                 SPR_NOACCESS, SPR_NOACCESS,
1780
                 &spr_read_generic, SPR_NOACCESS,
1781
                 0x00000000);
1782
    /* Exception */
1783
    spr_register(env, SPR_40x_DEAR, "DEAR",
1784
                 SPR_NOACCESS, SPR_NOACCESS,
1785
                 &spr_read_generic, &spr_write_generic,
1786
                 0x00000000);
1787
    spr_register(env, SPR_40x_ESR, "ESR",
1788
                 SPR_NOACCESS, SPR_NOACCESS,
1789
                 &spr_read_generic, &spr_write_generic,
1790
                 0x00000000);
1791
    spr_register(env, SPR_40x_EVPR, "EVPR",
1792
                 SPR_NOACCESS, SPR_NOACCESS,
1793
                 &spr_read_generic, &spr_write_excp_prefix,
1794
                 0x00000000);
1795
    spr_register(env, SPR_40x_SRR2, "SRR2",
1796
                 &spr_read_generic, &spr_write_generic,
1797
                 &spr_read_generic, &spr_write_generic,
1798
                 0x00000000);
1799
    spr_register(env, SPR_40x_SRR3, "SRR3",
1800
                 &spr_read_generic, &spr_write_generic,
1801
                 &spr_read_generic, &spr_write_generic,
1802
                 0x00000000);
1803
    /* Timers */
1804
    spr_register(env, SPR_40x_PIT, "PIT",
1805
                 SPR_NOACCESS, SPR_NOACCESS,
1806
                 &spr_read_40x_pit, &spr_write_40x_pit,
1807
                 0x00000000);
1808
    spr_register(env, SPR_40x_TCR, "TCR",
1809
                 SPR_NOACCESS, SPR_NOACCESS,
1810
                 &spr_read_generic, &spr_write_booke_tcr,
1811
                 0x00000000);
1812
    spr_register(env, SPR_40x_TSR, "TSR",
1813
                 SPR_NOACCESS, SPR_NOACCESS,
1814
                 &spr_read_generic, &spr_write_booke_tsr,
1815
                 0x00000000);
1816
}
1817

    
1818
/* SPR specific to PowerPC 405 implementation */
1819
static void gen_spr_405 (CPUPPCState *env)
1820
{
1821
    /* MMU */
1822
    spr_register(env, SPR_40x_PID, "PID",
1823
                 SPR_NOACCESS, SPR_NOACCESS,
1824
                 &spr_read_generic, &spr_write_generic,
1825
                 0x00000000);
1826
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1827
                 SPR_NOACCESS, SPR_NOACCESS,
1828
                 &spr_read_generic, &spr_write_generic,
1829
                 0x00700000);
1830
    /* Debug interface */
1831
    /* XXX : not implemented */
1832
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1833
                 SPR_NOACCESS, SPR_NOACCESS,
1834
                 &spr_read_generic, &spr_write_40x_dbcr0,
1835
                 0x00000000);
1836
    /* XXX : not implemented */
1837
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1838
                 SPR_NOACCESS, SPR_NOACCESS,
1839
                 &spr_read_generic, &spr_write_generic,
1840
                 0x00000000);
1841
    /* XXX : not implemented */
1842
    spr_register(env, SPR_40x_DBSR, "DBSR",
1843
                 SPR_NOACCESS, SPR_NOACCESS,
1844
                 &spr_read_generic, &spr_write_clear,
1845
                 /* Last reset was system reset */
1846
                 0x00000300);
1847
    /* XXX : not implemented */
1848
    spr_register(env, SPR_40x_DAC1, "DAC1",
1849
                 SPR_NOACCESS, SPR_NOACCESS,
1850
                 &spr_read_generic, &spr_write_generic,
1851
                 0x00000000);
1852
    spr_register(env, SPR_40x_DAC2, "DAC2",
1853
                 SPR_NOACCESS, SPR_NOACCESS,
1854
                 &spr_read_generic, &spr_write_generic,
1855
                 0x00000000);
1856
    /* XXX : not implemented */
1857
    spr_register(env, SPR_405_DVC1, "DVC1",
1858
                 SPR_NOACCESS, SPR_NOACCESS,
1859
                 &spr_read_generic, &spr_write_generic,
1860
                 0x00000000);
1861
    /* XXX : not implemented */
1862
    spr_register(env, SPR_405_DVC2, "DVC2",
1863
                 SPR_NOACCESS, SPR_NOACCESS,
1864
                 &spr_read_generic, &spr_write_generic,
1865
                 0x00000000);
1866
    /* XXX : not implemented */
1867
    spr_register(env, SPR_40x_IAC1, "IAC1",
1868
                 SPR_NOACCESS, SPR_NOACCESS,
1869
                 &spr_read_generic, &spr_write_generic,
1870
                 0x00000000);
1871
    spr_register(env, SPR_40x_IAC2, "IAC2",
1872
                 SPR_NOACCESS, SPR_NOACCESS,
1873
                 &spr_read_generic, &spr_write_generic,
1874
                 0x00000000);
1875
    /* XXX : not implemented */
1876
    spr_register(env, SPR_405_IAC3, "IAC3",
1877
                 SPR_NOACCESS, SPR_NOACCESS,
1878
                 &spr_read_generic, &spr_write_generic,
1879
                 0x00000000);
1880
    /* XXX : not implemented */
1881
    spr_register(env, SPR_405_IAC4, "IAC4",
1882
                 SPR_NOACCESS, SPR_NOACCESS,
1883
                 &spr_read_generic, &spr_write_generic,
1884
                 0x00000000);
1885
    /* Storage control */
1886
    /* XXX: TODO: not implemented */
1887
    spr_register(env, SPR_405_SLER, "SLER",
1888
                 SPR_NOACCESS, SPR_NOACCESS,
1889
                 &spr_read_generic, &spr_write_40x_sler,
1890
                 0x00000000);
1891
    spr_register(env, SPR_40x_ZPR, "ZPR",
1892
                 SPR_NOACCESS, SPR_NOACCESS,
1893
                 &spr_read_generic, &spr_write_generic,
1894
                 0x00000000);
1895
    /* XXX : not implemented */
1896
    spr_register(env, SPR_405_SU0R, "SU0R",
1897
                 SPR_NOACCESS, SPR_NOACCESS,
1898
                 &spr_read_generic, &spr_write_generic,
1899
                 0x00000000);
1900
    /* SPRG */
1901
    spr_register(env, SPR_USPRG0, "USPRG0",
1902
                 &spr_read_ureg, SPR_NOACCESS,
1903
                 &spr_read_ureg, SPR_NOACCESS,
1904
                 0x00000000);
1905
    spr_register(env, SPR_SPRG4, "SPRG4",
1906
                 SPR_NOACCESS, SPR_NOACCESS,
1907
                 &spr_read_generic, &spr_write_generic,
1908
                 0x00000000);
1909
    spr_register(env, SPR_USPRG4, "USPRG4",
1910
                 &spr_read_ureg, SPR_NOACCESS,
1911
                 &spr_read_ureg, SPR_NOACCESS,
1912
                 0x00000000);
1913
    spr_register(env, SPR_SPRG5, "SPRG5",
1914
                 SPR_NOACCESS, SPR_NOACCESS,
1915
                 spr_read_generic, &spr_write_generic,
1916
                 0x00000000);
1917
    spr_register(env, SPR_USPRG5, "USPRG5",
1918
                 &spr_read_ureg, SPR_NOACCESS,
1919
                 &spr_read_ureg, SPR_NOACCESS,
1920
                 0x00000000);
1921
    spr_register(env, SPR_SPRG6, "SPRG6",
1922
                 SPR_NOACCESS, SPR_NOACCESS,
1923
                 spr_read_generic, &spr_write_generic,
1924
                 0x00000000);
1925
    spr_register(env, SPR_USPRG6, "USPRG6",
1926
                 &spr_read_ureg, SPR_NOACCESS,
1927
                 &spr_read_ureg, SPR_NOACCESS,
1928
                 0x00000000);
1929
    spr_register(env, SPR_SPRG7, "SPRG7",
1930
                 SPR_NOACCESS, SPR_NOACCESS,
1931
                 spr_read_generic, &spr_write_generic,
1932
                 0x00000000);
1933
    spr_register(env, SPR_USPRG7, "USPRG7",
1934
                 &spr_read_ureg, SPR_NOACCESS,
1935
                 &spr_read_ureg, SPR_NOACCESS,
1936
                 0x00000000);
1937
}
1938

    
1939
/* SPR shared between PowerPC 401 & 403 implementations */
1940
static void gen_spr_401_403 (CPUPPCState *env)
1941
{
1942
    /* Time base */
1943
    spr_register(env, SPR_403_VTBL,  "TBL",
1944
                 &spr_read_tbl, SPR_NOACCESS,
1945
                 &spr_read_tbl, SPR_NOACCESS,
1946
                 0x00000000);
1947
    spr_register(env, SPR_403_TBL,   "TBL",
1948
                 SPR_NOACCESS, SPR_NOACCESS,
1949
                 SPR_NOACCESS, &spr_write_tbl,
1950
                 0x00000000);
1951
    spr_register(env, SPR_403_VTBU,  "TBU",
1952
                 &spr_read_tbu, SPR_NOACCESS,
1953
                 &spr_read_tbu, SPR_NOACCESS,
1954
                 0x00000000);
1955
    spr_register(env, SPR_403_TBU,   "TBU",
1956
                 SPR_NOACCESS, SPR_NOACCESS,
1957
                 SPR_NOACCESS, &spr_write_tbu,
1958
                 0x00000000);
1959
    /* Debug */
1960
    /* not emulated, as Qemu do not emulate caches */
1961
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1962
                 SPR_NOACCESS, SPR_NOACCESS,
1963
                 &spr_read_generic, &spr_write_generic,
1964
                 0x00000000);
1965
}
1966

    
1967
/* SPR specific to PowerPC 401 implementation */
1968
static void gen_spr_401 (CPUPPCState *env)
1969
{
1970
    /* Debug interface */
1971
    /* XXX : not implemented */
1972
    spr_register(env, SPR_40x_DBCR0, "DBCR",
1973
                 SPR_NOACCESS, SPR_NOACCESS,
1974
                 &spr_read_generic, &spr_write_40x_dbcr0,
1975
                 0x00000000);
1976
    /* XXX : not implemented */
1977
    spr_register(env, SPR_40x_DBSR, "DBSR",
1978
                 SPR_NOACCESS, SPR_NOACCESS,
1979
                 &spr_read_generic, &spr_write_clear,
1980
                 /* Last reset was system reset */
1981
                 0x00000300);
1982
    /* XXX : not implemented */
1983
    spr_register(env, SPR_40x_DAC1, "DAC",
1984
                 SPR_NOACCESS, SPR_NOACCESS,
1985
                 &spr_read_generic, &spr_write_generic,
1986
                 0x00000000);
1987
    /* XXX : not implemented */
1988
    spr_register(env, SPR_40x_IAC1, "IAC",
1989
                 SPR_NOACCESS, SPR_NOACCESS,
1990
                 &spr_read_generic, &spr_write_generic,
1991
                 0x00000000);
1992
    /* Storage control */
1993
    /* XXX: TODO: not implemented */
1994
    spr_register(env, SPR_405_SLER, "SLER",
1995
                 SPR_NOACCESS, SPR_NOACCESS,
1996
                 &spr_read_generic, &spr_write_40x_sler,
1997
                 0x00000000);
1998
    /* not emulated, as Qemu never does speculative access */
1999
    spr_register(env, SPR_40x_SGR, "SGR",
2000
                 SPR_NOACCESS, SPR_NOACCESS,
2001
                 &spr_read_generic, &spr_write_generic,
2002
                 0xFFFFFFFF);
2003
    /* not emulated, as Qemu do not emulate caches */
2004
    spr_register(env, SPR_40x_DCWR, "DCWR",
2005
                 SPR_NOACCESS, SPR_NOACCESS,
2006
                 &spr_read_generic, &spr_write_generic,
2007
                 0x00000000);
2008
}
2009

    
2010
static void gen_spr_401x2 (CPUPPCState *env)
2011
{
2012
    gen_spr_401(env);
2013
    spr_register(env, SPR_40x_PID, "PID",
2014
                 SPR_NOACCESS, SPR_NOACCESS,
2015
                 &spr_read_generic, &spr_write_generic,
2016
                 0x00000000);
2017
    spr_register(env, SPR_40x_ZPR, "ZPR",
2018
                 SPR_NOACCESS, SPR_NOACCESS,
2019
                 &spr_read_generic, &spr_write_generic,
2020
                 0x00000000);
2021
}
2022

    
2023
/* SPR specific to PowerPC 403 implementation */
2024
static void gen_spr_403 (CPUPPCState *env)
2025
{
2026
    /* Debug interface */
2027
    /* XXX : not implemented */
2028
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2029
                 SPR_NOACCESS, SPR_NOACCESS,
2030
                 &spr_read_generic, &spr_write_40x_dbcr0,
2031
                 0x00000000);
2032
    /* XXX : not implemented */
2033
    spr_register(env, SPR_40x_DBSR, "DBSR",
2034
                 SPR_NOACCESS, SPR_NOACCESS,
2035
                 &spr_read_generic, &spr_write_clear,
2036
                 /* Last reset was system reset */
2037
                 0x00000300);
2038
    /* XXX : not implemented */
2039
    spr_register(env, SPR_40x_DAC1, "DAC1",
2040
                 SPR_NOACCESS, SPR_NOACCESS,
2041
                 &spr_read_generic, &spr_write_generic,
2042
                 0x00000000);
2043
    /* XXX : not implemented */
2044
    spr_register(env, SPR_40x_DAC2, "DAC2",
2045
                 SPR_NOACCESS, SPR_NOACCESS,
2046
                 &spr_read_generic, &spr_write_generic,
2047
                 0x00000000);
2048
    /* XXX : not implemented */
2049
    spr_register(env, SPR_40x_IAC1, "IAC1",
2050
                 SPR_NOACCESS, SPR_NOACCESS,
2051
                 &spr_read_generic, &spr_write_generic,
2052
                 0x00000000);
2053
    /* XXX : not implemented */
2054
    spr_register(env, SPR_40x_IAC2, "IAC2",
2055
                 SPR_NOACCESS, SPR_NOACCESS,
2056
                 &spr_read_generic, &spr_write_generic,
2057
                 0x00000000);
2058
}
2059

    
2060
static void gen_spr_403_real (CPUPPCState *env)
2061
{
2062
    spr_register(env, SPR_403_PBL1,  "PBL1",
2063
                 SPR_NOACCESS, SPR_NOACCESS,
2064
                 &spr_read_403_pbr, &spr_write_403_pbr,
2065
                 0x00000000);
2066
    spr_register(env, SPR_403_PBU1,  "PBU1",
2067
                 SPR_NOACCESS, SPR_NOACCESS,
2068
                 &spr_read_403_pbr, &spr_write_403_pbr,
2069
                 0x00000000);
2070
    spr_register(env, SPR_403_PBL2,  "PBL2",
2071
                 SPR_NOACCESS, SPR_NOACCESS,
2072
                 &spr_read_403_pbr, &spr_write_403_pbr,
2073
                 0x00000000);
2074
    spr_register(env, SPR_403_PBU2,  "PBU2",
2075
                 SPR_NOACCESS, SPR_NOACCESS,
2076
                 &spr_read_403_pbr, &spr_write_403_pbr,
2077
                 0x00000000);
2078
}
2079

    
2080
static void gen_spr_403_mmu (CPUPPCState *env)
2081
{
2082
    /* MMU */
2083
    spr_register(env, SPR_40x_PID, "PID",
2084
                 SPR_NOACCESS, SPR_NOACCESS,
2085
                 &spr_read_generic, &spr_write_generic,
2086
                 0x00000000);
2087
    spr_register(env, SPR_40x_ZPR, "ZPR",
2088
                 SPR_NOACCESS, SPR_NOACCESS,
2089
                 &spr_read_generic, &spr_write_generic,
2090
                 0x00000000);
2091
}
2092

    
2093
/* SPR specific to PowerPC compression coprocessor extension */
2094
static void gen_spr_compress (CPUPPCState *env)
2095
{
2096
    /* XXX : not implemented */
2097
    spr_register(env, SPR_401_SKR, "SKR",
2098
                 SPR_NOACCESS, SPR_NOACCESS,
2099
                 &spr_read_generic, &spr_write_generic,
2100
                 0x00000000);
2101
}
2102

    
2103
#if defined (TARGET_PPC64)
2104
/* SPR specific to PowerPC 620 */
2105
static void gen_spr_620 (CPUPPCState *env)
2106
{
2107
    /* XXX : not implemented */
2108
    spr_register(env, SPR_620_PMR0, "PMR0",
2109
                 SPR_NOACCESS, SPR_NOACCESS,
2110
                 &spr_read_generic, &spr_write_generic,
2111
                 0x00000000);
2112
    /* XXX : not implemented */
2113
    spr_register(env, SPR_620_PMR1, "PMR1",
2114
                 SPR_NOACCESS, SPR_NOACCESS,
2115
                 &spr_read_generic, &spr_write_generic,
2116
                 0x00000000);
2117
    /* XXX : not implemented */
2118
    spr_register(env, SPR_620_PMR2, "PMR2",
2119
                 SPR_NOACCESS, SPR_NOACCESS,
2120
                 &spr_read_generic, &spr_write_generic,
2121
                 0x00000000);
2122
    /* XXX : not implemented */
2123
    spr_register(env, SPR_620_PMR3, "PMR3",
2124
                 SPR_NOACCESS, SPR_NOACCESS,
2125
                 &spr_read_generic, &spr_write_generic,
2126
                 0x00000000);
2127
    /* XXX : not implemented */
2128
    spr_register(env, SPR_620_PMR4, "PMR4",
2129
                 SPR_NOACCESS, SPR_NOACCESS,
2130
                 &spr_read_generic, &spr_write_generic,
2131
                 0x00000000);
2132
    /* XXX : not implemented */
2133
    spr_register(env, SPR_620_PMR5, "PMR5",
2134
                 SPR_NOACCESS, SPR_NOACCESS,
2135
                 &spr_read_generic, &spr_write_generic,
2136
                 0x00000000);
2137
    /* XXX : not implemented */
2138
    spr_register(env, SPR_620_PMR6, "PMR6",
2139
                 SPR_NOACCESS, SPR_NOACCESS,
2140
                 &spr_read_generic, &spr_write_generic,
2141
                 0x00000000);
2142
    /* XXX : not implemented */
2143
    spr_register(env, SPR_620_PMR7, "PMR7",
2144
                 SPR_NOACCESS, SPR_NOACCESS,
2145
                 &spr_read_generic, &spr_write_generic,
2146
                 0x00000000);
2147
    /* XXX : not implemented */
2148
    spr_register(env, SPR_620_PMR8, "PMR8",
2149
                 SPR_NOACCESS, SPR_NOACCESS,
2150
                 &spr_read_generic, &spr_write_generic,
2151
                 0x00000000);
2152
    /* XXX : not implemented */
2153
    spr_register(env, SPR_620_PMR9, "PMR9",
2154
                 SPR_NOACCESS, SPR_NOACCESS,
2155
                 &spr_read_generic, &spr_write_generic,
2156
                 0x00000000);
2157
    /* XXX : not implemented */
2158
    spr_register(env, SPR_620_PMRA, "PMR10",
2159
                 SPR_NOACCESS, SPR_NOACCESS,
2160
                 &spr_read_generic, &spr_write_generic,
2161
                 0x00000000);
2162
    /* XXX : not implemented */
2163
    spr_register(env, SPR_620_PMRB, "PMR11",
2164
                 SPR_NOACCESS, SPR_NOACCESS,
2165
                 &spr_read_generic, &spr_write_generic,
2166
                 0x00000000);
2167
    /* XXX : not implemented */
2168
    spr_register(env, SPR_620_PMRC, "PMR12",
2169
                 SPR_NOACCESS, SPR_NOACCESS,
2170
                 &spr_read_generic, &spr_write_generic,
2171
                 0x00000000);
2172
    /* XXX : not implemented */
2173
    spr_register(env, SPR_620_PMRD, "PMR13",
2174
                 SPR_NOACCESS, SPR_NOACCESS,
2175
                 &spr_read_generic, &spr_write_generic,
2176
                 0x00000000);
2177
    /* XXX : not implemented */
2178
    spr_register(env, SPR_620_PMRE, "PMR14",
2179
                 SPR_NOACCESS, SPR_NOACCESS,
2180
                 &spr_read_generic, &spr_write_generic,
2181
                 0x00000000);
2182
    /* XXX : not implemented */
2183
    spr_register(env, SPR_620_PMRF, "PMR15",
2184
                 SPR_NOACCESS, SPR_NOACCESS,
2185
                 &spr_read_generic, &spr_write_generic,
2186
                 0x00000000);
2187
    /* XXX : not implemented */
2188
    spr_register(env, SPR_620_HID8, "HID8",
2189
                 SPR_NOACCESS, SPR_NOACCESS,
2190
                 &spr_read_generic, &spr_write_generic,
2191
                 0x00000000);
2192
    /* XXX : not implemented */
2193
    spr_register(env, SPR_620_HID9, "HID9",
2194
                 SPR_NOACCESS, SPR_NOACCESS,
2195
                 &spr_read_generic, &spr_write_generic,
2196
                 0x00000000);
2197
}
2198
#endif /* defined (TARGET_PPC64) */
2199

    
2200
// XXX: TODO
2201
/*
2202
 * AMR     => SPR 29 (Power 2.04)
2203
 * CTRL    => SPR 136 (Power 2.04)
2204
 * CTRL    => SPR 152 (Power 2.04)
2205
 * SCOMC   => SPR 276 (64 bits ?)
2206
 * SCOMD   => SPR 277 (64 bits ?)
2207
 * TBU40   => SPR 286 (Power 2.04 hypv)
2208
 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2209
 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2210
 * HDSISR  => SPR 306 (Power 2.04 hypv)
2211
 * HDAR    => SPR 307 (Power 2.04 hypv)
2212
 * PURR    => SPR 309 (Power 2.04 hypv)
2213
 * HDEC    => SPR 310 (Power 2.04 hypv)
2214
 * HIOR    => SPR 311 (hypv)
2215
 * RMOR    => SPR 312 (970)
2216
 * HRMOR   => SPR 313 (Power 2.04 hypv)
2217
 * HSRR0   => SPR 314 (Power 2.04 hypv)
2218
 * HSRR1   => SPR 315 (Power 2.04 hypv)
2219
 * LPCR    => SPR 316 (970)
2220
 * LPIDR   => SPR 317 (970)
2221
 * SPEFSCR => SPR 512 (Power 2.04 emb)
2222
 * EPR     => SPR 702 (Power 2.04 emb)
2223
 * perf    => 768-783 (Power 2.04)
2224
 * perf    => 784-799 (Power 2.04)
2225
 * PPR     => SPR 896 (Power 2.04)
2226
 * EPLC    => SPR 947 (Power 2.04 emb)
2227
 * EPSC    => SPR 948 (Power 2.04 emb)
2228
 * DABRX   => 1015    (Power 2.04 hypv)
2229
 * FPECR   => SPR 1022 (?)
2230
 * ... and more (thermal management, performance counters, ...)
2231
 */
2232

    
2233
/*****************************************************************************/
2234
/* Exception vectors models                                                  */
2235
static void init_excp_4xx_real (CPUPPCState *env)
2236
{
2237
#if !defined(CONFIG_USER_ONLY)
2238
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2239
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2240
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2241
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2242
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2243
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2244
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2245
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2246
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2247
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2248
    env->excp_prefix = 0x00000000;
2249
    env->ivor_mask = 0x0000FFF0;
2250
    env->ivpr_mask = 0xFFFF0000;
2251
    /* Hardware reset vector */
2252
    env->hreset_vector = 0xFFFFFFFCUL;
2253
#endif
2254
}
2255

    
2256
static void init_excp_4xx_softmmu (CPUPPCState *env)
2257
{
2258
#if !defined(CONFIG_USER_ONLY)
2259
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2260
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2261
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2262
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2263
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2264
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2265
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2266
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2267
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2268
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2269
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2270
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2271
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2272
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2273
    env->excp_prefix = 0x00000000;
2274
    env->ivor_mask = 0x0000FFF0;
2275
    env->ivpr_mask = 0xFFFF0000;
2276
    /* Hardware reset vector */
2277
    env->hreset_vector = 0xFFFFFFFCUL;
2278
#endif
2279
}
2280

    
2281
static void init_excp_BookE (CPUPPCState *env)
2282
{
2283
#if !defined(CONFIG_USER_ONLY)
2284
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2285
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2286
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2287
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2288
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2289
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2290
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2291
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2292
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2293
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2294
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2295
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2296
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2297
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2298
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2299
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2300
    env->excp_prefix = 0x00000000;
2301
    env->ivor_mask = 0x0000FFE0;
2302
    env->ivpr_mask = 0xFFFF0000;
2303
    /* Hardware reset vector */
2304
    env->hreset_vector = 0xFFFFFFFCUL;
2305
#endif
2306
}
2307

    
2308
static void init_excp_601 (CPUPPCState *env)
2309
{
2310
#if !defined(CONFIG_USER_ONLY)
2311
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2312
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2313
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2314
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2315
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2316
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2317
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2318
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2319
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2320
    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2321
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2322
    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2323
    env->excp_prefix = 0xFFF00000;
2324
    /* Hardware reset vector */
2325
    env->hreset_vector = 0xFFFFFFFCUL;
2326
#endif
2327
}
2328

    
2329
static void init_excp_602 (CPUPPCState *env)
2330
{
2331
#if !defined(CONFIG_USER_ONLY)
2332
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2333
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2334
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2335
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2336
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2337
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2338
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2339
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2340
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2341
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2342
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2343
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2344
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2345
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2346
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2347
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2348
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2349
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2350
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2351
    env->excp_prefix = 0xFFF00000;
2352
    /* Hardware reset vector */
2353
    env->hreset_vector = 0xFFFFFFFCUL;
2354
#endif
2355
}
2356

    
2357
static void init_excp_603 (CPUPPCState *env)
2358
{
2359
#if !defined(CONFIG_USER_ONLY)
2360
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2361
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2362
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2363
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2364
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2365
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2366
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2367
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2368
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2369
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2370
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2371
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2372
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2373
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2374
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2375
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2376
    /* Hardware reset vector */
2377
    env->hreset_vector = 0xFFFFFFFCUL;
2378
#endif
2379
}
2380

    
2381
static void init_excp_G2 (CPUPPCState *env)
2382
{
2383
#if !defined(CONFIG_USER_ONLY)
2384
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2385
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2386
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2387
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2388
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2389
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2390
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2391
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2392
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2393
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2394
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2395
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2396
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2397
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2398
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2399
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2400
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2401
    /* Hardware reset vector */
2402
    env->hreset_vector = 0xFFFFFFFCUL;
2403
#endif
2404
}
2405

    
2406
static void init_excp_604 (CPUPPCState *env)
2407
{
2408
#if !defined(CONFIG_USER_ONLY)
2409
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2410
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2411
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2412
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2413
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2414
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2415
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2416
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2417
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2418
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2419
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2420
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2421
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2422
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2423
    /* Hardware reset vector */
2424
    env->hreset_vector = 0xFFFFFFFCUL;
2425
#endif
2426
}
2427

    
2428
#if defined(TARGET_PPC64)
2429
static void init_excp_620 (CPUPPCState *env)
2430
{
2431
#if !defined(CONFIG_USER_ONLY)
2432
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2433
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2434
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2435
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2436
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2437
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2438
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2439
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2440
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2441
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2442
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2443
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2444
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2445
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2446
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2447
    /* Hardware reset vector */
2448
    env->hreset_vector = 0x0000000000000100ULL; /* ? */
2449
#endif
2450
}
2451
#endif /* defined(TARGET_PPC64) */
2452

    
2453
static void init_excp_7x0 (CPUPPCState *env)
2454
{
2455
#if !defined(CONFIG_USER_ONLY)
2456
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2457
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2458
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2459
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2460
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2461
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2462
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2463
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2464
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2465
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2466
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2467
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2468
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2469
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2470
    /* Hardware reset vector */
2471
    env->hreset_vector = 0xFFFFFFFCUL;
2472
#endif
2473
}
2474

    
2475
static void init_excp_750FX (CPUPPCState *env)
2476
{
2477
#if !defined(CONFIG_USER_ONLY)
2478
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2479
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2480
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2481
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2482
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2483
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2484
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2485
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2486
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2487
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2488
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2489
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2490
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2491
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2492
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2493
    /* Hardware reset vector */
2494
    env->hreset_vector = 0xFFFFFFFCUL;
2495
#endif
2496
}
2497

    
2498
static void init_excp_7400 (CPUPPCState *env)
2499
{
2500
#if !defined(CONFIG_USER_ONLY)
2501
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2502
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2503
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2504
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2505
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2506
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2507
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2508
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2509
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2510
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2511
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2512
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2513
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2514
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2515
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2516
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2517
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2518
    /* Hardware reset vector */
2519
    env->hreset_vector = 0xFFFFFFFCUL;
2520
#endif
2521
}
2522

    
2523
static void init_excp_7450 (CPUPPCState *env)
2524
{
2525
#if !defined(CONFIG_USER_ONLY)
2526
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2527
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2528
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2529
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2530
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2531
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2532
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2533
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2534
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2535
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2536
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2537
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2538
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2539
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2540
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2541
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2542
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2543
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2544
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2545
    /* Hardware reset vector */
2546
    env->hreset_vector = 0xFFFFFFFCUL;
2547
#endif
2548
}
2549

    
2550
#if defined (TARGET_PPC64)
2551
static void init_excp_970 (CPUPPCState *env)
2552
{
2553
#if !defined(CONFIG_USER_ONLY)
2554
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2555
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2556
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2557
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2558
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2559
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2560
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2561
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2562
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2563
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2564
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2565
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2566
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2567
#endif
2568
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2569
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2570
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2571
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2572
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2573
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
2574
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
2575
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
2576
    /* Hardware reset vector */
2577
    env->hreset_vector = 0x0000000000000100ULL;
2578
#endif
2579
}
2580
#endif
2581

    
2582
/*****************************************************************************/
2583
/* PowerPC implementations definitions                                       */
2584

    
2585
/* PowerPC 40x instruction set                                               */
2586
#define POWERPC_INSNS_EMB    (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
2587

    
2588
/* PowerPC 401                                                               */
2589
#define POWERPC_INSNS_401    (POWERPC_INSNS_EMB |                             \
2590
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2591
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2592
#define POWERPC_MSRM_401     (0x00000000000FD201ULL)
2593
#define POWERPC_MMU_401      (POWERPC_MMU_REAL_4xx)
2594
#define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
2595
#define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
2596
#define POWERPC_BFDM_401     (bfd_mach_ppc_403)
2597
#define POWERPC_FLAG_401     (POWERPC_FLAG_NONE)
2598

    
2599
static void init_proc_401 (CPUPPCState *env)
2600
{
2601
    gen_spr_40x(env);
2602
    gen_spr_401_403(env);
2603
    gen_spr_401(env);
2604
    init_excp_4xx_real(env);
2605
    env->dcache_line_size = 32;
2606
    env->icache_line_size = 32;
2607
    /* Allocate hardware IRQ controller */
2608
    ppc40x_irq_init(env);
2609
}
2610

    
2611
/* PowerPC 401x2                                                             */
2612
#define POWERPC_INSNS_401x2  (POWERPC_INSNS_EMB |                             \
2613
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2614
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2615
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2616
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2617
#define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
2618
#define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
2619
#define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
2620
#define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
2621
#define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
2622
#define POWERPC_FLAG_401x2   (POWERPC_FLAG_NONE)
2623

    
2624
static void init_proc_401x2 (CPUPPCState *env)
2625
{
2626
    gen_spr_40x(env);
2627
    gen_spr_401_403(env);
2628
    gen_spr_401x2(env);
2629
    gen_spr_compress(env);
2630
    /* Memory management */
2631
#if !defined(CONFIG_USER_ONLY)
2632
    env->nb_tlb = 64;
2633
    env->nb_ways = 1;
2634
    env->id_tlbs = 0;
2635
#endif
2636
    init_excp_4xx_softmmu(env);
2637
    env->dcache_line_size = 32;
2638
    env->icache_line_size = 32;
2639
    /* Allocate hardware IRQ controller */
2640
    ppc40x_irq_init(env);
2641
}
2642

    
2643
/* PowerPC 401x3                                                             */
2644
#define POWERPC_INSNS_401x3  (POWERPC_INSNS_EMB |                             \
2645
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2646
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2647
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2648
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2649
#define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
2650
#define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
2651
#define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
2652
#define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
2653
#define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
2654
#define POWERPC_FLAG_401x3   (POWERPC_FLAG_NONE)
2655

    
2656
__attribute__ (( unused ))
2657
static void init_proc_401x3 (CPUPPCState *env)
2658
{
2659
    gen_spr_40x(env);
2660
    gen_spr_401_403(env);
2661
    gen_spr_401(env);
2662
    gen_spr_401x2(env);
2663
    gen_spr_compress(env);
2664
    init_excp_4xx_softmmu(env);
2665
    env->dcache_line_size = 32;
2666
    env->icache_line_size = 32;
2667
    /* Allocate hardware IRQ controller */
2668
    ppc40x_irq_init(env);
2669
}
2670

    
2671
/* IOP480                                                                    */
2672
#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB |                             \
2673
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2674
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2675
                              PPC_CACHE_DCBA |                                \
2676
                              PPC_4xx_COMMON | PPC_40x_EXCP |  PPC_40x_ICBT)
2677
#define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
2678
#define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
2679
#define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
2680
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2681
#define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
2682
#define POWERPC_FLAG_IOP480  (POWERPC_FLAG_NONE)
2683

    
2684
static void init_proc_IOP480 (CPUPPCState *env)
2685
{
2686
    gen_spr_40x(env);
2687
    gen_spr_401_403(env);
2688
    gen_spr_401x2(env);
2689
    gen_spr_compress(env);
2690
    /* Memory management */
2691
#if !defined(CONFIG_USER_ONLY)
2692
    env->nb_tlb = 64;
2693
    env->nb_ways = 1;
2694
    env->id_tlbs = 0;
2695
#endif
2696
    init_excp_4xx_softmmu(env);
2697
    env->dcache_line_size = 32;
2698
    env->icache_line_size = 32;
2699
    /* Allocate hardware IRQ controller */
2700
    ppc40x_irq_init(env);
2701
}
2702

    
2703
/* PowerPC 403                                                               */
2704
#define POWERPC_INSNS_403    (POWERPC_INSNS_EMB |                             \
2705
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2706
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2707
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2708
#define POWERPC_MSRM_403     (0x000000000007D00DULL)
2709
#define POWERPC_MMU_403      (POWERPC_MMU_REAL_4xx)
2710
#define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
2711
#define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
2712
#define POWERPC_BFDM_403     (bfd_mach_ppc_403)
2713
#define POWERPC_FLAG_403     (POWERPC_FLAG_NONE)
2714

    
2715
static void init_proc_403 (CPUPPCState *env)
2716
{
2717
    gen_spr_40x(env);
2718
    gen_spr_401_403(env);
2719
    gen_spr_403(env);
2720
    gen_spr_403_real(env);
2721
    init_excp_4xx_real(env);
2722
    env->dcache_line_size = 32;
2723
    env->icache_line_size = 32;
2724
    /* Allocate hardware IRQ controller */
2725
    ppc40x_irq_init(env);
2726
#if !defined(CONFIG_USER_ONLY)
2727
    /* Hardware reset vector */
2728
    env->hreset_vector = 0xFFFFFFFCUL;
2729
#endif
2730
}
2731

    
2732
/* PowerPC 403 GCX                                                           */
2733
#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB |                             \
2734
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2735
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2736
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2737
#define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
2738
#define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
2739
#define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
2740
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2741
#define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
2742
#define POWERPC_FLAG_403GCX  (POWERPC_FLAG_NONE)
2743

    
2744
static void init_proc_403GCX (CPUPPCState *env)
2745
{
2746
    gen_spr_40x(env);
2747
    gen_spr_401_403(env);
2748
    gen_spr_403(env);
2749
    gen_spr_403_real(env);
2750
    gen_spr_403_mmu(env);
2751
    /* Bus access control */
2752
    /* not emulated, as Qemu never does speculative access */
2753
    spr_register(env, SPR_40x_SGR, "SGR",
2754
                 SPR_NOACCESS, SPR_NOACCESS,
2755
                 &spr_read_generic, &spr_write_generic,
2756
                 0xFFFFFFFF);
2757
    /* not emulated, as Qemu do not emulate caches */
2758
    spr_register(env, SPR_40x_DCWR, "DCWR",
2759
                 SPR_NOACCESS, SPR_NOACCESS,
2760
                 &spr_read_generic, &spr_write_generic,
2761
                 0x00000000);
2762
    /* Memory management */
2763
#if !defined(CONFIG_USER_ONLY)
2764
    env->nb_tlb = 64;
2765
    env->nb_ways = 1;
2766
    env->id_tlbs = 0;
2767
#endif
2768
    init_excp_4xx_softmmu(env);
2769
    env->dcache_line_size = 32;
2770
    env->icache_line_size = 32;
2771
    /* Allocate hardware IRQ controller */
2772
    ppc40x_irq_init(env);
2773
}
2774

    
2775
/* PowerPC 405                                                               */
2776
#define POWERPC_INSNS_405    (POWERPC_INSNS_EMB | PPC_MFTB |                  \
2777
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2778
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2779
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT |  \
2780
                              PPC_405_MAC)
2781
#define POWERPC_MSRM_405     (0x000000000006E630ULL)
2782
#define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
2783
#define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
2784
#define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
2785
#define POWERPC_BFDM_405     (bfd_mach_ppc_403)
2786
#define POWERPC_FLAG_405     (POWERPC_FLAG_NONE)
2787

    
2788
static void init_proc_405 (CPUPPCState *env)
2789
{
2790
    /* Time base */
2791
    gen_tbl(env);
2792
    gen_spr_40x(env);
2793
    gen_spr_405(env);
2794
    /* Bus access control */
2795
    /* not emulated, as Qemu never does speculative access */
2796
    spr_register(env, SPR_40x_SGR, "SGR",
2797
                 SPR_NOACCESS, SPR_NOACCESS,
2798
                 &spr_read_generic, &spr_write_generic,
2799
                 0xFFFFFFFF);
2800
    /* not emulated, as Qemu do not emulate caches */
2801
    spr_register(env, SPR_40x_DCWR, "DCWR",
2802
                 SPR_NOACCESS, SPR_NOACCESS,
2803
                 &spr_read_generic, &spr_write_generic,
2804
                 0x00000000);
2805
    /* Memory management */
2806
#if !defined(CONFIG_USER_ONLY)
2807
    env->nb_tlb = 64;
2808
    env->nb_ways = 1;
2809
    env->id_tlbs = 0;
2810
#endif
2811
    init_excp_4xx_softmmu(env);
2812
    env->dcache_line_size = 32;
2813
    env->icache_line_size = 32;
2814
    /* Allocate hardware IRQ controller */
2815
    ppc40x_irq_init(env);
2816
}
2817

    
2818
/* PowerPC 440 EP                                                            */
2819
#define POWERPC_INSNS_440EP  (POWERPC_INSNS_EMB |                             \
2820
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2821
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2822
                              PPC_440_SPEC | PPC_RFMCI)
2823
#define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
2824
#define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
2825
#define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
2826
#define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
2827
#define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
2828
#define POWERPC_FLAG_440EP   (POWERPC_FLAG_NONE)
2829

    
2830
static void init_proc_440EP (CPUPPCState *env)
2831
{
2832
    /* Time base */
2833
    gen_tbl(env);
2834
    gen_spr_BookE(env);
2835
    gen_spr_440(env);
2836
    /* XXX : not implemented */
2837
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2838
                 SPR_NOACCESS, SPR_NOACCESS,
2839
                 &spr_read_generic, &spr_write_generic,
2840
                 0x00000000);
2841
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2842
                 SPR_NOACCESS, SPR_NOACCESS,
2843
                 &spr_read_generic, &spr_write_generic,
2844
                 0x00000000);
2845
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2846
                 SPR_NOACCESS, SPR_NOACCESS,
2847
                 &spr_read_generic, &spr_write_generic,
2848
                 0x00000000);
2849
    /* XXX : not implemented */
2850
    spr_register(env, SPR_440_CCR1, "CCR1",
2851
                 SPR_NOACCESS, SPR_NOACCESS,
2852
                 &spr_read_generic, &spr_write_generic,
2853
                 0x00000000);
2854
    /* Memory management */
2855
#if !defined(CONFIG_USER_ONLY)
2856
    env->nb_tlb = 64;
2857
    env->nb_ways = 1;
2858
    env->id_tlbs = 0;
2859
#endif
2860
    init_excp_BookE(env);
2861
    env->dcache_line_size = 32;
2862
    env->icache_line_size = 32;
2863
    /* XXX: TODO: allocate internal IRQ controller */
2864
}
2865

    
2866
/* PowerPC 440 GP                                                            */
2867
#define POWERPC_INSNS_440GP  (POWERPC_INSNS_EMB |                             \
2868
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2869
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2870
                              PPC_405_MAC | PPC_440_SPEC)
2871
#define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
2872
#define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
2873
#define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
2874
#define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
2875
#define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
2876
#define POWERPC_FLAG_440GP   (POWERPC_FLAG_NONE)
2877

    
2878
static void init_proc_440GP (CPUPPCState *env)
2879
{
2880
    /* Time base */
2881
    gen_tbl(env);
2882
    gen_spr_BookE(env);
2883
    gen_spr_440(env);
2884
    /* Memory management */
2885
#if !defined(CONFIG_USER_ONLY)
2886
    env->nb_tlb = 64;
2887
    env->nb_ways = 1;
2888
    env->id_tlbs = 0;
2889
#endif
2890
    init_excp_BookE(env);
2891
    env->dcache_line_size = 32;
2892
    env->icache_line_size = 32;
2893
    /* XXX: TODO: allocate internal IRQ controller */
2894
}
2895

    
2896
/* PowerPC 440x4                                                             */
2897
#define POWERPC_INSNS_440x4  (POWERPC_INSNS_EMB |                             \
2898
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2899
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2900
                              PPC_440_SPEC)
2901
#define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
2902
#define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
2903
#define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
2904
#define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
2905
#define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
2906
#define POWERPC_FLAG_440x4   (POWERPC_FLAG_NONE)
2907

    
2908
__attribute__ (( unused ))
2909
static void init_proc_440x4 (CPUPPCState *env)
2910
{
2911
    /* Time base */
2912
    gen_tbl(env);
2913
    gen_spr_BookE(env);
2914
    gen_spr_440(env);
2915
    /* Memory management */
2916
#if !defined(CONFIG_USER_ONLY)
2917
    env->nb_tlb = 64;
2918
    env->nb_ways = 1;
2919
    env->id_tlbs = 0;
2920
#endif
2921
    init_excp_BookE(env);
2922
    env->dcache_line_size = 32;
2923
    env->icache_line_size = 32;
2924
    /* XXX: TODO: allocate internal IRQ controller */
2925
}
2926

    
2927
/* PowerPC 440x5                                                             */
2928
#define POWERPC_INSNS_440x5  (POWERPC_INSNS_EMB |                             \
2929
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2930
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2931
                              PPC_440_SPEC | PPC_RFMCI)
2932
#define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
2933
#define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
2934
#define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
2935
#define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
2936
#define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
2937
#define POWERPC_FLAG_440x5   (POWERPC_FLAG_NONE)
2938

    
2939
static void init_proc_440x5 (CPUPPCState *env)
2940
{
2941
    /* Time base */
2942
    gen_tbl(env);
2943
    gen_spr_BookE(env);
2944
    gen_spr_440(env);
2945
    /* XXX : not implemented */
2946
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2947
                 SPR_NOACCESS, SPR_NOACCESS,
2948
                 &spr_read_generic, &spr_write_generic,
2949
                 0x00000000);
2950
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2951
                 SPR_NOACCESS, SPR_NOACCESS,
2952
                 &spr_read_generic, &spr_write_generic,
2953
                 0x00000000);
2954
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2955
                 SPR_NOACCESS, SPR_NOACCESS,
2956
                 &spr_read_generic, &spr_write_generic,
2957
                 0x00000000);
2958
    /* XXX : not implemented */
2959
    spr_register(env, SPR_440_CCR1, "CCR1",
2960
                 SPR_NOACCESS, SPR_NOACCESS,
2961
                 &spr_read_generic, &spr_write_generic,
2962
                 0x00000000);
2963
    /* Memory management */
2964
#if !defined(CONFIG_USER_ONLY)
2965
    env->nb_tlb = 64;
2966
    env->nb_ways = 1;
2967
    env->id_tlbs = 0;
2968
#endif
2969
    init_excp_BookE(env);
2970
    env->dcache_line_size = 32;
2971
    env->icache_line_size = 32;
2972
    /* XXX: TODO: allocate internal IRQ controller */
2973
}
2974

    
2975
/* PowerPC 460 (guessed)                                                     */
2976
#define POWERPC_INSNS_460    (POWERPC_INSNS_EMB |                             \
2977
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2978
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2979
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2980
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
2981
#define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
2982
#define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
2983
#define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
2984
#define POWERPC_BFDM_460     (bfd_mach_ppc_403)
2985
#define POWERPC_FLAG_460     (POWERPC_FLAG_NONE)
2986

    
2987
__attribute__ (( unused ))
2988
static void init_proc_460 (CPUPPCState *env)
2989
{
2990
    /* Time base */
2991
    gen_tbl(env);
2992
    gen_spr_BookE(env);
2993
    gen_spr_440(env);
2994
    /* XXX : not implemented */
2995
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2996
                 SPR_NOACCESS, SPR_NOACCESS,
2997
                 &spr_read_generic, &spr_write_generic,
2998
                 0x00000000);
2999
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3000
                 SPR_NOACCESS, SPR_NOACCESS,
3001
                 &spr_read_generic, &spr_write_generic,
3002
                 0x00000000);
3003
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3004
                 SPR_NOACCESS, SPR_NOACCESS,
3005
                 &spr_read_generic, &spr_write_generic,
3006
                 0x00000000);
3007
    /* XXX : not implemented */
3008
    spr_register(env, SPR_440_CCR1, "CCR1",
3009
                 SPR_NOACCESS, SPR_NOACCESS,
3010
                 &spr_read_generic, &spr_write_generic,
3011
                 0x00000000);
3012
    /* XXX : not implemented */
3013
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3014
                 &spr_read_generic, &spr_write_generic,
3015
                 &spr_read_generic, &spr_write_generic,
3016
                 0x00000000);
3017
    /* Memory management */
3018
#if !defined(CONFIG_USER_ONLY)
3019
    env->nb_tlb = 64;
3020
    env->nb_ways = 1;
3021
    env->id_tlbs = 0;
3022
#endif
3023
    init_excp_BookE(env);
3024
    env->dcache_line_size = 32;
3025
    env->icache_line_size = 32;
3026
    /* XXX: TODO: allocate internal IRQ controller */
3027
}
3028

    
3029
/* PowerPC 460F (guessed)                                                    */
3030
#define POWERPC_INSNS_460F   (POWERPC_INSNS_EMB |                             \
3031
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
3032
                              PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES |  \
3033
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |            \
3034
                              PPC_FLOAT_STFIWX |                              \
3035
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
3036
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3037
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3038
#define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3039
#define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3040
#define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3041
#define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3042
#define POWERPC_FLAG_460F    (POWERPC_FLAG_NONE)
3043

    
3044
__attribute__ (( unused ))
3045
static void init_proc_460F (CPUPPCState *env)
3046
{
3047
    /* Time base */
3048
    gen_tbl(env);
3049
    gen_spr_BookE(env);
3050
    gen_spr_440(env);
3051
    /* XXX : not implemented */
3052
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3053
                 SPR_NOACCESS, SPR_NOACCESS,
3054
                 &spr_read_generic, &spr_write_generic,
3055
                 0x00000000);
3056
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3057
                 SPR_NOACCESS, SPR_NOACCESS,
3058
                 &spr_read_generic, &spr_write_generic,
3059
                 0x00000000);
3060
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3061
                 SPR_NOACCESS, SPR_NOACCESS,
3062
                 &spr_read_generic, &spr_write_generic,
3063
                 0x00000000);
3064
    /* XXX : not implemented */
3065
    spr_register(env, SPR_440_CCR1, "CCR1",
3066
                 SPR_NOACCESS, SPR_NOACCESS,
3067
                 &spr_read_generic, &spr_write_generic,
3068
                 0x00000000);
3069
    /* XXX : not implemented */
3070
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3071
                 &spr_read_generic, &spr_write_generic,
3072
                 &spr_read_generic, &spr_write_generic,
3073
                 0x00000000);
3074
    /* Memory management */
3075
#if !defined(CONFIG_USER_ONLY)
3076
    env->nb_tlb = 64;
3077
    env->nb_ways = 1;
3078
    env->id_tlbs = 0;
3079
#endif
3080
    init_excp_BookE(env);
3081
    env->dcache_line_size = 32;
3082
    env->icache_line_size = 32;
3083
    /* XXX: TODO: allocate internal IRQ controller */
3084
}
3085

    
3086
/* Generic BookE PowerPC                                                     */
3087
#define POWERPC_INSNS_BookE  (POWERPC_INSNS_EMB |                             \
3088
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
3089
                              PPC_CACHE_DCBA |                                \
3090
                              PPC_FLOAT | PPC_FLOAT_FSQRT |                   \
3091
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3092
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIW |              \
3093
                              PPC_BOOKE)
3094
#define POWERPC_MSRM_BookE   (0x000000000006D630ULL)
3095
#define POWERPC_MMU_BookE    (POWERPC_MMU_BOOKE)
3096
#define POWERPC_EXCP_BookE   (POWERPC_EXCP_BOOKE)
3097
#define POWERPC_INPUT_BookE  (PPC_FLAGS_INPUT_BookE)
3098
#define POWERPC_BFDM_BookE   (bfd_mach_ppc_403)
3099
#define POWERPC_FLAG_BookE   (POWERPC_FLAG_NONE)
3100

    
3101
__attribute__ (( unused ))
3102
static void init_proc_BookE (CPUPPCState *env)
3103
{
3104
    init_excp_BookE(env);
3105
    env->dcache_line_size = 32;
3106
    env->icache_line_size = 32;
3107
}
3108

    
3109
/* e200 core                                                                 */
3110

    
3111
/* e300 core                                                                 */
3112

    
3113
/* e500 core                                                                 */
3114
#define POWERPC_INSNS_e500   (POWERPC_INSNS_EMB |                             \
3115
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
3116
                              PPC_CACHE_DCBA |                                \
3117
                              PPC_BOOKE | PPC_E500_VECTOR)
3118
#define POWERPC_MMU_e500     (POWERPC_MMU_SOFT_4xx)
3119
#define POWERPC_EXCP_e500    (POWERPC_EXCP_40x)
3120
#define POWERPC_INPUT_e500   (PPC_FLAGS_INPUT_BookE)
3121
#define POWERPC_BFDM_e500    (bfd_mach_ppc_403)
3122
#define POWERPC_FLAG_e500    (POWERPC_FLAG_SPE)
3123

    
3124
__attribute__ (( unused ))
3125
static void init_proc_e500 (CPUPPCState *env)
3126
{
3127
    /* Time base */
3128
    gen_tbl(env);
3129
    gen_spr_BookE(env);
3130
    /* Memory management */
3131
    gen_spr_BookE_FSL(env);
3132
#if !defined(CONFIG_USER_ONLY)
3133
    env->nb_tlb = 64;
3134
    env->nb_ways = 1;
3135
    env->id_tlbs = 0;
3136
#endif
3137
    init_excp_BookE(env);
3138
    env->dcache_line_size = 32;
3139
    env->icache_line_size = 32;
3140
    /* XXX: TODO: allocate internal IRQ controller */
3141
}
3142

    
3143
/* e600 core                                                                 */
3144

    
3145
/* Non-embedded PowerPC                                                      */
3146
/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC                    */
3147
#define POWERPC_INSNS_6xx    (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |     \
3148
                              PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3149
/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602      */
3150
#define POWERPC_INSNS_WORKS  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |           \
3151
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3152
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3153
                              PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB |   \
3154
                              PPC_SEGMENT)
3155

    
3156
/* POWER : same as 601, without mfmsr, mfsr                                  */
3157
#if defined(TODO)
3158
#define POWERPC_INSNS_POWER  (XXX_TODO)
3159
/* POWER RSC (from RAD6000) */
3160
#define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
3161
#endif /* TODO */
3162

    
3163
/* PowerPC 601                                                               */
3164
#define POWERPC_INSNS_601    (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ |            \
3165
                              PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3166
#define POWERPC_MSRM_601     (0x000000000000FE70ULL)
3167
//#define POWERPC_MMU_601      (POWERPC_MMU_601)
3168
//#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
3169
#define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
3170
#define POWERPC_BFDM_601     (bfd_mach_ppc_601)
3171
#define POWERPC_FLAG_601     (POWERPC_FLAG_NONE)
3172

    
3173
static void init_proc_601 (CPUPPCState *env)
3174
{
3175
    gen_spr_ne_601(env);
3176
    gen_spr_601(env);
3177
    /* Hardware implementation registers */
3178
    /* XXX : not implemented */
3179
    spr_register(env, SPR_HID0, "HID0",
3180
                 SPR_NOACCESS, SPR_NOACCESS,
3181
                 &spr_read_generic, &spr_write_generic,
3182
                 0x00000000);
3183
    /* XXX : not implemented */
3184
    spr_register(env, SPR_HID1, "HID1",
3185
                 SPR_NOACCESS, SPR_NOACCESS,
3186
                 &spr_read_generic, &spr_write_generic,
3187
                 0x00000000);
3188
    /* XXX : not implemented */
3189
    spr_register(env, SPR_601_HID2, "HID2",
3190
                 SPR_NOACCESS, SPR_NOACCESS,
3191
                 &spr_read_generic, &spr_write_generic,
3192
                 0x00000000);
3193
    /* XXX : not implemented */
3194
    spr_register(env, SPR_601_HID5, "HID5",
3195
                 SPR_NOACCESS, SPR_NOACCESS,
3196
                 &spr_read_generic, &spr_write_generic,
3197
                 0x00000000);
3198
    /* XXX : not implemented */
3199
    spr_register(env, SPR_601_HID15, "HID15",
3200
                 SPR_NOACCESS, SPR_NOACCESS,
3201
                 &spr_read_generic, &spr_write_generic,
3202
                 0x00000000);
3203
    /* Memory management */
3204
#if !defined(CONFIG_USER_ONLY)
3205
    env->nb_tlb = 64;
3206
    env->nb_ways = 2;
3207
    env->id_tlbs = 0;
3208
#endif
3209
    init_excp_601(env);
3210
    env->dcache_line_size = 64;
3211
    env->icache_line_size = 64;
3212
    /* XXX: TODO: allocate internal IRQ controller */
3213
}
3214

    
3215
/* PowerPC 602                                                               */
3216
#define POWERPC_INSNS_602    (POWERPC_INSNS_6xx | PPC_MFTB |                  \
3217
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3218
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3219
                              PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3220
                              PPC_SEGMENT | PPC_602_SPEC)
3221
#define POWERPC_MSRM_602     (0x000000000033FF73ULL)
3222
#define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
3223
//#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
3224
#define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
3225
#define POWERPC_BFDM_602     (bfd_mach_ppc_602)
3226
#define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR)
3227

    
3228
static void init_proc_602 (CPUPPCState *env)
3229
{
3230
    gen_spr_ne_601(env);
3231
    gen_spr_602(env);
3232
    /* Time base */
3233
    gen_tbl(env);
3234
    /* hardware implementation registers */
3235
    /* XXX : not implemented */
3236
    spr_register(env, SPR_HID0, "HID0",
3237
                 SPR_NOACCESS, SPR_NOACCESS,
3238
                 &spr_read_generic, &spr_write_generic,
3239
                 0x00000000);
3240
    /* XXX : not implemented */
3241
    spr_register(env, SPR_HID1, "HID1",
3242
                 SPR_NOACCESS, SPR_NOACCESS,
3243
                 &spr_read_generic, &spr_write_generic,
3244
                 0x00000000);
3245
    /* Memory management */
3246
    gen_low_BATs(env);
3247
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3248
    init_excp_602(env);
3249
    env->dcache_line_size = 32;
3250
    env->icache_line_size = 32;
3251
    /* Allocate hardware IRQ controller */
3252
    ppc6xx_irq_init(env);
3253
}
3254

    
3255
/* PowerPC 603                                                               */
3256
#define POWERPC_INSNS_603    (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3257
#define POWERPC_MSRM_603     (0x000000000001FF73ULL)
3258
#define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
3259
//#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
3260
#define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
3261
#define POWERPC_BFDM_603     (bfd_mach_ppc_603)
3262
#define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR)
3263

    
3264
static void init_proc_603 (CPUPPCState *env)
3265
{
3266
    gen_spr_ne_601(env);
3267
    gen_spr_603(env);
3268
    /* Time base */
3269
    gen_tbl(env);
3270
    /* hardware implementation registers */
3271
    /* XXX : not implemented */
3272
    spr_register(env, SPR_HID0, "HID0",
3273
                 SPR_NOACCESS, SPR_NOACCESS,
3274
                 &spr_read_generic, &spr_write_generic,
3275
                 0x00000000);
3276
    /* XXX : not implemented */
3277
    spr_register(env, SPR_HID1, "HID1",
3278
                 SPR_NOACCESS, SPR_NOACCESS,
3279
                 &spr_read_generic, &spr_write_generic,
3280
                 0x00000000);
3281
    /* Memory management */
3282
    gen_low_BATs(env);
3283
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3284
    init_excp_603(env);
3285
    env->dcache_line_size = 32;
3286
    env->icache_line_size = 32;
3287
    /* Allocate hardware IRQ controller */
3288
    ppc6xx_irq_init(env);
3289
}
3290

    
3291
/* PowerPC 603e                                                              */
3292
#define POWERPC_INSNS_603E   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3293
#define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
3294
#define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
3295
//#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
3296
#define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
3297
#define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
3298
#define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR)
3299

    
3300
static void init_proc_603E (CPUPPCState *env)
3301
{
3302
    gen_spr_ne_601(env);
3303
    gen_spr_603(env);
3304
    /* Time base */
3305
    gen_tbl(env);
3306
    /* hardware implementation registers */
3307
    /* XXX : not implemented */
3308
    spr_register(env, SPR_HID0, "HID0",
3309
                 SPR_NOACCESS, SPR_NOACCESS,
3310
                 &spr_read_generic, &spr_write_generic,
3311
                 0x00000000);
3312
    /* XXX : not implemented */
3313
    spr_register(env, SPR_HID1, "HID1",
3314
                 SPR_NOACCESS, SPR_NOACCESS,
3315
                 &spr_read_generic, &spr_write_generic,
3316
                 0x00000000);
3317
    /* XXX : not implemented */
3318
    spr_register(env, SPR_IABR, "IABR",
3319
                 SPR_NOACCESS, SPR_NOACCESS,
3320
                 &spr_read_generic, &spr_write_generic,
3321
                 0x00000000);
3322
    /* Memory management */
3323
    gen_low_BATs(env);
3324
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3325
    init_excp_603(env);
3326
    env->dcache_line_size = 32;
3327
    env->icache_line_size = 32;
3328
    /* Allocate hardware IRQ controller */
3329
    ppc6xx_irq_init(env);
3330
}
3331

    
3332
/* PowerPC G2                                                                */
3333
#define POWERPC_INSNS_G2     (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3334
#define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3335
#define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3336
//#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3337
#define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3338
#define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3339
#define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR)
3340

    
3341
static void init_proc_G2 (CPUPPCState *env)
3342
{
3343
    gen_spr_ne_601(env);
3344
    gen_spr_G2_755(env);
3345
    gen_spr_G2(env);
3346
    /* Time base */
3347
    gen_tbl(env);
3348
    /* Hardware implementation register */
3349
    /* XXX : not implemented */
3350
    spr_register(env, SPR_HID0, "HID0",
3351
                 SPR_NOACCESS, SPR_NOACCESS,
3352
                 &spr_read_generic, &spr_write_generic,
3353
                 0x00000000);
3354
    /* XXX : not implemented */
3355
    spr_register(env, SPR_HID1, "HID1",
3356
                 SPR_NOACCESS, SPR_NOACCESS,
3357
                 &spr_read_generic, &spr_write_generic,
3358
                 0x00000000);
3359
    /* XXX : not implemented */
3360
    spr_register(env, SPR_HID2, "HID2",
3361
                 SPR_NOACCESS, SPR_NOACCESS,
3362
                 &spr_read_generic, &spr_write_generic,
3363
                 0x00000000);
3364
    /* Memory management */
3365
    gen_low_BATs(env);
3366
    gen_high_BATs(env);
3367
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3368
    init_excp_G2(env);
3369
    env->dcache_line_size = 32;
3370
    env->icache_line_size = 32;
3371
    /* Allocate hardware IRQ controller */
3372
    ppc6xx_irq_init(env);
3373
}
3374

    
3375
/* PowerPC G2LE                                                              */
3376
#define POWERPC_INSNS_G2LE   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3377
#define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3378
#define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3379
#define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3380
#define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3381
#define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3382
#define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR)
3383

    
3384
static void init_proc_G2LE (CPUPPCState *env)
3385
{
3386
    gen_spr_ne_601(env);
3387
    gen_spr_G2_755(env);
3388
    gen_spr_G2(env);
3389
    /* Time base */
3390
    gen_tbl(env);
3391
    /* Hardware implementation register */
3392
    /* XXX : not implemented */
3393
    spr_register(env, SPR_HID0, "HID0",
3394
                 SPR_NOACCESS, SPR_NOACCESS,
3395
                 &spr_read_generic, &spr_write_generic,
3396
                 0x00000000);
3397
    /* XXX : not implemented */
3398
    spr_register(env, SPR_HID1, "HID1",
3399
                 SPR_NOACCESS, SPR_NOACCESS,
3400
                 &spr_read_generic, &spr_write_generic,
3401
                 0x00000000);
3402
    /* XXX : not implemented */
3403
    spr_register(env, SPR_HID2, "HID2",
3404
                 SPR_NOACCESS, SPR_NOACCESS,
3405
                 &spr_read_generic, &spr_write_generic,
3406
                 0x00000000);
3407
    /* Memory management */
3408
    gen_low_BATs(env);
3409
    gen_high_BATs(env);
3410
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3411
    init_excp_G2(env);
3412
    env->dcache_line_size = 32;
3413
    env->icache_line_size = 32;
3414
    /* Allocate hardware IRQ controller */
3415
    ppc6xx_irq_init(env);
3416
}
3417

    
3418
/* PowerPC 604                                                               */
3419
#define POWERPC_INSNS_604    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3420
#define POWERPC_MSRM_604     (0x000000000005FF77ULL)
3421
#define POWERPC_MMU_604      (POWERPC_MMU_32B)
3422
//#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
3423
#define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
3424
#define POWERPC_BFDM_604     (bfd_mach_ppc_604)
3425
#define POWERPC_FLAG_604     (POWERPC_FLAG_NONE)
3426

    
3427
static void init_proc_604 (CPUPPCState *env)
3428
{
3429
    gen_spr_ne_601(env);
3430
    gen_spr_604(env);
3431
    /* Time base */
3432
    gen_tbl(env);
3433
    /* Hardware implementation registers */
3434
    /* XXX : not implemented */
3435
    spr_register(env, SPR_HID0, "HID0",
3436
                 SPR_NOACCESS, SPR_NOACCESS,
3437
                 &spr_read_generic, &spr_write_generic,
3438
                 0x00000000);
3439
    /* XXX : not implemented */
3440
    spr_register(env, SPR_HID1, "HID1",
3441
                 SPR_NOACCESS, SPR_NOACCESS,
3442
                 &spr_read_generic, &spr_write_generic,
3443
                 0x00000000);
3444
    /* Memory management */
3445
    gen_low_BATs(env);
3446
    init_excp_604(env);
3447
    env->dcache_line_size = 32;
3448
    env->icache_line_size = 32;
3449
    /* Allocate hardware IRQ controller */
3450
    ppc6xx_irq_init(env);
3451
}
3452

    
3453
/* PowerPC 740/750 (aka G3)                                                  */
3454
#define POWERPC_INSNS_7x0    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3455
#define POWERPC_MSRM_7x0     (0x000000000007FF77ULL)
3456
#define POWERPC_MMU_7x0      (POWERPC_MMU_32B)
3457
//#define POWERPC_EXCP_7x0     (POWERPC_EXCP_7x0)
3458
#define POWERPC_INPUT_7x0    (PPC_FLAGS_INPUT_6xx)
3459
#define POWERPC_BFDM_7x0     (bfd_mach_ppc_750)
3460
#define POWERPC_FLAG_7x0     (POWERPC_FLAG_NONE)
3461

    
3462
static void init_proc_7x0 (CPUPPCState *env)
3463
{
3464
    gen_spr_ne_601(env);
3465
    gen_spr_7xx(env);
3466
    /* Time base */
3467
    gen_tbl(env);
3468
    /* Thermal management */
3469
    gen_spr_thrm(env);
3470
    /* Hardware implementation registers */
3471
    /* XXX : not implemented */
3472
    spr_register(env, SPR_HID0, "HID0",
3473
                 SPR_NOACCESS, SPR_NOACCESS,
3474
                 &spr_read_generic, &spr_write_generic,
3475
                 0x00000000);
3476
    /* XXX : not implemented */
3477
    spr_register(env, SPR_HID1, "HID1",
3478
                 SPR_NOACCESS, SPR_NOACCESS,
3479
                 &spr_read_generic, &spr_write_generic,
3480
                 0x00000000);
3481
    /* Memory management */
3482
    gen_low_BATs(env);
3483
    init_excp_7x0(env);
3484
    env->dcache_line_size = 32;
3485
    env->icache_line_size = 32;
3486
    /* Allocate hardware IRQ controller */
3487
    ppc6xx_irq_init(env);
3488
}
3489

    
3490
/* PowerPC 750FX/GX                                                          */
3491
#define POWERPC_INSNS_750fx  (POWERPC_INSNS_WORKS | PPC_EXTERN)
3492
#define POWERPC_MSRM_750fx   (0x000000000007FF77ULL)
3493
#define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
3494
#define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
3495
#define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
3496
#define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
3497
#define POWERPC_FLAG_750fx   (POWERPC_FLAG_NONE)
3498

    
3499
static void init_proc_750fx (CPUPPCState *env)
3500
{
3501
    gen_spr_ne_601(env);
3502
    gen_spr_7xx(env);
3503
    /* Time base */
3504
    gen_tbl(env);
3505
    /* Thermal management */
3506
    gen_spr_thrm(env);
3507
    /* Hardware implementation registers */
3508
    /* XXX : not implemented */
3509
    spr_register(env, SPR_HID0, "HID0",
3510
                 SPR_NOACCESS, SPR_NOACCESS,
3511
                 &spr_read_generic, &spr_write_generic,
3512
                 0x00000000);
3513
    /* XXX : not implemented */
3514
    spr_register(env, SPR_HID1, "HID1",
3515
                 SPR_NOACCESS, SPR_NOACCESS,
3516
                 &spr_read_generic, &spr_write_generic,
3517
                 0x00000000);
3518
    /* XXX : not implemented */
3519
    spr_register(env, SPR_750_HID2, "HID2",
3520
                 SPR_NOACCESS, SPR_NOACCESS,
3521
                 &spr_read_generic, &spr_write_generic,
3522
                 0x00000000);
3523
    /* Memory management */
3524
    gen_low_BATs(env);
3525
    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3526
    gen_high_BATs(env);
3527
    init_excp_750FX(env);
3528
    env->dcache_line_size = 32;
3529
    env->icache_line_size = 32;
3530
    /* Allocate hardware IRQ controller */
3531
    ppc6xx_irq_init(env);
3532
}
3533

    
3534
/* PowerPC 745/755                                                           */
3535
#define POWERPC_INSNS_7x5    (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3536
#define POWERPC_MSRM_7x5     (0x000000000007FF77ULL)
3537
#define POWERPC_MMU_7x5      (POWERPC_MMU_SOFT_6xx)
3538
//#define POWERPC_EXCP_7x5     (POWERPC_EXCP_7x5)
3539
#define POWERPC_INPUT_7x5    (PPC_FLAGS_INPUT_6xx)
3540
#define POWERPC_BFDM_7x5     (bfd_mach_ppc_750)
3541
#define POWERPC_FLAG_7x5     (POWERPC_FLAG_NONE)
3542

    
3543
static void init_proc_7x5 (CPUPPCState *env)
3544
{
3545
    gen_spr_ne_601(env);
3546
    gen_spr_G2_755(env);
3547
    /* Time base */
3548
    gen_tbl(env);
3549
    /* L2 cache control */
3550
    /* XXX : not implemented */
3551
    spr_register(env, SPR_ICTC, "ICTC",
3552
                 SPR_NOACCESS, SPR_NOACCESS,
3553
                 &spr_read_generic, &spr_write_generic,
3554
                 0x00000000);
3555
    /* XXX : not implemented */
3556
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3557
                 SPR_NOACCESS, SPR_NOACCESS,
3558
                 &spr_read_generic, &spr_write_generic,
3559
                 0x00000000);
3560
    /* Hardware implementation registers */
3561
    /* XXX : not implemented */
3562
    spr_register(env, SPR_HID0, "HID0",
3563
                 SPR_NOACCESS, SPR_NOACCESS,
3564
                 &spr_read_generic, &spr_write_generic,
3565
                 0x00000000);
3566
    /* XXX : not implemented */
3567
    spr_register(env, SPR_HID1, "HID1",
3568
                 SPR_NOACCESS, SPR_NOACCESS,
3569
                 &spr_read_generic, &spr_write_generic,
3570
                 0x00000000);
3571
    /* XXX : not implemented */
3572
    spr_register(env, SPR_HID2, "HID2",
3573
                 SPR_NOACCESS, SPR_NOACCESS,
3574
                 &spr_read_generic, &spr_write_generic,
3575
                 0x00000000);
3576
    /* Memory management */
3577
    gen_low_BATs(env);
3578
    gen_high_BATs(env);
3579
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3580
    /* XXX: exception vectors ? */
3581
    env->dcache_line_size = 32;
3582
    env->icache_line_size = 32;
3583
    /* Allocate hardware IRQ controller */
3584
    ppc6xx_irq_init(env);
3585
#if !defined(CONFIG_USER_ONLY)
3586
    /* Hardware reset vector */
3587
    env->hreset_vector = 0xFFFFFFFCUL;
3588
#endif
3589
}
3590

    
3591
/* PowerPC 7400 (aka G4)                                                     */
3592
#define POWERPC_INSNS_7400   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3593
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3594
                              PPC_ALTIVEC)
3595
#define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
3596
#define POWERPC_MMU_7400     (POWERPC_MMU_32B)
3597
#define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
3598
#define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
3599
#define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
3600
#define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE)
3601

    
3602
static void init_proc_7400 (CPUPPCState *env)
3603
{
3604
    gen_spr_ne_601(env);
3605
    gen_spr_7xx(env);
3606
    /* Time base */
3607
    gen_tbl(env);
3608
    /* 74xx specific SPR */
3609
    gen_spr_74xx(env);
3610
    /* Thermal management */
3611
    gen_spr_thrm(env);
3612
    /* Memory management */
3613
    gen_low_BATs(env);
3614
    init_excp_7400(env);
3615
    env->dcache_line_size = 32;
3616
    env->icache_line_size = 32;
3617
    /* Allocate hardware IRQ controller */
3618
    ppc6xx_irq_init(env);
3619
}
3620

    
3621
/* PowerPC 7410 (aka G4)                                                     */
3622
#define POWERPC_INSNS_7410   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3623
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3624
                              PPC_ALTIVEC)
3625
#define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
3626
#define POWERPC_MMU_7410     (POWERPC_MMU_32B)
3627
#define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
3628
#define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
3629
#define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
3630
#define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE)
3631

    
3632
static void init_proc_7410 (CPUPPCState *env)
3633
{
3634
    gen_spr_ne_601(env);
3635
    gen_spr_7xx(env);
3636
    /* Time base */
3637
    gen_tbl(env);
3638
    /* 74xx specific SPR */
3639
    gen_spr_74xx(env);
3640
    /* Thermal management */
3641
    gen_spr_thrm(env);
3642
    /* L2PMCR */
3643
    /* XXX : not implemented */
3644
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3645
                 SPR_NOACCESS, SPR_NOACCESS,
3646
                 &spr_read_generic, &spr_write_generic,
3647
                 0x00000000);
3648
    /* LDSTDB */
3649
    /* XXX : not implemented */
3650
    spr_register(env, SPR_LDSTDB, "LDSTDB",
3651
                 SPR_NOACCESS, SPR_NOACCESS,
3652
                 &spr_read_generic, &spr_write_generic,
3653
                 0x00000000);
3654
    /* Memory management */
3655
    gen_low_BATs(env);
3656
    init_excp_7400(env);
3657
    env->dcache_line_size = 32;
3658
    env->icache_line_size = 32;
3659
    /* Allocate hardware IRQ controller */
3660
    ppc6xx_irq_init(env);
3661
}
3662

    
3663
/* PowerPC 7440 (aka G4)                                                     */
3664
#define POWERPC_INSNS_7440   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3665
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3666
                              PPC_ALTIVEC)
3667
#define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
3668
#define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
3669
#define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
3670
#define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
3671
#define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
3672
#define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE)
3673

    
3674
__attribute__ (( unused ))
3675
static void init_proc_7440 (CPUPPCState *env)
3676
{
3677
    gen_spr_ne_601(env);
3678
    gen_spr_7xx(env);
3679
    /* Time base */
3680
    gen_tbl(env);
3681
    /* 74xx specific SPR */
3682
    gen_spr_74xx(env);
3683
    /* LDSTCR */
3684
    /* XXX : not implemented */
3685
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3686
                 SPR_NOACCESS, SPR_NOACCESS,
3687
                 &spr_read_generic, &spr_write_generic,
3688
                 0x00000000);
3689
    /* ICTRL */
3690
    /* XXX : not implemented */
3691
    spr_register(env, SPR_ICTRL, "ICTRL",
3692
                 SPR_NOACCESS, SPR_NOACCESS,
3693
                 &spr_read_generic, &spr_write_generic,
3694
                 0x00000000);
3695
    /* MSSSR0 */
3696
    /* XXX : not implemented */
3697
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3698
                 SPR_NOACCESS, SPR_NOACCESS,
3699
                 &spr_read_generic, &spr_write_generic,
3700
                 0x00000000);
3701
    /* PMC */
3702
    /* XXX : not implemented */
3703
    spr_register(env, SPR_PMC5, "PMC5",
3704
                 SPR_NOACCESS, SPR_NOACCESS,
3705
                 &spr_read_generic, &spr_write_generic,
3706
                 0x00000000);
3707
    /* XXX : not implemented */
3708
    spr_register(env, SPR_UPMC5, "UPMC5",
3709
                 &spr_read_ureg, SPR_NOACCESS,
3710
                 &spr_read_ureg, SPR_NOACCESS,
3711
                 0x00000000);
3712
    /* XXX : not implemented */
3713
    spr_register(env, SPR_PMC6, "PMC6",
3714
                 SPR_NOACCESS, SPR_NOACCESS,
3715
                 &spr_read_generic, &spr_write_generic,
3716
                 0x00000000);
3717
    /* XXX : not implemented */
3718
    spr_register(env, SPR_UPMC6, "UPMC6",
3719
                 &spr_read_ureg, SPR_NOACCESS,
3720
                 &spr_read_ureg, SPR_NOACCESS,
3721
                 0x00000000);
3722
    /* Memory management */
3723
    gen_low_BATs(env);
3724
    gen_74xx_soft_tlb(env, 128, 2);
3725
    init_excp_7450(env);
3726
    env->dcache_line_size = 32;
3727
    env->icache_line_size = 32;
3728
    /* Allocate hardware IRQ controller */
3729
    ppc6xx_irq_init(env);
3730
}
3731

    
3732
/* PowerPC 7450 (aka G4)                                                     */
3733
#define POWERPC_INSNS_7450   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3734
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3735
                              PPC_ALTIVEC)
3736
#define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
3737
#define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
3738
#define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
3739
#define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
3740
#define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
3741
#define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE)
3742

    
3743
__attribute__ (( unused ))
3744
static void init_proc_7450 (CPUPPCState *env)
3745
{
3746
    gen_spr_ne_601(env);
3747
    gen_spr_7xx(env);
3748
    /* Time base */
3749
    gen_tbl(env);
3750
    /* 74xx specific SPR */
3751
    gen_spr_74xx(env);
3752
    /* Level 3 cache control */
3753
    gen_l3_ctrl(env);
3754
    /* LDSTCR */
3755
    /* XXX : not implemented */
3756
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3757
                 SPR_NOACCESS, SPR_NOACCESS,
3758
                 &spr_read_generic, &spr_write_generic,
3759
                 0x00000000);
3760
    /* ICTRL */
3761
    /* XXX : not implemented */
3762
    spr_register(env, SPR_ICTRL, "ICTRL",
3763
                 SPR_NOACCESS, SPR_NOACCESS,
3764
                 &spr_read_generic, &spr_write_generic,
3765
                 0x00000000);
3766
    /* MSSSR0 */
3767
    /* XXX : not implemented */
3768
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3769
                 SPR_NOACCESS, SPR_NOACCESS,
3770
                 &spr_read_generic, &spr_write_generic,
3771
                 0x00000000);
3772
    /* PMC */
3773
    /* XXX : not implemented */
3774
    spr_register(env, SPR_PMC5, "PMC5",
3775
                 SPR_NOACCESS, SPR_NOACCESS,
3776
                 &spr_read_generic, &spr_write_generic,
3777
                 0x00000000);
3778
    /* XXX : not implemented */
3779
    spr_register(env, SPR_UPMC5, "UPMC5",
3780
                 &spr_read_ureg, SPR_NOACCESS,
3781
                 &spr_read_ureg, SPR_NOACCESS,
3782
                 0x00000000);
3783
    /* XXX : not implemented */
3784
    spr_register(env, SPR_PMC6, "PMC6",
3785
                 SPR_NOACCESS, SPR_NOACCESS,
3786
                 &spr_read_generic, &spr_write_generic,
3787
                 0x00000000);
3788
    /* XXX : not implemented */
3789
    spr_register(env, SPR_UPMC6, "UPMC6",
3790
                 &spr_read_ureg, SPR_NOACCESS,
3791
                 &spr_read_ureg, SPR_NOACCESS,
3792
                 0x00000000);
3793
    /* Memory management */
3794
    gen_low_BATs(env);
3795
    gen_74xx_soft_tlb(env, 128, 2);
3796
    init_excp_7450(env);
3797
    env->dcache_line_size = 32;
3798
    env->icache_line_size = 32;
3799
    /* Allocate hardware IRQ controller */
3800
    ppc6xx_irq_init(env);
3801
}
3802

    
3803
/* PowerPC 7445 (aka G4)                                                     */
3804
#define POWERPC_INSNS_7445   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3805
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3806
                              PPC_ALTIVEC)
3807
#define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
3808
#define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
3809
#define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
3810
#define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
3811
#define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
3812
#define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE)
3813

    
3814
__attribute__ (( unused ))
3815
static void init_proc_7445 (CPUPPCState *env)
3816
{
3817
    gen_spr_ne_601(env);
3818
    gen_spr_7xx(env);
3819
    /* Time base */
3820
    gen_tbl(env);
3821
    /* 74xx specific SPR */
3822
    gen_spr_74xx(env);
3823
    /* LDSTCR */
3824
    /* XXX : not implemented */
3825
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3826
                 SPR_NOACCESS, SPR_NOACCESS,
3827
                 &spr_read_generic, &spr_write_generic,
3828
                 0x00000000);
3829
    /* ICTRL */
3830
    /* XXX : not implemented */
3831
    spr_register(env, SPR_ICTRL, "ICTRL",
3832
                 SPR_NOACCESS, SPR_NOACCESS,
3833
                 &spr_read_generic, &spr_write_generic,
3834
                 0x00000000);
3835
    /* MSSSR0 */
3836
    /* XXX : not implemented */
3837
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3838
                 SPR_NOACCESS, SPR_NOACCESS,
3839
                 &spr_read_generic, &spr_write_generic,
3840
                 0x00000000);
3841
    /* PMC */
3842
    /* XXX : not implemented */
3843
    spr_register(env, SPR_PMC5, "PMC5",
3844
                 SPR_NOACCESS, SPR_NOACCESS,
3845
                 &spr_read_generic, &spr_write_generic,
3846
                 0x00000000);
3847
    /* XXX : not implemented */
3848
    spr_register(env, SPR_UPMC5, "UPMC5",
3849
                 &spr_read_ureg, SPR_NOACCESS,
3850
                 &spr_read_ureg, SPR_NOACCESS,
3851
                 0x00000000);
3852
    /* XXX : not implemented */
3853
    spr_register(env, SPR_PMC6, "PMC6",
3854
                 SPR_NOACCESS, SPR_NOACCESS,
3855
                 &spr_read_generic, &spr_write_generic,
3856
                 0x00000000);
3857
    /* XXX : not implemented */
3858
    spr_register(env, SPR_UPMC6, "UPMC6",
3859
                 &spr_read_ureg, SPR_NOACCESS,
3860
                 &spr_read_ureg, SPR_NOACCESS,
3861
                 0x00000000);
3862
    /* SPRGs */
3863
    spr_register(env, SPR_SPRG4, "SPRG4",
3864
                 SPR_NOACCESS, SPR_NOACCESS,
3865
                 &spr_read_generic, &spr_write_generic,
3866
                 0x00000000);
3867
    spr_register(env, SPR_USPRG4, "USPRG4",
3868
                 &spr_read_ureg, SPR_NOACCESS,
3869
                 &spr_read_ureg, SPR_NOACCESS,
3870
                 0x00000000);
3871
    spr_register(env, SPR_SPRG5, "SPRG5",
3872
                 SPR_NOACCESS, SPR_NOACCESS,
3873
                 &spr_read_generic, &spr_write_generic,
3874
                 0x00000000);
3875
    spr_register(env, SPR_USPRG5, "USPRG5",
3876
                 &spr_read_ureg, SPR_NOACCESS,
3877
                 &spr_read_ureg, SPR_NOACCESS,
3878
                 0x00000000);
3879
    spr_register(env, SPR_SPRG6, "SPRG6",
3880
                 SPR_NOACCESS, SPR_NOACCESS,
3881
                 &spr_read_generic, &spr_write_generic,
3882
                 0x00000000);
3883
    spr_register(env, SPR_USPRG6, "USPRG6",
3884
                 &spr_read_ureg, SPR_NOACCESS,
3885
                 &spr_read_ureg, SPR_NOACCESS,
3886
                 0x00000000);
3887
    spr_register(env, SPR_SPRG7, "SPRG7",
3888
                 SPR_NOACCESS, SPR_NOACCESS,
3889
                 &spr_read_generic, &spr_write_generic,
3890
                 0x00000000);
3891
    spr_register(env, SPR_USPRG7, "USPRG7",
3892
                 &spr_read_ureg, SPR_NOACCESS,
3893
                 &spr_read_ureg, SPR_NOACCESS,
3894
                 0x00000000);
3895
    /* Memory management */
3896
    gen_low_BATs(env);
3897
    gen_high_BATs(env);
3898
    gen_74xx_soft_tlb(env, 128, 2);
3899
    init_excp_7450(env);
3900
    env->dcache_line_size = 32;
3901
    env->icache_line_size = 32;
3902
    /* Allocate hardware IRQ controller */
3903
    ppc6xx_irq_init(env);
3904
}
3905

    
3906
/* PowerPC 7455 (aka G4)                                                     */
3907
#define POWERPC_INSNS_7455   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3908
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3909
                              PPC_ALTIVEC)
3910
#define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
3911
#define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
3912
#define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
3913
#define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
3914
#define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
3915
#define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE)
3916

    
3917
__attribute__ (( unused ))
3918
static void init_proc_7455 (CPUPPCState *env)
3919
{
3920
    gen_spr_ne_601(env);
3921
    gen_spr_7xx(env);
3922
    /* Time base */
3923
    gen_tbl(env);
3924
    /* 74xx specific SPR */
3925
    gen_spr_74xx(env);
3926
    /* Level 3 cache control */
3927
    gen_l3_ctrl(env);
3928
    /* LDSTCR */
3929
    /* XXX : not implemented */
3930
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3931
                 SPR_NOACCESS, SPR_NOACCESS,
3932
                 &spr_read_generic, &spr_write_generic,
3933
                 0x00000000);
3934
    /* ICTRL */
3935
    /* XXX : not implemented */
3936
    spr_register(env, SPR_ICTRL, "ICTRL",
3937
                 SPR_NOACCESS, SPR_NOACCESS,
3938
                 &spr_read_generic, &spr_write_generic,
3939
                 0x00000000);
3940
    /* MSSSR0 */
3941
    /* XXX : not implemented */
3942
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3943
                 SPR_NOACCESS, SPR_NOACCESS,
3944
                 &spr_read_generic, &spr_write_generic,
3945
                 0x00000000);
3946
    /* PMC */
3947
    /* XXX : not implemented */
3948
    spr_register(env, SPR_PMC5, "PMC5",
3949
                 SPR_NOACCESS, SPR_NOACCESS,
3950
                 &spr_read_generic, &spr_write_generic,
3951
                 0x00000000);
3952
    /* XXX : not implemented */
3953
    spr_register(env, SPR_UPMC5, "UPMC5",
3954
                 &spr_read_ureg, SPR_NOACCESS,
3955
                 &spr_read_ureg, SPR_NOACCESS,
3956
                 0x00000000);
3957
    /* XXX : not implemented */
3958
    spr_register(env, SPR_PMC6, "PMC6",
3959
                 SPR_NOACCESS, SPR_NOACCESS,
3960
                 &spr_read_generic, &spr_write_generic,
3961
                 0x00000000);
3962
    /* XXX : not implemented */
3963
    spr_register(env, SPR_UPMC6, "UPMC6",
3964
                 &spr_read_ureg, SPR_NOACCESS,
3965
                 &spr_read_ureg, SPR_NOACCESS,
3966
                 0x00000000);
3967
    /* SPRGs */
3968
    spr_register(env, SPR_SPRG4, "SPRG4",
3969
                 SPR_NOACCESS, SPR_NOACCESS,
3970
                 &spr_read_generic, &spr_write_generic,
3971
                 0x00000000);
3972
    spr_register(env, SPR_USPRG4, "USPRG4",
3973
                 &spr_read_ureg, SPR_NOACCESS,
3974
                 &spr_read_ureg, SPR_NOACCESS,
3975
                 0x00000000);
3976
    spr_register(env, SPR_SPRG5, "SPRG5",
3977
                 SPR_NOACCESS, SPR_NOACCESS,
3978
                 &spr_read_generic, &spr_write_generic,
3979
                 0x00000000);
3980
    spr_register(env, SPR_USPRG5, "USPRG5",
3981
                 &spr_read_ureg, SPR_NOACCESS,
3982
                 &spr_read_ureg, SPR_NOACCESS,
3983
                 0x00000000);
3984
    spr_register(env, SPR_SPRG6, "SPRG6",
3985
                 SPR_NOACCESS, SPR_NOACCESS,
3986
                 &spr_read_generic, &spr_write_generic,
3987
                 0x00000000);
3988
    spr_register(env, SPR_USPRG6, "USPRG6",
3989
                 &spr_read_ureg, SPR_NOACCESS,
3990
                 &spr_read_ureg, SPR_NOACCESS,
3991
                 0x00000000);
3992
    spr_register(env, SPR_SPRG7, "SPRG7",
3993
                 SPR_NOACCESS, SPR_NOACCESS,
3994
                 &spr_read_generic, &spr_write_generic,
3995
                 0x00000000);
3996
    spr_register(env, SPR_USPRG7, "USPRG7",
3997
                 &spr_read_ureg, SPR_NOACCESS,
3998
                 &spr_read_ureg, SPR_NOACCESS,
3999
                 0x00000000);
4000
    /* Memory management */
4001
    gen_low_BATs(env);
4002
    gen_high_BATs(env);
4003
    gen_74xx_soft_tlb(env, 128, 2);
4004
    init_excp_7450(env);
4005
    env->dcache_line_size = 32;
4006
    env->icache_line_size = 32;
4007
    /* Allocate hardware IRQ controller */
4008
    ppc6xx_irq_init(env);
4009
}
4010

    
4011
#if defined (TARGET_PPC64)
4012
#define POWERPC_INSNS_WORK64  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |          \
4013
                               PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |           \
4014
                               PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |            \
4015
                               PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4016
/* PowerPC 970                                                               */
4017
#define POWERPC_INSNS_970    (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4018
                              PPC_64B | PPC_ALTIVEC |                         \
4019
                              PPC_SEGMENT_64B | PPC_SLBI)
4020
#define POWERPC_MSRM_970     (0x900000000204FF36ULL)
4021
#define POWERPC_MMU_970      (POWERPC_MMU_64B)
4022
//#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
4023
#define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
4024
#define POWERPC_BFDM_970     (bfd_mach_ppc64)
4025
#define POWERPC_FLAG_970     (POWERPC_FLAG_VRE)
4026

    
4027
#if defined(CONFIG_USER_ONLY)
4028
#define POWERPC970_HID5_INIT 0x00000080
4029
#else
4030
#define POWERPC970_HID5_INIT 0x00000000
4031
#endif
4032

    
4033
static void init_proc_970 (CPUPPCState *env)
4034
{
4035
    gen_spr_ne_601(env);
4036
    gen_spr_7xx(env);
4037
    /* Time base */
4038
    gen_tbl(env);
4039
    /* Hardware implementation registers */
4040
    /* XXX : not implemented */
4041
    spr_register(env, SPR_HID0, "HID0",
4042
                 SPR_NOACCESS, SPR_NOACCESS,
4043
                 &spr_read_generic, &spr_write_clear,
4044
                 0x60000000);
4045
    /* XXX : not implemented */
4046
    spr_register(env, SPR_HID1, "HID1",
4047
                 SPR_NOACCESS, SPR_NOACCESS,
4048
                 &spr_read_generic, &spr_write_generic,
4049
                 0x00000000);
4050
    /* XXX : not implemented */
4051
    spr_register(env, SPR_750_HID2, "HID2",
4052
                 SPR_NOACCESS, SPR_NOACCESS,
4053
                 &spr_read_generic, &spr_write_generic,
4054
                 0x00000000);
4055
    /* XXX : not implemented */
4056
    spr_register(env, SPR_970_HID5, "HID5",
4057
                 SPR_NOACCESS, SPR_NOACCESS,
4058
                 &spr_read_generic, &spr_write_generic,
4059
                 POWERPC970_HID5_INIT);
4060
    /* Memory management */
4061
    /* XXX: not correct */
4062
    gen_low_BATs(env);
4063
    /* XXX : not implemented */
4064
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4065
                 SPR_NOACCESS, SPR_NOACCESS,
4066
                 &spr_read_generic, SPR_NOACCESS,
4067
                 0x00000000); /* TOFIX */
4068
    /* XXX : not implemented */
4069
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4070
                 SPR_NOACCESS, SPR_NOACCESS,
4071
                 &spr_read_generic, &spr_write_generic,
4072
                 0x00000000); /* TOFIX */
4073
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4074
                 SPR_NOACCESS, SPR_NOACCESS,
4075
                 &spr_read_generic, &spr_write_generic,
4076
                 0xFFF00000); /* XXX: This is a hack */
4077
#if !defined(CONFIG_USER_ONLY)
4078
    env->excp_prefix = 0xFFF00000;
4079
#endif
4080
#if !defined(CONFIG_USER_ONLY)
4081
    env->slb_nr = 32;
4082
#endif
4083
    init_excp_970(env);
4084
    env->dcache_line_size = 128;
4085
    env->icache_line_size = 128;
4086
    /* Allocate hardware IRQ controller */
4087
    ppc970_irq_init(env);
4088
}
4089

    
4090
/* PowerPC 970FX (aka G5)                                                    */
4091
#define POWERPC_INSNS_970FX  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4092
                              PPC_64B | PPC_ALTIVEC |                         \
4093
                              PPC_SEGMENT_64B | PPC_SLBI)
4094
#define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
4095
#define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
4096
#define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
4097
#define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
4098
#define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
4099
#define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE)
4100

    
4101
static void init_proc_970FX (CPUPPCState *env)
4102
{
4103
    gen_spr_ne_601(env);
4104
    gen_spr_7xx(env);
4105
    /* Time base */
4106
    gen_tbl(env);
4107
    /* Hardware implementation registers */
4108
    /* XXX : not implemented */
4109
    spr_register(env, SPR_HID0, "HID0",
4110
                 SPR_NOACCESS, SPR_NOACCESS,
4111
                 &spr_read_generic, &spr_write_clear,
4112
                 0x60000000);
4113
    /* XXX : not implemented */
4114
    spr_register(env, SPR_HID1, "HID1",
4115
                 SPR_NOACCESS, SPR_NOACCESS,
4116
                 &spr_read_generic, &spr_write_generic,
4117
                 0x00000000);
4118
    /* XXX : not implemented */
4119
    spr_register(env, SPR_750_HID2, "HID2",
4120
                 SPR_NOACCESS, SPR_NOACCESS,
4121
                 &spr_read_generic, &spr_write_generic,
4122
                 0x00000000);
4123
    /* XXX : not implemented */
4124
    spr_register(env, SPR_970_HID5, "HID5",
4125
                 SPR_NOACCESS, SPR_NOACCESS,
4126
                 &spr_read_generic, &spr_write_generic,
4127
                 POWERPC970_HID5_INIT);
4128
    /* Memory management */
4129
    /* XXX: not correct */
4130
    gen_low_BATs(env);
4131
    /* XXX : not implemented */
4132
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4133
                 SPR_NOACCESS, SPR_NOACCESS,
4134
                 &spr_read_generic, SPR_NOACCESS,
4135
                 0x00000000); /* TOFIX */
4136
    /* XXX : not implemented */
4137
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4138
                 SPR_NOACCESS, SPR_NOACCESS,
4139
                 &spr_read_generic, &spr_write_generic,
4140
                 0x00000000); /* TOFIX */
4141
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4142
                 SPR_NOACCESS, SPR_NOACCESS,
4143
                 &spr_read_generic, &spr_write_generic,
4144
                 0xFFF00000); /* XXX: This is a hack */
4145
#if !defined(CONFIG_USER_ONLY)
4146
    env->excp_prefix = 0xFFF00000;
4147
#endif
4148
#if !defined(CONFIG_USER_ONLY)
4149
    env->slb_nr = 32;
4150
#endif
4151
    init_excp_970(env);
4152
    env->dcache_line_size = 128;
4153
    env->icache_line_size = 128;
4154
    /* Allocate hardware IRQ controller */
4155
    ppc970_irq_init(env);
4156
}
4157

    
4158
/* PowerPC 970 GX                                                            */
4159
#define POWERPC_INSNS_970GX  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4160
                              PPC_64B | PPC_ALTIVEC |                         \
4161
                              PPC_SEGMENT_64B | PPC_SLBI)
4162
#define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
4163
#define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
4164
#define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
4165
#define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
4166
#define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
4167
#define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE)
4168

    
4169
static void init_proc_970GX (CPUPPCState *env)
4170
{
4171
    gen_spr_ne_601(env);
4172
    gen_spr_7xx(env);
4173
    /* Time base */
4174
    gen_tbl(env);
4175
    /* Hardware implementation registers */
4176
    /* XXX : not implemented */
4177
    spr_register(env, SPR_HID0, "HID0",
4178
                 SPR_NOACCESS, SPR_NOACCESS,
4179
                 &spr_read_generic, &spr_write_clear,
4180
                 0x60000000);
4181
    /* XXX : not implemented */
4182
    spr_register(env, SPR_HID1, "HID1",
4183
                 SPR_NOACCESS, SPR_NOACCESS,
4184
                 &spr_read_generic, &spr_write_generic,
4185
                 0x00000000);
4186
    /* XXX : not implemented */
4187
    spr_register(env, SPR_750_HID2, "HID2",
4188
                 SPR_NOACCESS, SPR_NOACCESS,
4189
                 &spr_read_generic, &spr_write_generic,
4190
                 0x00000000);
4191
    /* XXX : not implemented */
4192
    spr_register(env, SPR_970_HID5, "HID5",
4193
                 SPR_NOACCESS, SPR_NOACCESS,
4194
                 &spr_read_generic, &spr_write_generic,
4195
                 POWERPC970_HID5_INIT);
4196
    /* Memory management */
4197
    /* XXX: not correct */
4198
    gen_low_BATs(env);
4199
    /* XXX : not implemented */
4200
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4201
                 SPR_NOACCESS, SPR_NOACCESS,
4202
                 &spr_read_generic, SPR_NOACCESS,
4203
                 0x00000000); /* TOFIX */
4204
    /* XXX : not implemented */
4205
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4206
                 SPR_NOACCESS, SPR_NOACCESS,
4207
                 &spr_read_generic, &spr_write_generic,
4208
                 0x00000000); /* TOFIX */
4209
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4210
                 SPR_NOACCESS, SPR_NOACCESS,
4211
                 &spr_read_generic, &spr_write_generic,
4212
                 0xFFF00000); /* XXX: This is a hack */
4213
#if !defined(CONFIG_USER_ONLY)
4214
    env->excp_prefix = 0xFFF00000;
4215
#endif
4216
#if !defined(CONFIG_USER_ONLY)
4217
    env->slb_nr = 32;
4218
#endif
4219
    init_excp_970(env);
4220
    env->dcache_line_size = 128;
4221
    env->icache_line_size = 128;
4222
    /* Allocate hardware IRQ controller */
4223
    ppc970_irq_init(env);
4224
}
4225

    
4226
/* PowerPC 620                                                               */
4227
#define POWERPC_INSNS_620    (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
4228
                              PPC_64B | PPC_SLBI)
4229
#define POWERPC_MSRM_620     (0x800000000005FF73ULL)
4230
#define POWERPC_MMU_620      (POWERPC_MMU_64B)
4231
#define POWERPC_EXCP_620     (POWERPC_EXCP_970)
4232
#define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_970)
4233
#define POWERPC_BFDM_620     (bfd_mach_ppc64)
4234
#define POWERPC_FLAG_620     (POWERPC_FLAG_NONE)
4235

    
4236
__attribute__ (( unused ))
4237
static void init_proc_620 (CPUPPCState *env)
4238
{
4239
    gen_spr_ne_601(env);
4240
    gen_spr_620(env);
4241
    /* Time base */
4242
    gen_tbl(env);
4243
    /* Hardware implementation registers */
4244
    /* XXX : not implemented */
4245
    spr_register(env, SPR_HID0, "HID0",
4246
                 SPR_NOACCESS, SPR_NOACCESS,
4247
                 &spr_read_generic, &spr_write_generic,
4248
                 0x00000000);
4249
    /* Memory management */
4250
    gen_low_BATs(env);
4251
    gen_high_BATs(env);
4252
    init_excp_620(env);
4253
    env->dcache_line_size = 64;
4254
    env->icache_line_size = 64;
4255
    /* XXX: TODO: initialize internal interrupt controller */
4256
}
4257
#endif /* defined (TARGET_PPC64) */
4258

    
4259
/* Default 32 bits PowerPC target will be 604 */
4260
#define CPU_POWERPC_PPC32     CPU_POWERPC_604
4261
#define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
4262
#define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
4263
#define POWERPC_MMU_PPC32     POWERPC_MMU_604
4264
#define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
4265
#define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
4266
#define init_proc_PPC32       init_proc_604
4267
#define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
4268
#define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
4269

    
4270
/* Default 64 bits PowerPC target will be 970 FX */
4271
#define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
4272
#define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
4273
#define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
4274
#define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
4275
#define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
4276
#define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
4277
#define init_proc_PPC64       init_proc_970FX
4278
#define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
4279
#define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
4280

    
4281
/* Default PowerPC target will be PowerPC 32 */
4282
#if defined (TARGET_PPC64) && 0 // XXX: TODO
4283
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
4284
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4285
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
4286
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
4287
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
4288
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4289
#define init_proc_DEFAULT     init_proc_PPC64
4290
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
4291
#define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
4292
#else
4293
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
4294
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4295
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
4296
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
4297
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
4298
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4299
#define init_proc_DEFAULT     init_proc_PPC32
4300
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
4301
#define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
4302
#endif
4303

    
4304
/*****************************************************************************/
4305
/* PVR definitions for most known PowerPC                                    */
4306
enum {
4307
    /* PowerPC 401 family */
4308
    /* Generic PowerPC 401 */
4309
#define CPU_POWERPC_401       CPU_POWERPC_401G2
4310
    /* PowerPC 401 cores */
4311
    CPU_POWERPC_401A1       = 0x00210000,
4312
    CPU_POWERPC_401B2       = 0x00220000,
4313
#if 0
4314
    CPU_POWERPC_401B3       = xxx,
4315
#endif
4316
    CPU_POWERPC_401C2       = 0x00230000,
4317
    CPU_POWERPC_401D2       = 0x00240000,
4318
    CPU_POWERPC_401E2       = 0x00250000,
4319
    CPU_POWERPC_401F2       = 0x00260000,
4320
    CPU_POWERPC_401G2       = 0x00270000,
4321
    /* PowerPC 401 microcontrolers */
4322
#if 0
4323
    CPU_POWERPC_401GF       = xxx,
4324
#endif
4325
#define CPU_POWERPC_IOP480    CPU_POWERPC_401B2
4326
    /* IBM Processor for Network Resources */
4327
    CPU_POWERPC_COBRA       = 0x10100000, /* XXX: 405 ? */
4328
#if 0
4329
    CPU_POWERPC_XIPCHIP     = xxx,
4330
#endif
4331
    /* PowerPC 403 family */
4332
    /* Generic PowerPC 403 */
4333
#define CPU_POWERPC_403       CPU_POWERPC_403GC
4334
    /* PowerPC 403 microcontrollers */
4335
    CPU_POWERPC_403GA       = 0x00200011,
4336
    CPU_POWERPC_403GB       = 0x00200100,
4337
    CPU_POWERPC_403GC       = 0x00200200,
4338
    CPU_POWERPC_403GCX      = 0x00201400,
4339
#if 0
4340
    CPU_POWERPC_403GP       = xxx,
4341
#endif
4342
    /* PowerPC 405 family */
4343
    /* Generic PowerPC 405 */
4344
#define CPU_POWERPC_405       CPU_POWERPC_405D4
4345
    /* PowerPC 405 cores */
4346
#if 0
4347
    CPU_POWERPC_405A3       = xxx,
4348
#endif
4349
#if 0
4350
    CPU_POWERPC_405A4       = xxx,
4351
#endif
4352
#if 0
4353
    CPU_POWERPC_405B3       = xxx,
4354
#endif
4355
#if 0
4356
    CPU_POWERPC_405B4       = xxx,
4357
#endif
4358
#if 0
4359
    CPU_POWERPC_405C3       = xxx,
4360
#endif
4361
#if 0
4362
    CPU_POWERPC_405C4       = xxx,
4363
#endif
4364
    CPU_POWERPC_405D2       = 0x20010000,
4365
#if 0
4366
    CPU_POWERPC_405D3       = xxx,
4367
#endif
4368
    CPU_POWERPC_405D4       = 0x41810000,
4369
#if 0
4370
    CPU_POWERPC_405D5       = xxx,
4371
#endif
4372
#if 0
4373
    CPU_POWERPC_405E4       = xxx,
4374
#endif
4375
#if 0
4376
    CPU_POWERPC_405F4       = xxx,
4377
#endif
4378
#if 0
4379
    CPU_POWERPC_405F5       = xxx,
4380
#endif
4381
#if 0
4382
    CPU_POWERPC_405F6       = xxx,
4383
#endif
4384
    /* PowerPC 405 microcontrolers */
4385
    /* XXX: missing 0x200108a0 */
4386
#define CPU_POWERPC_405CR     CPU_POWERPC_405CRc
4387
    CPU_POWERPC_405CRa      = 0x40110041,
4388
    CPU_POWERPC_405CRb      = 0x401100C5,
4389
    CPU_POWERPC_405CRc      = 0x40110145,
4390
    CPU_POWERPC_405EP       = 0x51210950,
4391
#if 0
4392
    CPU_POWERPC_405EXr      = xxx,
4393
#endif
4394
    CPU_POWERPC_405EZ       = 0x41511460, /* 0x51210950 ? */
4395
#if 0
4396
    CPU_POWERPC_405FX       = xxx,
4397
#endif
4398
#define CPU_POWERPC_405GP     CPU_POWERPC_405GPd
4399
    CPU_POWERPC_405GPa      = 0x40110000,
4400
    CPU_POWERPC_405GPb      = 0x40110040,
4401
    CPU_POWERPC_405GPc      = 0x40110082,
4402
    CPU_POWERPC_405GPd      = 0x401100C4,
4403
#define CPU_POWERPC_405GPe    CPU_POWERPC_405CRc
4404
    CPU_POWERPC_405GPR      = 0x50910951,
4405
#if 0
4406
    CPU_POWERPC_405H        = xxx,
4407
#endif
4408
#if 0
4409
    CPU_POWERPC_405L        = xxx,
4410
#endif
4411
    CPU_POWERPC_405LP       = 0x41F10000,
4412
#if 0
4413
    CPU_POWERPC_405PM       = xxx,
4414
#endif
4415
#if 0
4416
    CPU_POWERPC_405PS       = xxx,
4417
#endif
4418
#if 0
4419
    CPU_POWERPC_405S        = xxx,
4420
#endif
4421
    /* IBM network processors */
4422
    CPU_POWERPC_NPE405H     = 0x414100C0,
4423
    CPU_POWERPC_NPE405H2    = 0x41410140,
4424
    CPU_POWERPC_NPE405L     = 0x416100C0,
4425
    CPU_POWERPC_NPE4GS3     = 0x40B10000,
4426
#if 0
4427
    CPU_POWERPC_NPCxx1      = xxx,
4428
#endif
4429
#if 0
4430
    CPU_POWERPC_NPR161      = xxx,
4431
#endif
4432
#if 0
4433
    CPU_POWERPC_LC77700     = xxx,
4434
#endif
4435
    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4436
#if 0
4437
    CPU_POWERPC_STB01000    = xxx,
4438
#endif
4439
#if 0
4440
    CPU_POWERPC_STB01010    = xxx,
4441
#endif
4442
#if 0
4443
    CPU_POWERPC_STB0210     = xxx, /* 401B3 */
4444
#endif
4445
    CPU_POWERPC_STB03       = 0x40310000, /* 0x40130000 ? */
4446
#if 0
4447
    CPU_POWERPC_STB043      = xxx,
4448
#endif
4449
#if 0
4450
    CPU_POWERPC_STB045      = xxx,
4451
#endif
4452
    CPU_POWERPC_STB04       = 0x41810000,
4453
    CPU_POWERPC_STB25       = 0x51510950,
4454
#if 0
4455
    CPU_POWERPC_STB130      = xxx,
4456
#endif
4457
    /* Xilinx cores */
4458
    CPU_POWERPC_X2VP4       = 0x20010820,
4459
#define CPU_POWERPC_X2VP7     CPU_POWERPC_X2VP4
4460
    CPU_POWERPC_X2VP20      = 0x20010860,
4461
#define CPU_POWERPC_X2VP50    CPU_POWERPC_X2VP20
4462
#if 0
4463
    CPU_POWERPC_ZL10310     = xxx,
4464
#endif
4465
#if 0
4466
    CPU_POWERPC_ZL10311     = xxx,
4467
#endif
4468
#if 0
4469
    CPU_POWERPC_ZL10320     = xxx,
4470
#endif
4471
#if 0
4472
    CPU_POWERPC_ZL10321     = xxx,
4473
#endif
4474
    /* PowerPC 440 family */
4475
    /* Generic PowerPC 440 */
4476
#define CPU_POWERPC_440       CPU_POWERPC_440GXf
4477
    /* PowerPC 440 cores */
4478
#if 0
4479
    CPU_POWERPC_440A4       = xxx,
4480
#endif
4481
#if 0
4482
    CPU_POWERPC_440A5       = xxx,
4483
#endif
4484
#if 0
4485
    CPU_POWERPC_440B4       = xxx,
4486
#endif
4487
#if 0
4488
    CPU_POWERPC_440F5       = xxx,
4489
#endif
4490
#if 0
4491
    CPU_POWERPC_440G5       = xxx,
4492
#endif
4493
#if 0
4494
    CPU_POWERPC_440H4       = xxx,
4495
#endif
4496
#if 0
4497
    CPU_POWERPC_440H6       = xxx,
4498
#endif
4499
    /* PowerPC 440 microcontrolers */
4500
#define CPU_POWERPC_440EP     CPU_POWERPC_440EPb
4501
    CPU_POWERPC_440EPa      = 0x42221850,
4502
    CPU_POWERPC_440EPb      = 0x422218D3,
4503
#define CPU_POWERPC_440GP     CPU_POWERPC_440GPc
4504
    CPU_POWERPC_440GPb      = 0x40120440,
4505
    CPU_POWERPC_440GPc      = 0x40120481,
4506
#define CPU_POWERPC_440GR     CPU_POWERPC_440GRa
4507
#define CPU_POWERPC_440GRa    CPU_POWERPC_440EPb
4508
    CPU_POWERPC_440GRX      = 0x200008D0,
4509
#define CPU_POWERPC_440EPX    CPU_POWERPC_440GRX
4510
#define CPU_POWERPC_440GX     CPU_POWERPC_440GXf
4511
    CPU_POWERPC_440GXa      = 0x51B21850,
4512
    CPU_POWERPC_440GXb      = 0x51B21851,
4513
    CPU_POWERPC_440GXc      = 0x51B21892,
4514
    CPU_POWERPC_440GXf      = 0x51B21894,
4515
#if 0
4516
    CPU_POWERPC_440S        = xxx,
4517
#endif
4518
    CPU_POWERPC_440SP       = 0x53221850,
4519
    CPU_POWERPC_440SP2      = 0x53221891,
4520
    CPU_POWERPC_440SPE      = 0x53421890,
4521
    /* PowerPC 460 family */
4522
#if 0
4523
    /* Generic PowerPC 464 */
4524
#define CPU_POWERPC_464       CPU_POWERPC_464H90
4525
#endif
4526
    /* PowerPC 464 microcontrolers */
4527
#if 0
4528
    CPU_POWERPC_464H90      = xxx,
4529
#endif
4530
#if 0
4531
    CPU_POWERPC_464H90FP    = xxx,
4532
#endif
4533
    /* Freescale embedded PowerPC cores */
4534
    /* e200 family */
4535
#define CPU_POWERPC_e200      CPU_POWERPC_e200z6
4536
#if 0
4537
    CPU_POWERPC_e200z0      = xxx,
4538
#endif
4539
#if 0
4540
    CPU_POWERPC_e200z3      = xxx,
4541
#endif
4542
    CPU_POWERPC_e200z5      = 0x81000000,
4543
    CPU_POWERPC_e200z6      = 0x81120000,
4544
    /* e300 family */
4545
#define CPU_POWERPC_e300      CPU_POWERPC_e300c3
4546
    CPU_POWERPC_e300c1      = 0x00830000,
4547
    CPU_POWERPC_e300c2      = 0x00840000,
4548
    CPU_POWERPC_e300c3      = 0x00850000,
4549
    /* e500 family */
4550
#define CPU_POWERPC_e500      CPU_POWERPC_e500_v22
4551
    CPU_POWERPC_e500_v11    = 0x80200010,
4552
    CPU_POWERPC_e500_v12    = 0x80200020,
4553
    CPU_POWERPC_e500_v21    = 0x80210010,
4554
    CPU_POWERPC_e500_v22    = 0x80210020,
4555
#if 0
4556
    CPU_POWERPC_e500mc      = xxx,
4557
#endif
4558
    /* e600 family */
4559
    CPU_POWERPC_e600        = 0x80040010,
4560
    /* PowerPC MPC 5xx cores */
4561
    CPU_POWERPC_5xx         = 0x00020020,
4562
    /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4563
    CPU_POWERPC_8xx         = 0x00500000,
4564
    /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4565
    CPU_POWERPC_82xx_HIP3   = 0x00810101,
4566
    CPU_POWERPC_82xx_HIP4   = 0x80811014,
4567
    CPU_POWERPC_827x        = 0x80822013,
4568
    /* PowerPC 6xx cores */
4569
    CPU_POWERPC_601         = 0x00010001,
4570
    CPU_POWERPC_601a        = 0x00010002,
4571
    CPU_POWERPC_602         = 0x00050100,
4572
    CPU_POWERPC_603         = 0x00030100,
4573
#define CPU_POWERPC_603E      CPU_POWERPC_603E_v41
4574
    CPU_POWERPC_603E_v11    = 0x00060101,
4575
    CPU_POWERPC_603E_v12    = 0x00060102,
4576
    CPU_POWERPC_603E_v13    = 0x00060103,
4577
    CPU_POWERPC_603E_v14    = 0x00060104,
4578
    CPU_POWERPC_603E_v22    = 0x00060202,
4579
    CPU_POWERPC_603E_v3     = 0x00060300,
4580
    CPU_POWERPC_603E_v4     = 0x00060400,
4581
    CPU_POWERPC_603E_v41    = 0x00060401,
4582
    CPU_POWERPC_603E7t      = 0x00071201,
4583
    CPU_POWERPC_603E7v      = 0x00070100,
4584
    CPU_POWERPC_603E7v1     = 0x00070101,
4585
    CPU_POWERPC_603E7v2     = 0x00070201,
4586
    CPU_POWERPC_603E7       = 0x00070200,
4587
    CPU_POWERPC_603P        = 0x00070000,
4588
#define CPU_POWERPC_603R      CPU_POWERPC_603E7t
4589
    CPU_POWERPC_G2          = 0x00810011,
4590
#if 0 // Linux pretends the MSB is zero...
4591
    CPU_POWERPC_G2H4        = 0x80811010,
4592
    CPU_POWERPC_G2gp        = 0x80821010,
4593
    CPU_POWERPC_G2ls        = 0x90810010,
4594
    CPU_POWERPC_G2LE        = 0x80820010,
4595
    CPU_POWERPC_G2LEgp      = 0x80822010,
4596
    CPU_POWERPC_G2LEls      = 0xA0822010,
4597
#else
4598
    CPU_POWERPC_G2H4        = 0x00811010,
4599
    CPU_POWERPC_G2gp        = 0x00821010,
4600
    CPU_POWERPC_G2ls        = 0x10810010,
4601
    CPU_POWERPC_G2LE        = 0x00820010,
4602
    CPU_POWERPC_G2LEgp      = 0x00822010,
4603
    CPU_POWERPC_G2LEls      = 0x20822010,
4604
#endif
4605
    CPU_POWERPC_604         = 0x00040103,
4606
#define CPU_POWERPC_604E      CPU_POWERPC_604E_v24
4607
    CPU_POWERPC_604E_v10    = 0x00090100, /* Also 2110 & 2120 */
4608
    CPU_POWERPC_604E_v22    = 0x00090202,
4609
    CPU_POWERPC_604E_v24    = 0x00090204,
4610
    CPU_POWERPC_604R        = 0x000a0101, /* Also 0x00093102 */
4611
#if 0
4612
    CPU_POWERPC_604EV       = xxx,
4613
#endif
4614
    /* PowerPC 740/750 cores (aka G3) */
4615
    /* XXX: missing 0x00084202 */
4616
#define CPU_POWERPC_7x0       CPU_POWERPC_7x0_v31
4617
    CPU_POWERPC_7x0_v20     = 0x00080200,
4618
    CPU_POWERPC_7x0_v21     = 0x00080201,
4619
    CPU_POWERPC_7x0_v22     = 0x00080202,
4620
    CPU_POWERPC_7x0_v30     = 0x00080300,
4621
    CPU_POWERPC_7x0_v31     = 0x00080301,
4622
    CPU_POWERPC_740E        = 0x00080100,
4623
    CPU_POWERPC_7x0P        = 0x10080000,
4624
    /* XXX: missing 0x00087010 (CL ?) */
4625
    CPU_POWERPC_750CL       = 0x00087200,
4626
#define CPU_POWERPC_750CX     CPU_POWERPC_750CX_v22
4627
    CPU_POWERPC_750CX_v21   = 0x00082201,
4628
    CPU_POWERPC_750CX_v22   = 0x00082202,
4629
#define CPU_POWERPC_750CXE    CPU_POWERPC_750CXE_v31b
4630
    CPU_POWERPC_750CXE_v21  = 0x00082211,
4631
    CPU_POWERPC_750CXE_v22  = 0x00082212,
4632
    CPU_POWERPC_750CXE_v23  = 0x00082213,
4633
    CPU_POWERPC_750CXE_v24  = 0x00082214,
4634
    CPU_POWERPC_750CXE_v24b = 0x00083214,
4635
    CPU_POWERPC_750CXE_v31  = 0x00083211,
4636
    CPU_POWERPC_750CXE_v31b = 0x00083311,
4637
    CPU_POWERPC_750CXR      = 0x00083410,
4638
    CPU_POWERPC_750E        = 0x00080200,
4639
    CPU_POWERPC_750FL       = 0x700A0203,
4640
#define CPU_POWERPC_750FX     CPU_POWERPC_750FX_v23
4641
    CPU_POWERPC_750FX_v10   = 0x70000100,
4642
    CPU_POWERPC_750FX_v20   = 0x70000200,
4643
    CPU_POWERPC_750FX_v21   = 0x70000201,
4644
    CPU_POWERPC_750FX_v22   = 0x70000202,
4645
    CPU_POWERPC_750FX_v23   = 0x70000203,
4646
    CPU_POWERPC_750GL       = 0x70020102,
4647
#define CPU_POWERPC_750GX     CPU_POWERPC_750GX_v12
4648
    CPU_POWERPC_750GX_v10   = 0x70020100,
4649
    CPU_POWERPC_750GX_v11   = 0x70020101,
4650
    CPU_POWERPC_750GX_v12   = 0x70020102,
4651
#define CPU_POWERPC_750L      CPU_POWERPC_750L_v32 /* Aka LoneStar */
4652
    CPU_POWERPC_750L_v22    = 0x00088202,
4653
    CPU_POWERPC_750L_v30    = 0x00088300,
4654
    CPU_POWERPC_750L_v32    = 0x00088302,
4655
    /* PowerPC 745/755 cores */
4656
#define CPU_POWERPC_7x5       CPU_POWERPC_7x5_v28
4657
    CPU_POWERPC_7x5_v10     = 0x00083100,
4658
    CPU_POWERPC_7x5_v11     = 0x00083101,
4659
    CPU_POWERPC_7x5_v20     = 0x00083200,
4660
    CPU_POWERPC_7x5_v21     = 0x00083201,
4661
    CPU_POWERPC_7x5_v22     = 0x00083202, /* aka D */
4662
    CPU_POWERPC_7x5_v23     = 0x00083203, /* aka E */
4663
    CPU_POWERPC_7x5_v24     = 0x00083204,
4664
    CPU_POWERPC_7x5_v25     = 0x00083205,
4665
    CPU_POWERPC_7x5_v26     = 0x00083206,
4666
    CPU_POWERPC_7x5_v27     = 0x00083207,
4667
    CPU_POWERPC_7x5_v28     = 0x00083208,
4668
#if 0
4669
    CPU_POWERPC_7x5P        = xxx,
4670
#endif
4671
    /* PowerPC 74xx cores (aka G4) */
4672
    /* XXX: missing 0x000C1101 */
4673
#define CPU_POWERPC_7400      CPU_POWERPC_7400_v29
4674
    CPU_POWERPC_7400_v10    = 0x000C0100,
4675
    CPU_POWERPC_7400_v11    = 0x000C0101,
4676
    CPU_POWERPC_7400_v20    = 0x000C0200,
4677
    CPU_POWERPC_7400_v22    = 0x000C0202,
4678
    CPU_POWERPC_7400_v26    = 0x000C0206,
4679
    CPU_POWERPC_7400_v27    = 0x000C0207,
4680
    CPU_POWERPC_7400_v28    = 0x000C0208,
4681
    CPU_POWERPC_7400_v29    = 0x000C0209,
4682
#define CPU_POWERPC_7410      CPU_POWERPC_7410_v14
4683
    CPU_POWERPC_7410_v10    = 0x800C1100,
4684
    CPU_POWERPC_7410_v11    = 0x800C1101,
4685
    CPU_POWERPC_7410_v12    = 0x800C1102, /* aka C */
4686
    CPU_POWERPC_7410_v13    = 0x800C1103, /* aka D */
4687
    CPU_POWERPC_7410_v14    = 0x800C1104, /* aka E */
4688
#define CPU_POWERPC_7448      CPU_POWERPC_7448_v21
4689
    CPU_POWERPC_7448_v10    = 0x80040100,
4690
    CPU_POWERPC_7448_v11    = 0x80040101,
4691
    CPU_POWERPC_7448_v20    = 0x80040200,
4692
    CPU_POWERPC_7448_v21    = 0x80040201,
4693
#define CPU_POWERPC_7450      CPU_POWERPC_7450_v21
4694
    CPU_POWERPC_7450_v10    = 0x80000100,
4695
    CPU_POWERPC_7450_v11    = 0x80000101,
4696
    CPU_POWERPC_7450_v12    = 0x80000102,
4697
    CPU_POWERPC_7450_v20    = 0x80000200, /* aka D: 2.04 */
4698
    CPU_POWERPC_7450_v21    = 0x80000201, /* aka E */
4699
    CPU_POWERPC_74x1        = 0x80000203,
4700
    CPU_POWERPC_74x1G       = 0x80000210, /* aka G: 2.3 */
4701
    /* XXX: missing 0x80010200 */
4702
#define CPU_POWERPC_74x5      CPU_POWERPC_74x5_v32
4703
    CPU_POWERPC_74x5_v10    = 0x80010100,
4704
    CPU_POWERPC_74x5_v21    = 0x80010201, /* aka C: 2.1 */
4705
    CPU_POWERPC_74x5_v32    = 0x80010302,
4706
    CPU_POWERPC_74x5_v33    = 0x80010303, /* aka F: 3.3 */
4707
    CPU_POWERPC_74x5_v34    = 0x80010304, /* aka G: 3.4 */
4708
#define CPU_POWERPC_74x7      CPU_POWERPC_74x7_v12
4709
    CPU_POWERPC_74x7_v10    = 0x80020100, /* aka A: 1.0 */
4710
    CPU_POWERPC_74x7_v11    = 0x80030101, /* aka B: 1.1 */
4711
    CPU_POWERPC_74x7_v12    = 0x80020102, /* aka C: 1.2 */
4712
    /* 64 bits PowerPC */
4713
#if defined(TARGET_PPC64)
4714
    CPU_POWERPC_620         = 0x00140000,
4715
    CPU_POWERPC_630         = 0x00400000,
4716
    CPU_POWERPC_631         = 0x00410104,
4717
    CPU_POWERPC_POWER4      = 0x00350000,
4718
    CPU_POWERPC_POWER4P     = 0x00380000,
4719
    CPU_POWERPC_POWER5      = 0x003A0203,
4720
#define CPU_POWERPC_POWER5GR  CPU_POWERPC_POWER5
4721
    CPU_POWERPC_POWER5P     = 0x003B0000,
4722
#define CPU_POWERPC_POWER5GS  CPU_POWERPC_POWER5P
4723
    CPU_POWERPC_POWER6      = 0x003E0000,
4724
    CPU_POWERPC_POWER6_5    = 0x0F000001, /* POWER6 running POWER5 mode */
4725
    CPU_POWERPC_POWER6A     = 0x0F000002,
4726
    CPU_POWERPC_970         = 0x00390202,
4727
#define CPU_POWERPC_970FX     CPU_POWERPC_970FX_v31
4728
    CPU_POWERPC_970FX_v10   = 0x00391100,
4729
    CPU_POWERPC_970FX_v20   = 0x003C0200,
4730
    CPU_POWERPC_970FX_v21   = 0x003C0201,