Revision 417f38f0
| b/target-mips/op.c | ||
|---|---|---|
| 799 | 799 |
} |
| 800 | 800 |
FLOAT_OP(cvts, d) |
| 801 | 801 |
{
|
| 802 |
FST2 = float64_to_float32(WT0, &env->fp_status);
|
|
| 802 |
FST2 = float64_to_float32(FDT0, &env->fp_status);
|
|
| 803 | 803 |
DEBUG_FPU_STATE(); |
| 804 | 804 |
RETURN(); |
| 805 | 805 |
} |
| b/target-mips/translate.c | ||
|---|---|---|
| 1791 | 1791 |
break; |
| 1792 | 1792 |
case FOP(32, 17): /* cvt.s.d */ |
| 1793 | 1793 |
CHECK_FR(ctx, fs | fd); |
| 1794 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
| 1794 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
| 1795 | 1795 |
gen_op_float_cvts_d(); |
| 1796 | 1796 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 1797 | 1797 |
opn = "cvt.s.d"; |
| ... | ... | |
| 1812 | 1812 |
break; |
| 1813 | 1813 |
case FOP(36, 17): /* cvt.w.d */ |
| 1814 | 1814 |
CHECK_FR(ctx, fs | fd); |
| 1815 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
| 1815 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
| 1816 | 1816 |
gen_op_float_cvtw_d(); |
| 1817 | 1817 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 1818 | 1818 |
opn = "cvt.w.d"; |
| ... | ... | |
| 2089 | 2089 |
case 0x39: /* SWC1 */ |
| 2090 | 2090 |
case 0x3D: /* SDC1 */ |
| 2091 | 2091 |
#if defined(MIPS_USES_FPU) |
| 2092 |
save_cpu_state(ctx, 1); |
|
| 2092 | 2093 |
gen_op_cp1_enabled(); |
| 2093 | 2094 |
gen_flt_ldst(ctx, op, rt, rs, imm); |
| 2094 | 2095 |
#else |
| ... | ... | |
| 2098 | 2099 |
|
| 2099 | 2100 |
case 0x11: /* CP1 opcode */ |
| 2100 | 2101 |
#if defined(MIPS_USES_FPU) |
| 2102 |
save_cpu_state(ctx, 1); |
|
| 2101 | 2103 |
gen_op_cp1_enabled(); |
| 2102 | 2104 |
op1 = ((ctx->opcode >> 21) & 0x1F); |
| 2103 | 2105 |
switch (op1) {
|
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