Archipelago » qemu

/*

 *  MIPS emulation helpers for qemu.

 *

 *  Copyright (c) 2004-2005 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA

 */

#include <stdlib.h>

#include "exec.h"

#include "host-utils.h"

#include "helper.h"

/*****************************************************************************/

/* Exceptions processing helpers */

void helper_raise_exception_err (uint32_t exception, int error_code)

{

#if 1

    if (exception < 0x100)

        qemu_log("%s: %d %d\n", __func__, exception, error_code);

#endif

    env->exception_index = exception;

    env->error_code = error_code;

    cpu_loop_exit();

}

void helper_raise_exception (uint32_t exception)

{

    helper_raise_exception_err(exception, 0);

}

void helper_interrupt_restart (void)

{

    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&

        !(env->CP0_Status & (1 << CP0St_ERL)) &&

        !(env->hflags & MIPS_HFLAG_DM) &&

        (env->CP0_Status & (1 << CP0St_IE)) &&

        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {

        env->CP0_Cause &= ~(0x1f << CP0Ca_EC);

        helper_raise_exception(EXCP_EXT_INTERRUPT);

    }

}

#if !defined(CONFIG_USER_ONLY)

static void do_restore_state (void *pc_ptr)

{

    TranslationBlock *tb;

    unsigned long pc = (unsigned long) pc_ptr;

    tb = tb_find_pc (pc);

    if (tb) {

        cpu_restore_state (tb, env, pc, NULL);

    }

}

#endif

target_ulong helper_clo (target_ulong t0)

{

    return clo32(t0);

}

target_ulong helper_clz (target_ulong t0)

{

    return clz32(t0);

}

#if defined(TARGET_MIPS64)

target_ulong helper_dclo (target_ulong t0)

{

    return clo64(t0);

}

target_ulong helper_dclz (target_ulong t0)

{

    return clz64(t0);

}

#endif /* TARGET_MIPS64 */

/* 64 bits arithmetic for 32 bits hosts */

static inline uint64_t get_HILO (void)

{

    return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];

}

static inline void set_HILO (uint64_t HILO)

{

    env->active_tc.LO[0] = (int32_t)HILO;

    env->active_tc.HI[0] = (int32_t)(HILO >> 32);

}

static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)

{

    env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);

    t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);

}

static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)

{

    t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);

    env->active_tc.HI[0] = (int32_t)(HILO >> 32);

}

/* Multiplication variants of the vr54xx. */

target_ulong helper_muls (target_ulong t0, target_ulong t1)

{

    set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));

    return t0;

}

target_ulong helper_mulsu (target_ulong t0, target_ulong t1)

{

    set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));

    return t0;

}

target_ulong helper_macc (target_ulong t0, target_ulong t1)

{

    set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));

    return t0;

}

target_ulong helper_macchi (target_ulong t0, target_ulong t1)

{

    set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));

    return t0;

}

target_ulong helper_maccu (target_ulong t0, target_ulong t1)

{

    set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));

    return t0;

}

target_ulong helper_macchiu (target_ulong t0, target_ulong t1)

{

    set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));

    return t0;

}

target_ulong helper_msac (target_ulong t0, target_ulong t1)

{

    set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));

    return t0;

}

target_ulong helper_msachi (target_ulong t0, target_ulong t1)

{

    set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));

    return t0;

}

target_ulong helper_msacu (target_ulong t0, target_ulong t1)

{

    set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));

    return t0;

}

target_ulong helper_msachiu (target_ulong t0, target_ulong t1)

{

    set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));

    return t0;

}

target_ulong helper_mulhi (target_ulong t0, target_ulong t1)

{

    set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);

    return t0;

}

target_ulong helper_mulhiu (target_ulong t0, target_ulong t1)

{

    set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);

    return t0;

}

target_ulong helper_mulshi (target_ulong t0, target_ulong t1)

{

    set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));

    return t0;

}

target_ulong helper_mulshiu (target_ulong t0, target_ulong t1)

{

    set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));

    return t0;

}

#ifdef TARGET_MIPS64

void helper_dmult (target_ulong t0, target_ulong t1)

{

    muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);

}

void helper_dmultu (target_ulong t0, target_ulong t1)

{

    mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);

}

#endif

#ifdef TARGET_WORDS_BIGENDIAN

#define GET_LMASK(v) ((v) & 3)

#define GET_OFFSET(addr, offset) (addr + (offset))

#else

#define GET_LMASK(v) (((v) & 3) ^ 3)

#define GET_OFFSET(addr, offset) (addr - (offset))

#endif

target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)

{

    target_ulong tmp;

#ifdef CONFIG_USER_ONLY

#define ldfun ldub_raw

#else

    int (*ldfun)(target_ulong);

    switch (mem_idx)

    {

    case 0: ldfun = ldub_kernel; break;

    case 1: ldfun = ldub_super; break;

    default:

    case 2: ldfun = ldub_user; break;

    }

#endif

    tmp = ldfun(t0);

    t1 = (t1 & 0x00FFFFFF) | (tmp << 24);

    if (GET_LMASK(t0) <= 2) {

        tmp = ldfun(GET_OFFSET(t0, 1));

        t1 = (t1 & 0xFF00FFFF) | (tmp << 16);

    }

    if (GET_LMASK(t0) <= 1) {

        tmp = ldfun(GET_OFFSET(t0, 2));

        t1 = (t1 & 0xFFFF00FF) | (tmp << 8);

    }

    if (GET_LMASK(t0) == 0) {

        tmp = ldfun(GET_OFFSET(t0, 3));

        t1 = (t1 & 0xFFFFFF00) | tmp;

    }

    return (int32_t)t1;

}

target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)

{

    target_ulong tmp;

#ifdef CONFIG_USER_ONLY

#define ldfun ldub_raw

#else

    int (*ldfun)(target_ulong);

    switch (mem_idx)

    {

    case 0: ldfun = ldub_kernel; break;

    case 1: ldfun = ldub_super; break;

    default:

    case 2: ldfun = ldub_user; break;

    }

#endif

    tmp = ldfun(t0);

    t1 = (t1 & 0xFFFFFF00) | tmp;

    if (GET_LMASK(t0) >= 1) {

        tmp = ldfun(GET_OFFSET(t0, -1));

        t1 = (t1 & 0xFFFF00FF) | (tmp << 8);

    }

    if (GET_LMASK(t0) >= 2) {

        tmp = ldfun(GET_OFFSET(t0, -2));

        t1 = (t1 & 0xFF00FFFF) | (tmp << 16);

    }

    if (GET_LMASK(t0) == 3) {

        tmp = ldfun(GET_OFFSET(t0, -3));

        t1 = (t1 & 0x00FFFFFF) | (tmp << 24);

    }

    return (int32_t)t1;

}

void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)

{

#ifdef CONFIG_USER_ONLY

#define stfun stb_raw

#else

    void (*stfun)(target_ulong, int);

    switch (mem_idx)

    {

    case 0: stfun = stb_kernel; break;

    case 1: stfun = stb_super; break;

    default:

    case 2: stfun = stb_user; break;

    }

#endif

    stfun(t0, (uint8_t)(t1 >> 24));

    if (GET_LMASK(t0) <= 2)

        stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));

    if (GET_LMASK(t0) <= 1)

        stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));

    if (GET_LMASK(t0) == 0)

        stfun(GET_OFFSET(t0, 3), (uint8_t)t1);

}

void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)

{

#ifdef CONFIG_USER_ONLY

#define stfun stb_raw

#else

    void (*stfun)(target_ulong, int);

    switch (mem_idx)

    {

    case 0: stfun = stb_kernel; break;

    case 1: stfun = stb_super; break;

    default:

    case 2: stfun = stb_user; break;

    }

#endif

    stfun(t0, (uint8_t)t1);

    if (GET_LMASK(t0) >= 1)

        stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));

    if (GET_LMASK(t0) >= 2)

        stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));

    if (GET_LMASK(t0) == 3)

        stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));

}

#if defined(TARGET_MIPS64)

/* "half" load and stores.  We must do the memory access inline,

   or fault handling won't work.  */

#ifdef TARGET_WORDS_BIGENDIAN

#define GET_LMASK64(v) ((v) & 7)

#else

#define GET_LMASK64(v) (((v) & 7) ^ 7)

#endif

target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)

{

    uint64_t tmp;

#ifdef CONFIG_USER_ONLY

#define ldfun ldub_raw

#else

    int (*ldfun)(target_ulong);

    switch (mem_idx)

    {

    case 0: ldfun = ldub_kernel; break;

    case 1: ldfun = ldub_super; break;

    default:

    case 2: ldfun = ldub_user; break;

    }

#endif

    tmp = ldfun(t0);

    t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);

    if (GET_LMASK64(t0) <= 6) {

        tmp = ldfun(GET_OFFSET(t0, 1));

        t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);

    }

    if (GET_LMASK64(t0) <= 5) {

        tmp = ldfun(GET_OFFSET(t0, 2));

        t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);

    }

    if (GET_LMASK64(t0) <= 4) {

        tmp = ldfun(GET_OFFSET(t0, 3));

        t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);

    }

    if (GET_LMASK64(t0) <= 3) {

        tmp = ldfun(GET_OFFSET(t0, 4));

        t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);

    }

    if (GET_LMASK64(t0) <= 2) {

        tmp = ldfun(GET_OFFSET(t0, 5));

        t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);

    }

    if (GET_LMASK64(t0) <= 1) {

        tmp = ldfun(GET_OFFSET(t0, 6));

        t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);

    }

    if (GET_LMASK64(t0) == 0) {

        tmp = ldfun(GET_OFFSET(t0, 7));

        t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;

    }

    return t1;

}

target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)

{

    uint64_t tmp;

#ifdef CONFIG_USER_ONLY

#define ldfun ldub_raw

#else

    int (*ldfun)(target_ulong);

    switch (mem_idx)

    {

    case 0: ldfun = ldub_kernel; break;

    case 1: ldfun = ldub_super; break;

    default:

    case 2: ldfun = ldub_user; break;

    }

#endif

    tmp = ldfun(t0);

    t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;

    if (GET_LMASK64(t0) >= 1) {

        tmp = ldfun(GET_OFFSET(t0, -1));

        t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);

    }

    if (GET_LMASK64(t0) >= 2) {

        tmp = ldfun(GET_OFFSET(t0, -2));

        t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);

    }

    if (GET_LMASK64(t0) >= 3) {

        tmp = ldfun(GET_OFFSET(t0, -3));

        t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);

    }

    if (GET_LMASK64(t0) >= 4) {

        tmp = ldfun(GET_OFFSET(t0, -4));

        t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);

    }

    if (GET_LMASK64(t0) >= 5) {

        tmp = ldfun(GET_OFFSET(t0, -5));

        t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);

    }

    if (GET_LMASK64(t0) >= 6) {

        tmp = ldfun(GET_OFFSET(t0, -6));

        t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);

    }

    if (GET_LMASK64(t0) == 7) {

        tmp = ldfun(GET_OFFSET(t0, -7));

        t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);

    }

    return t1;

}

void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)

{

#ifdef CONFIG_USER_ONLY

#define stfun stb_raw

#else

    void (*stfun)(target_ulong, int);

    switch (mem_idx)

    {

    case 0: stfun = stb_kernel; break;

    case 1: stfun = stb_super; break;

    default:

    case 2: stfun = stb_user; break;

    }

#endif

    stfun(t0, (uint8_t)(t1 >> 56));

    if (GET_LMASK64(t0) <= 6)

        stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));

    if (GET_LMASK64(t0) <= 5)

        stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));

    if (GET_LMASK64(t0) <= 4)

        stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));

    if (GET_LMASK64(t0) <= 3)

        stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));

    if (GET_LMASK64(t0) <= 2)

        stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));

    if (GET_LMASK64(t0) <= 1)

        stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));

    if (GET_LMASK64(t0) <= 0)

        stfun(GET_OFFSET(t0, 7), (uint8_t)t1);

}

void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)

{

#ifdef CONFIG_USER_ONLY

#define stfun stb_raw

#else

    void (*stfun)(target_ulong, int);

    switch (mem_idx)

    {

    case 0: stfun = stb_kernel; break;

    case 1: stfun = stb_super; break;

     default:

    case 2: stfun = stb_user; break;

    }

#endif

    stfun(t0, (uint8_t)t1);

    if (GET_LMASK64(t0) >= 1)

        stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));

    if (GET_LMASK64(t0) >= 2)

        stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));

    if (GET_LMASK64(t0) >= 3)

        stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));

    if (GET_LMASK64(t0) >= 4)

        stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));

    if (GET_LMASK64(t0) >= 5)

        stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));

    if (GET_LMASK64(t0) >= 6)

        stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));

    if (GET_LMASK64(t0) == 7)

        stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));

}

#endif /* TARGET_MIPS64 */

#ifndef CONFIG_USER_ONLY

/* CP0 helpers */

target_ulong helper_mfc0_mvpcontrol (void)

{

    return env->mvp->CP0_MVPControl;

}

target_ulong helper_mfc0_mvpconf0 (void)

{

    return env->mvp->CP0_MVPConf0;

}

target_ulong helper_mfc0_mvpconf1 (void)

{

    return env->mvp->CP0_MVPConf1;

}

target_ulong helper_mfc0_random (void)

{

    return (int32_t)cpu_mips_get_random(env);

}

target_ulong helper_mfc0_tcstatus (void)

{

    return env->active_tc.CP0_TCStatus;

}

target_ulong helper_mftc0_tcstatus(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    if (other_tc == env->current_tc)

        return env->active_tc.CP0_TCStatus;

    else

        return env->tcs[other_tc].CP0_TCStatus;

}

target_ulong helper_mfc0_tcbind (void)

{

    return env->active_tc.CP0_TCBind;

}

target_ulong helper_mftc0_tcbind(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    if (other_tc == env->current_tc)

        return env->active_tc.CP0_TCBind;

    else

        return env->tcs[other_tc].CP0_TCBind;

}

target_ulong helper_mfc0_tcrestart (void)

{

    return env->active_tc.PC;

}

target_ulong helper_mftc0_tcrestart(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    if (other_tc == env->current_tc)

        return env->active_tc.PC;

    else

        return env->tcs[other_tc].PC;

}

target_ulong helper_mfc0_tchalt (void)

{

    return env->active_tc.CP0_TCHalt;

}

target_ulong helper_mftc0_tchalt(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    if (other_tc == env->current_tc)

        return env->active_tc.CP0_TCHalt;

    else

        return env->tcs[other_tc].CP0_TCHalt;

}

target_ulong helper_mfc0_tccontext (void)

{

    return env->active_tc.CP0_TCContext;

}

target_ulong helper_mftc0_tccontext(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    if (other_tc == env->current_tc)

        return env->active_tc.CP0_TCContext;

    else

        return env->tcs[other_tc].CP0_TCContext;

}

target_ulong helper_mfc0_tcschedule (void)

{

    return env->active_tc.CP0_TCSchedule;

}

target_ulong helper_mftc0_tcschedule(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    if (other_tc == env->current_tc)

        return env->active_tc.CP0_TCSchedule;

    else

        return env->tcs[other_tc].CP0_TCSchedule;

}

target_ulong helper_mfc0_tcschefback (void)

{

    return env->active_tc.CP0_TCScheFBack;

}

target_ulong helper_mftc0_tcschefback(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    if (other_tc == env->current_tc)

        return env->active_tc.CP0_TCScheFBack;

    else

        return env->tcs[other_tc].CP0_TCScheFBack;

}

target_ulong helper_mfc0_count (void)

{

    return (int32_t)cpu_mips_get_count(env);

}

target_ulong helper_mftc0_entryhi(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    int32_t tcstatus;

    if (other_tc == env->current_tc)

        tcstatus = env->active_tc.CP0_TCStatus;

    else

        tcstatus = env->tcs[other_tc].CP0_TCStatus;

    return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);

}

target_ulong helper_mftc0_status(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    target_ulong t0;

    int32_t tcstatus;

    if (other_tc == env->current_tc)

        tcstatus = env->active_tc.CP0_TCStatus;

    else

        tcstatus = env->tcs[other_tc].CP0_TCStatus;

    t0 = env->CP0_Status & ~0xf1000018;

    t0 |= tcstatus & (0xf << CP0TCSt_TCU0);

    t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);

    t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);

    return t0;

}

target_ulong helper_mfc0_lladdr (void)

{

    return (int32_t)env->CP0_LLAddr >> 4;

}

target_ulong helper_mfc0_watchlo (uint32_t sel)

{

    return (int32_t)env->CP0_WatchLo[sel];

}

target_ulong helper_mfc0_watchhi (uint32_t sel)

{

    return env->CP0_WatchHi[sel];

}

target_ulong helper_mfc0_debug (void)

{

    target_ulong t0 = env->CP0_Debug;

    if (env->hflags & MIPS_HFLAG_DM)

        t0 |= 1 << CP0DB_DM;

    return t0;

}

target_ulong helper_mftc0_debug(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    int32_t tcstatus;

    if (other_tc == env->current_tc)

        tcstatus = env->active_tc.CP0_Debug_tcstatus;

    else

        tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;

    /* XXX: Might be wrong, check with EJTAG spec. */

    return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |

            (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));

}

#if defined(TARGET_MIPS64)

target_ulong helper_dmfc0_tcrestart (void)

{

    return env->active_tc.PC;

}

target_ulong helper_dmfc0_tchalt (void)

{

    return env->active_tc.CP0_TCHalt;

}

target_ulong helper_dmfc0_tccontext (void)

{

    return env->active_tc.CP0_TCContext;

}

target_ulong helper_dmfc0_tcschedule (void)

{

    return env->active_tc.CP0_TCSchedule;

}

target_ulong helper_dmfc0_tcschefback (void)

{

    return env->active_tc.CP0_TCScheFBack;

}

target_ulong helper_dmfc0_lladdr (void)

{

    return env->CP0_LLAddr >> 4;

}

target_ulong helper_dmfc0_watchlo (uint32_t sel)

{

    return env->CP0_WatchLo[sel];

}

#endif /* TARGET_MIPS64 */

void helper_mtc0_index (target_ulong t0)

{

    int num = 1;

    unsigned int tmp = env->tlb->nb_tlb;

    do {

        tmp >>= 1;

        num <<= 1;

    } while (tmp);

    env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));

}

void helper_mtc0_mvpcontrol (target_ulong t0)

{

    uint32_t mask = 0;

    uint32_t newval;

    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))

        mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |

                (1 << CP0MVPCo_EVP);

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))

        mask |= (1 << CP0MVPCo_STLB);

    newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);

    // TODO: Enable/disable shared TLB, enable/disable VPEs.

    env->mvp->CP0_MVPControl = newval;

}

void helper_mtc0_vpecontrol (target_ulong t0)

{

    uint32_t mask;

    uint32_t newval;

    mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |

           (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);

    newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);

    /* Yield scheduler intercept not implemented. */

    /* Gating storage scheduler intercept not implemented. */

    // TODO: Enable/disable TCs.

    env->CP0_VPEControl = newval;

}

void helper_mtc0_vpeconf0 (target_ulong t0)

{

    uint32_t mask = 0;

    uint32_t newval;

    if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {

        if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))

            mask |= (0xff << CP0VPEC0_XTC);

        mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);

    }

    newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);

    // TODO: TC exclusive handling due to ERL/EXL.

    env->CP0_VPEConf0 = newval;

}

void helper_mtc0_vpeconf1 (target_ulong t0)

{

    uint32_t mask = 0;

    uint32_t newval;

    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))

        mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |

                (0xff << CP0VPEC1_NCP1);

    newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);

    /* UDI not implemented. */

    /* CP2 not implemented. */

    // TODO: Handle FPU (CP1) binding.

    env->CP0_VPEConf1 = newval;

}

void helper_mtc0_yqmask (target_ulong t0)

{

    /* Yield qualifier inputs not implemented. */

    env->CP0_YQMask = 0x00000000;

}

void helper_mtc0_vpeopt (target_ulong t0)

{

    env->CP0_VPEOpt = t0 & 0x0000ffff;

}

void helper_mtc0_entrylo0 (target_ulong t0)

{

    /* Large physaddr (PABITS) not implemented */

    /* 1k pages not implemented */

    env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;

}

void helper_mtc0_tcstatus (target_ulong t0)